Exeception Processing (e.g., Interrupts And Traps) Patents (Class 712/244)
  • Patent number: 11042468
    Abstract: A method for debugging a software program is provided when the software program is executed on a processor. An asynchronous debug event is detected. The asynchronous debug event is tracked through a data pipeline to the processor. In one embodiment, the asynchronous debug event is acted on only when the processor is ready to consume a data element associated with the asynchronous debug event.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: June 22, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Joseph Raymond Michael Zbiciak, Jason Lynn Peck
  • Patent number: 11011001
    Abstract: For configuring and installing access control devices at an installation site, configuration data for unidentified access control devices of the installation site is stored (S10) in a cloud-based computer system (1). The cloud-based computer system (1) receives (S2) a registration assigning the installation site to a media identifier stored in a setup media device. A particular one of the access control devices (4) at the installation site reads (S40) the media identifier stored in the setup media device (5). The media identifier from the particular access control device (4) is received (S5) in the cloud-based computer system (1). In the cloud-based computer system (1), the particular access control device (4) is mapped to one of the unidentified access control devices of the installation site. The configuration data of the mapped access control device is transmitted (S80) from the cloud-based computer system (1) to the particular access control device (4).
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: May 18, 2021
    Assignee: DORMAKABA SWITZERLAND LTD
    Inventors: Christian Kuster, Patrik Alessi
  • Patent number: 10983790
    Abstract: An arithmetic processing unit includes an instruction decoder, first to fourth reservation stations, first and second computing units, first and second load-store units, and an allocation unit. The allocation unit, when the execution instruction is a first instruction that is executable in first and second computing units but not executable in first and second load-store units, allocates the first instruction to first or second reservation station based on a first allocation table, and when the execution instruction is a second instruction that is executable in the first and second load-store units but not executable in the first and second computing units, allocates the second instruction to third or fourth reservation station based on a second allocation table.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: April 20, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Ryohei Okazaki
  • Patent number: 10984096
    Abstract: After a heuristic event counter in a processor has triggered a performance monitoring interrupt (PMI) when the processor was executing a target program in user mode, and after the processor has switched to kernel mode in response to the PMI, a heuristic event handler automatically performs preliminary analysis in kernel mode, without switching back to user mode, to determine whether heavyweight code analysis is warranted. The preliminary analysis comprises (a) obtaining an instruction pointer (IP) for the target program from a last branch record (LBR) buffer in the processor, (b) using transaction hardware in the processor to determine whether the IP from LBR buffer points to a readable page in memory, and (c) determining that heavyweight code analysis is not warranted in response to a determination that the page pointed to by the IP from LBR buffer is not readable. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Koichi Yamada, Sevin F. Varoglu, Ajay Harikumar, Alex Nayshtut
  • Patent number: 10956158
    Abstract: A method, processor and system for processing data is disclosed that includes evicting one or more evicted fields from a logical register mapper; receiving, by a history buffer, the one or more evicted fields from the logical register mapper; determining whether two or more of the evicted fields from the mapper qualify to be written to a single entry in the history buffer; and in response to the two or more evicted fields qualifying, writing the two or more qualifying evicted fields received from the mapper to a single entry in the qualified history buffer. The method, processor, and/or system further includes in an embodiment, remapping the one or more qualified evicted fields, and further, in response to the two or more evicted fields not qualifying to be written to a single entry in the history buffer, writing the two or more evicted fields to multiple history buffer entries.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Battle, Khandker N. Adeeb, Brian D. Barrick, Joshua W. Bowman, Thao T. Doan, Susan E. Eisen, Brandon Goddard, Dung Q. Nguyen
  • Patent number: 10949249
    Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: March 16, 2021
    Assignee: Renesas Electronics Corporation
    Inventor: Naotaka Maruyama
  • Patent number: 10942803
    Abstract: A method for performing data processing for error handling in a memory device, the memory device and the controller thereof, and the associated electronic device are provided. The method may include: programming a codeword of a set of data into a non-volatile (NV) memory, wherein the codeword includes the set of data and a parity-check code; reading the codeword from a volatile memory to generate readout data of the codeword; determining whether the readout data is correct according to the readout version of the set of data and the readout version of the parity-check code; and when determining that the readout data is correct, outputting the readout version of the set of data as the set of data for further usage of the processing circuit, otherwise, sending a predetermined signal to the processing circuit and storing error information regarding the set of data into a register of the controller.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: March 9, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Hung-En Hsieh, Che-Yi Wu
  • Patent number: 10853906
    Abstract: One embodiment provides an accelerator module comprising a memory stack including multiple memory dies; a graphics processing unit (GPU) coupled with the memory stack via one or more memory controllers, the GPU including a plurality of multiprocessors having a single instruction, multiple thread (SIMT) architecture, the multiprocessors to execute at least one single instruction. The at least one single instruction is to cause at least a portion of the GPU to perform a floating point operation on input having differing precisions. The floating point operation is a two-dimensional matrix multiply and accumulate operation.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Sara S. Baghsorkhi, Anbang Yao, Kevin Nealis, Xiaoming Chen, Altug Koker, Abhishek R. Appu, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Ben J. Ashbaugh, Barath Lakshmanan, Liwei Ma, Joydeep Ray, Ping T. Tang, Michael S. Strickland
  • Patent number: 10841095
    Abstract: The disclosure relates to a system, devices and methods for distributing and using a communication scheme to enable secure communication between communication nodes in a network. A method comprises determining, in the network node, a set of available IP addresses and a set of ports, dividing, in the network node, a time frame in time slots, associating, in the network node, each time slot with an IP address, with a port associated with the IP address and with a unique cryptographic key, distributing, from the network node, the communication scheme to the communication node, receiving, in the communication node, the communication scheme and communicating, in the communication node, with another communication node in possession of a corresponding communication scheme by hopping between the IP addresses and ports according to the communication scheme and encrypting the communication using the unique cryptographic key.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: November 17, 2020
    Assignee: SAAB AB
    Inventor: Mats Jonsson
  • Patent number: 10831563
    Abstract: A system for resolving a resource deadlock between processes. A shared data structure is maintained that includes process records of the processes. Process states and process priorities are defined for each of the processes. Values of the process states and process priorities are indicated in the process records. One or more aggregated states of the processes are defined. A respective state of the process is determined, by each process, based on at least one of the process states and process priorities of the process records, and the aggregated states of the processes. The respective state is used to allocate or deallocate resources to the process to mitigate and resolve the resource deadlock between the processes.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Lior Aronovich
  • Patent number: 10831626
    Abstract: A method for testing a multi-core integrated circuit device including a plurality of processing cores includes testing a first processing core on the integrated circuit device utilizing one or more tests. If a first feature on the first processing core fails a first test, the method includes performing a second test on the first processing core that tests the first processing core without the first feature. The method includes determining, based on the second test, if the first processing core is operable without the first feature. If the first processing core is operable without the first feature, the method includes storing information about the first processing core's capabilities in vital product data.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: James N. Klazynski, Douglas L. Lehr
  • Patent number: 10684887
    Abstract: The disclosure provides an approach for modifying a kernel by adding conditional halting points. The disclosure also provides an approach for modifying a kernel by implementing a virtual shared memory between an application running on a CPU and a workload running on a compute accelerator. The disclosure provides an approach for setting up the kernel and its working set on a compute accelerator, executing the workload, suspending the workload, and then resuming the workload at a later time, optionally on a different host computer.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: June 16, 2020
    Assignee: VMware, Inc.
    Inventor: Matthew D. McClure
  • Patent number: 10565003
    Abstract: When executed, a transaction-hint instruction specifies a transaction-count-to-completion (CTC) value for a transaction. The CTC value indicates how far a transaction is from completion. The CTC may be a number of instructions to completion or an amount of time to completion. The CTC value is adjusted as the transaction progresses. When a disruptive event associated with inducing transactional aborts, such as an interrupt or a conflicting memory access, is identified while processing the transaction, processing of the disruptive event is deferred if the adjusted CTC value satisfies deferral criteria. If the adjusted CTC value does not satisfy deferral criteria, the transaction is aborted and the disruptive event is processed.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael Karl Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 10521231
    Abstract: In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: December 31, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Lisa C. Heller, Damian Leo Osisek, Timothy J. Slegel
  • Patent number: 10516656
    Abstract: The invention relates to devices, methods, and computer program products for secure data communication according to a network protocol having a plurality of communication layers layered into a protocol stack. Said device comprises a processor system, in which a processor, controlled by a task scheduler, executes a plurality of autonomous software modules, which each run a communication layer of the protocol stack. The software modules are linked via communication channels to the protocol stack and the protocol stack is connected to an interface framework for data communication with an external network. At least one software module uses an assigned cryptographic key for secure data communication in its communication layer. The task scheduler is configured to obtain said key from the external network via the interface framework and to distribute said key to the assigned software module.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: December 24, 2019
    Inventor: Diethard Mahorka
  • Patent number: 10409920
    Abstract: A Computer-executable method, system, and computer program product for managing tiers of data storage in a data storage environment using a data storage system, the Computer-executable method, system, and computer program product comprising a non-transitory computer readable medium encoded with computer-executable program code for using read signatures in replication, the code configured to enable the execution of initializing a data stack, updating a map of the data stack; and distributing the map of the data stack to a compute node.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: September 10, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: John S. Harwood, Alexandr Veprinsky, Wai C. Yim, Erez Webman
  • Patent number: 10324725
    Abstract: The disclosure provides a method and a system for identifying and replacing code translations that generate spurious fault events. In one embodiment the method includes executing a first set and a second set of native instructions, performing a third translation of a target instruction to form a third set of native instructions in response to a determination that a fault occurrence is attributed to a first translation, wherein the third set of native instructions is not the same as the second set of native instructions, and the third set of native instructions is not the same as the first set of native instructions, and executing the third set of native instructions.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: June 18, 2019
    Assignee: Nvidia Corporation
    Inventors: Nathan Tuck, David Dunn, Ross Segelken, Madhu Swarna
  • Patent number: 10268534
    Abstract: Methods and systems to narrow a search for potential sources of problems in a distributed computing system are described. A volatile event type of event messages recorded in an event-log file is identified. The volatile event type is an event type that may have unexpectedly increased in frequency over an observation time window. An historical period of time may be selected to search for potential sources of the volatile event type. Frequencies of event messages in the event-log file with the same event type as the volatile event type are determined for time intervals of the historical period of time. A time interval of the historical period of time with a largest increase in frequency of event messages is identified. A list of event messages of the event-log file in a selected sub-time interval of the sub-time intervals of the time interval are displayed in a graphical user interface.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: April 23, 2019
    Assignee: VMware, Inc.
    Inventors: Darren Brown, Jeremy OlmstedThompson, Nicholas Kushmerick
  • Patent number: 10255656
    Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes sorting logic to sort processing threads into thread groups based on bit depth of floating point thread operations.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: April 9, 2019
    Assignee: INTEL CORPORATION
    Inventors: Abhishek R. Appu, Altug Koker, Linda L. Hurd, Dukhwan Kim, Mike B. Macpherson, John C. Weast, Feng Chen, Farshad Akhbari, Narayan Srinivasa, Nadathur Rajagopalan Satish, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman
  • Patent number: 10243727
    Abstract: The present disclosure presents methods, apparatuses, and systems to bolster communication security, and more particularly to utilize a constant time cryptographic co-processor engine for such communication security. For example, the disclosure includes a method for secure communication, comprising receiving encrypted data at a receiving device; obtaining a randomization for at least one bit of the encrypted data; modifying an execution of a cryptographic algorithm on the at least one bit to obtain a randomized cryptographic algorithm based on the randomization; and executing the randomized cryptographic algorithm on the at least one bit of encrypted data to recover original data associated with the encrypted data.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: March 26, 2019
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Winthrop Wu, James Goodman, Martin Kiernicki, Yoichi Shimokawa, William Thomas Morrison, Creighton Eldridge, David Kaplan
  • Patent number: 10223154
    Abstract: When executed, a transaction-hint instruction specifies a transaction-count-to-completion (CTC) value for a transaction. The CTC value indicates how far a transaction is from completion. The CTC may be a number of instructions to completion or an amount of time to completion. The CTC value is adjusted as the transaction progresses. When a disruptive event associated with inducing transactional aborts, such as an interrupt or a conflicting memory access, is identified while processing the transaction, processing of the disruptive event is deferred if the adjusted CTC value satisfies deferral criteria. If the adjusted CTC value does not satisfy deferral criteria, the transaction is aborted and the disruptive event is processed.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael Karl Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 10224271
    Abstract: A computer-implemented method includes, in a code transformation system, identifying save-to-return code instructions, function call code instructions, comparison code instructions, and exceptional code instructions. The function call code instructions are associated with the save-to-return code instructions. The comparison code instructions are associated with the save-to-return code instructions. The exceptional code instructions are associated with the comparison code instructions. A predefined proximity range based on a predefined proximity value as well as a proximity eligibility indicator are determined. The proximity eligibility indicator denotes whether the save-to-return code instructions and the comparison code instructions are within the predefined proximity range.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Iain A. Ireland, Allan H. Kielstra, Muntasir A. Mallick
  • Patent number: 10210019
    Abstract: When executed, a transaction-hint instruction specifies a transaction-count-to-completion (CTC) value for a transaction. The CTC value indicates how far a transaction is from completion. The CTC may be a number of instructions to completion or an amount of time to completion. The CTC value is adjusted as the transaction progresses. When a disruptive event associated with inducing transactional aborts, such as an interrupt or a conflicting memory access, is identified while processing the transaction, processing of the disruptive event is deferred if the adjusted CTC value satisfies deferral criteria. If the adjusted CTC value does not satisfy deferral criteria, the transaction is aborted and the disruptive event is processed.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael Karl Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 10127121
    Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices, where the load/store slices are coupled to the execution slices via a results bus. Operation of such a multi-slice processor includes: capturing first state information corresponding to a first set of control signals; monitoring state information of a plurality of logical components of the multi-slice processor; selecting, in dependence upon one or more selection criteria and upon the monitored state information, a second set of control signals; and capturing second state information corresponding to the second set of control signals, wherein the first set of control signals is different than the second set of control signals.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: November 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Khandker N. Adeeb, Steven J. Battle, Brandon R. Goddard, Dung Q. Nguyen, Tu-An T. Nguyen, Nicholas R. Orzol, Brian D. Victor, Brendan M. Wong
  • Patent number: 10120656
    Abstract: Embodiments of the present invention provide a system for the utilization of a robotic process automation system for functional evaluation and improvement of back end instructional constructs. The system may scan a set of code to identify an exception comprising an exception tag and an exception string located at a first location within the set of code. The system may then transmit the set of code and the identified exception to a robotic process automation system, along with instructions for the robotic process automation system to compare the exception tag and exception string to a replacement code database to identify an exception string. The robotic process automation system can then replace the exception string in the set of code with the identified replacement string.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: November 6, 2018
    Assignee: Bank of America Corporation
    Inventors: Awadhesh Pratap Singh, Samson Paulraj, Suki Ramasamy
  • Patent number: 10102015
    Abstract: A computing device for just-in-time cross-compiling compiled binaries of application programs that utilize graphics processing unit (GPU) executed programs configured to be executed on a first GPU having a first instruction set architecture (ISA), the computing device including a second GPU having a second ISA different from the first ISA of the first GPU, and a processor configured to execute an application program that utilizes a plurality of GPU-executed programs configured to be executed for the first ISA of the first GPU, execute a run-time executable cross-compiler configured to, while the application program is being executed, translate compiled binary of the plurality of GPU-executed programs from the first ISA to the second ISA, and execute the translated plurality of GPU-executed programs on the second GPU.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: October 16, 2018
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Matthew Gordon, Eric David Heutchy
  • Patent number: 10083125
    Abstract: Software-managed resources are used to utilize effective-to-real memory address translation for synchronization among processes executing on processor cores in a multi-core computing system. A failure to find a pre-determined effective memory address translation in an effective-to-real memory address translation table on a first processor core triggers an address translation exception in a second processor core and causes an exception handler on the second processor core to start a new process, thereby acting as a means to achieve synchronization among processes on the first processor core and the second processor core. The specific functionality is implemented in the exception handler, which is tailored to respond to the exception based on the address that generated it.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: September 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tong Chen, John Kevin O'Brien, Zehra Noman Sura
  • Patent number: 10055251
    Abstract: Mechanisms for injecting code into embedded devices are provided. In some embodiments, once the code is injected into the embedded device, the injected code can analyze and modify the code of the embedded device (e.g., firmware) to create the execution environment for the injected code. For example, the injected code can identify program instruction locations in the code of the embedded device into which jump instructions can be placed. The injected code can also insert at least one jump instruction at an identified program instruction location in the code of the embedded device. In response to the execution of a jump instruction, the injected code can save a context of the code of the embedded device to memory and loading a payload context into a processor of the embedded device. The payload context can then be executed by the processor of the embedded device.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: August 21, 2018
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Ang Cui, Salvatore J. Stolfo
  • Patent number: 9983932
    Abstract: A pipeline processor which meets a latency restriction on an equal model is provided. The pipeline processor includes a pipeline processing unit to process an instruction at a plurality of stages and an equal model compensator to store the results of the processing of some or all of the instructions located in the pipeline processing unit and to write the results of the processing in a register file based on the latency of each instruction.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: May 29, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Heejun Shim, Yenjo Han, Jae-Young Kim, Yeon-Gon Cho, Jinseok Lee
  • Patent number: 9977417
    Abstract: A method and a system for optimizing utilization of a programmable logic element for use in an electronic control unit for vehicles, wherein the programmable logic element has a soft CPU and/or an unused remaining area. A plurality of model variants is generated that reproduce functionality of the control unit, and generate a plurality of soft CPU configurations with differing configuration scope, which occupy an area corresponding to the configuration scope of the programmable logic element, and execute processor-in-the-loop simulations for the plurality of model variants and/or soft CPU configurations after instantiation of the soft CPU corresponding to the soft CPU configuration on a programmable logic element. The profiling data acquired for the soft CPU during the PIL simulation is used with regard to the processing of the input signal for optimizing utilization of the programmable logic element.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: May 22, 2018
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventor: Olaf Grajetzky
  • Patent number: 9934034
    Abstract: State machine engines are disclosed, including those having an instruction insertion register. One such instruction insertion register may provide an initialization instruction, such as to prepare a state machine engine for data analysis. An instruction insertion register may also provide an instruction in an attempt to resolve an error that occurs during operation of a state machine engine. An instruction insertion register may also be used to debug a state machine engine, such as after the state machine experiences a fatal error.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: April 3, 2018
    Assignee: Micron Technology, Inc.
    Inventor: David R. Brown
  • Patent number: 9934075
    Abstract: Technologies are generally described for task management on computing platforms. In some examples, a method performed under control of a task management system may include determining a relationship among a plurality of tasks executed on a first platform to identify one or more associated tasks; identifying at least one attribute of each of the one or more associated tasks; generating a job that includes the one or more associated tasks and the identified at least one attribute of each of the one or more associated tasks; and instantiating, on a second platform, the one or more associated tasks included in the job based on the at least one attribute of each of the one or more associated tasks, in response to a request to launch the job.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 3, 2018
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Yang-Won Jung
  • Patent number: 9930133
    Abstract: A system and method for managing application performance includes a storage controller including a memory containing machine readable medium comprising machine executable code having stored thereon instructions for performing a method of managing application performance and a processor coupled to the memory. The processor is configured to execute the machine executable code to receive storage requests from a plurality of first applications via a network interface, manage QoS settings for the storage controller and the first applications, and in response to receiving an accelerate command associated with a second application from the first applications, increase a first share of a storage resource allocated to the second application, decrease unlocked second shares of the storage resource of the first applications, and lock the first share. The storage resource is a request queue or a first cache. In some embodiments, the second application is a throughput application or a latency application.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: March 27, 2018
    Assignee: NetApp, Inc.
    Inventors: Sai Rama Krishna Susarla, Scott Hubbard, William Patrick Delaney, Rodney A. Dekoning
  • Patent number: 9836325
    Abstract: One embodiment of the present disclosure sets forth an effective way to maintain fairness and order in the scheduling of common resource access requests related to replay operations. Specifically, a streaming multiprocessor (SM) includes a total order queue (TOQ) configured to schedule the access requests over one or more execution cycles. Access requests are allowed to make forward progress when needed common resources have been allocated to the request. Where multiple access requests require the same common resource, priority is given to the older access request. Access requests may be placed in a sleep state pending availability of certain common resources. Deadlock may be avoided by allowing an older access request to steal resources from a younger resource request. One advantage of the disclosed technique is that older common resource access requests are not repeatedly blocked from making forward progress by newer access requests.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: December 5, 2017
    Assignee: NVIDIA Corporation
    Inventors: Michael Fetterman, Shirish Gadre, John H. Edmondson, Omkar Paranjape, Anjana Rajendran, Eric Lyell Hill, Rajeshwaran Selvanesan, Charles McCarver, Kevin Mitchell, Steven James Heinrich
  • Patent number: 9804896
    Abstract: Techniques described herein are generally related to thread migration across processing cores of a multi-core processor. Execution of a thread may be migrated from a first processing core to a second processing core. Selective state data required for execution of the thread on the second processing core can be identified and can be dynamically acquired from the first processing core. The acquired state data can be utilized by the thread executed on the second processing core.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: October 31, 2017
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Sriram Vajapeyam
  • Patent number: 9680720
    Abstract: Network traffic that includes an Operations, Administration, and Maintenance (OAM) unit is received. A first data flow to which the OAM data unit belongs is identified from among a plurality of data flows of network traffic. Based on identifying the first flow of communication traffic to which the OAM data unit belongs, a first entry corresponding to the first flow is retrieved from a memory that stores OAM action data including a plurality of entries indicating how OAM data units in different flows of communication traffic are to be processed. The first entry is from among the plurality of entries and indicates how OAM data units in the first flow are to be processed, including whether the network device should modify the data unit as part of an OAM action. The OAM data unit is processed in accordance with the first entry.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: June 13, 2017
    Assignee: Marvell Israel (M.I.S.L.) Ltd.
    Inventors: Tal Mizrahi, David Melman
  • Patent number: 9619237
    Abstract: Embodiments relate to speculative branch handling for transaction abort. An aspect includes detecting a beginning of a current execution of a transaction. Another aspect includes, based on detecting the beginning of the transaction, disabling speculative execution based on branch prediction of an initial branch instruction of the transaction, wherein the initial branch instruction branches to two possible paths, and wherein a first path of the two possible paths comprises an abort handler. Another aspect includes disabling updating of a history table for the initial branch instruction.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: April 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael Billeci, James J. Bonanno, Adam B. Collura, Christian Jacobi, Anthony Saporito, Timothy J. Slegel
  • Patent number: 9594648
    Abstract: In one embodiment, the present invention includes a method for controlling redundant execution such that if an exceptional event occurs, the redundant execution is stopped, non-redundant execution is performed in one of the threads until the exceptional event has been-resolved, after which a state of the threads is synchronized, and redundant execution is continued. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: March 14, 2017
    Assignee: Intel Corporation
    Inventors: Glenn J. Hinton, Steven E. Raasch, Sebastien Hily, John G. Holm, Ronak Singhal, Avinash Sodani, Deborah T. Marr
  • Patent number: 9558001
    Abstract: Methods and reservation stations for selecting instructions to issue to a functional unit of an out-of-order processor. The method includes classifying each instruction into one of a number of categories based on the type of instruction. Once classified an instruction is stored in an instruction queue corresponding to the category in which it was classified. Instructions are then selected from one or more of the instruction queues to issue to the functional unit based on a relative priority of the plurality of types of instructions. This allows certain types of instructions (e.g. control transfer instructions, flag setting instructions and/or address generation instructions) to be prioritized over other types of instructions even if they are younger.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: January 31, 2017
    Assignee: Imagination Technologies Limited
    Inventors: Anand Khot, Hugh Jackson
  • Patent number: 9552285
    Abstract: Micro-execution is the ability to run any code segment in isolation. Implementations for micro-execution of code segments are described. A test engine determines an effective address of a memory operation of an instruction of an executable program. The test engine determines, prior to performing the memory operation and based on a memory policy, that the effective address is to be replaced with a replacement address. Based on determining that the effective address is to be replaced, the test engine allocates the replacement address and executes the instruction based on the allocated replacement address.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: January 24, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Patrice Godefroid
  • Patent number: 9552250
    Abstract: Discovering a hardware failure in a processor is disclosed. When an operating system or application fails, a function containing the instruction that failed along with the register set of the CPU at the failure is recorded. The function is analyzed into its basic blocks. The failing instruction, the failing basic block, the definitions that reach the failing instruction, and the CPU register set at the failure provide information to determine whether the failure was caused by hardware or software. If, after a complete search of the definitions reaching the failing instruction, the search discovers a first definition defining the failing instruction and a second definition defining the first definition such that the second definition reaches the failing instruction and the first definition assigns a register value that does not match a register value in the failing instruction, then a hardware failure is the cause of the crash.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: January 24, 2017
    Assignee: VMware, Inc.
    Inventors: Hariprakash Govindarajalu, Yujie Chen, Sowgandh Sunil Gadi, Ravi Parimi
  • Patent number: 9547595
    Abstract: A transactional memory system salvages hardware lock elision (HLE) transactions. A computer system of the transactional memory system records information about locks elided to begin HLE transactional execution of first and second transactional code regions. The computer system detects a pending cache line conflict of a cache line, and based on the detecting stops execution of the first code region of the first transaction and the second code region of the second transaction. The computer system determines that the first lock and the second lock are different locks and uses the recorded information about locks elided to acquire the first lock of the first transaction and the second lock of the second transaction. The computer system commits speculative state of the first transaction and the second transaction and the computer system continues execution of the first code region and the second code region non-transactionally.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: January 17, 2017
    Assignee: International Business Machines Corporation
    Inventors: Harold W. Cain, III, Michael Karl Gschwind, Maged M. Michael, Chung-Lung K. Shum
  • Patent number: 9535697
    Abstract: The present embodiments provide a system that facilitates lazy register window fills in a processor. During program execution, when the system encounters a restore instruction for a register window, the system determines if the restore instruction causes an underflow condition that requires the register window to be filled from a stack in memory. If so, the system completes the restore instruction by updating state information for the register window to indicate that the restore instruction is complete without actually filling the individual registers that comprise the register window from the stack. During subsequent program execution, the system lazily fills registers in the register window from the stack as the registers are accessed by the program.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: January 3, 2017
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventor: Yuan C. Chou
  • Patent number: 9535926
    Abstract: A server computer system performs a first set of operations for a first transaction. The first transaction pertaining to data stored in a file system. The server computer system delays a second set of operations for the first transaction and identifies a second transaction pertaining to the data. In response to identifying the second transaction, the server computer system cancels the second set of operations for the first transaction, and cancels a first set of operations for the second transaction.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: January 3, 2017
    Assignee: Red Hat, Inc.
    Inventors: Anand Vishweswaran Avati, Pranith Kumar Karampuri
  • Patent number: 9521952
    Abstract: A position of a light absorber existing in a subject and an initial sound pressure of an acoustic wave generated at the light absorber are calculated from an electric signal converted from the received acoustic wave generated in response to irradiation of the subject with light. An optical absorption coefficient and an optical scattering coefficient of the subject are calculated using the position of the light absorber and the initial sound pressure of the acoustic wave generated at the position of the light absorber. A light quantity distribution in the subject is calculated using the optical absorption coefficient and the optical scattering coefficient of the subject. An optical absorption coefficient distribution in the subject is calculated using the light quantity distribution in the subject and an initial sound pressure distribution in the subject obtained from the electric signal.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: December 20, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takuro Miyasato
  • Patent number: 9483323
    Abstract: Providing unblocked read operations concurrent with write operations with respect to shared data resources in parallel processing systems. In an embodiment, for each data resource, a pair of fields and an index field is maintained. The index field indicates which of the two fields (e.g., first field) stores a current value for the data resource. However, when a new value is to be stored for the data resource, the value is first stored in the second field using a execution entity, while ensuring exclusive access for the execution entity to the second field. The index field is then updated to indicate that the second field stores the current value, such that the new value in the second field is thereafter available as the current value for read operations. All read operations by any corresponding concurrent execution entities, during the write operation, are continued unblocked.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: November 1, 2016
    Assignee: Oracle International Corporation
    Inventor: Giridhar Narasimhamurthy
  • Patent number: 9454377
    Abstract: Embodiments relate to speculative branch handling for transaction abort. An aspect includes detecting a beginning of a current execution of a transaction. Another aspect includes, based on detecting the beginning of the transaction, disabling speculative execution based on branch prediction of an initial branch instruction of the transaction, wherein the initial branch instruction branches to two possible paths, and wherein a first path of the two possible paths comprises an abort handler. Another aspect includes disabling updating of a history table for the initial branch instruction.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: September 27, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael Billeci, James J. Bonanno, Adam B. Collura, Christian Jacobi, Anthony Saporito, Timothy J. Siegel
  • Patent number: 9424090
    Abstract: Systems and methods provide a processing task load and type adaptive manycore processor architecture, enabling flexible and efficient information processing. The architecture enables executing time variable sets of information processing tasks of differing types on their assigned processing cores of matching types. This involves: for successive core allocation periods (CAPs), selecting specific processing tasks for execution on the cores of the manycore processor for a next CAP based at least in part on core capacity demand expressions associated with the processing tasks hosted on the processor, assigning the selected tasks for execution at cores of the processor for the next CAP so as to maximize the number of processor cores whose assigned tasks for the present and next CAP are associated with same core type, and reconfiguring the cores so that a type of each core in said array matches a type of its assigned task on the next CAP.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: August 23, 2016
    Assignee: THROUGHPUTER, INC.
    Inventor: Mark Henrik Sandstrom
  • Patent number: 9405637
    Abstract: An embodiment of the invention provides a method for changing a multi-processor system from a performance mode to a safety mode while the system continues to run software. When an external event or exception occurs, context is switched from the performance mode to the safety mode. After context is switched, at least one pair of CPUs is synchronized to operate in the safety mode. In addition, a multi-processor system may be switched form the safety mode to the performance mode while the software continues to operate.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: August 2, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Alexandre Pierre Palus
  • Patent number: 9405544
    Abstract: A system and method for efficient branch prediction. A processor includes a next fetch predictor to generate a fast branch prediction for branch instructions at an early pipeline stage. The processor also includes a main return address stack (RAS) at a later pipeline stage for predicting the target of return instructions. When a return instruction is encountered, the prediction from the next fetch predictor is replaced by the top of the main RAS. If there are any recent call or return instructions in flight toward the main RAS, then a separate prediction is generated by a mini-RAS.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: August 2, 2016
    Assignee: Apple Inc.
    Inventors: Douglas C. Holman, Ramesh B. Gunna, Conrado Blasco-Allue