Abstract: Embodiments are directed to a phased boot process to dynamically initialize devices in a verified environment. An embodiment of a system includes a memory device to store platform initialization firmware to cause the processing system to: initialize, during a boot process, a portion of the one or more memory modules as system management random access memory (SMRAM) for system management mode (SMM) usage; generate an SMM component in the SMRAM, the SMM component comprising an SMM handler routine to handle dynamic intellectual property (IP) management operations corresponding to the plurality of hardware components; register the SMM handler routine with an SMM interrupt (SMI) for identification of SMM events from an operating system (OS); and generate an SMM dispatcher in the SMRAM, the SMM dispatcher to create an instance of the SMM handler routine in the SMRAM in response to receiving an SMI from the OS during runtime of the processing system.

Abstract: The present disclosure relates to a mechanism for issuing instructions in a processor (e.g., a vector processor) implemented as an overlay on programmable hardware (e.g., a field programmable gate array (FPGA) device). Implementations described herein include features for optimizing resource availability on programmable hardware units and enabling superscalar execution when coupled with a temporal single-instruction multiple data (SIMD). Systems described herein involve an issue component of a processor controller (e.g., a vector processor controller) that enables fast and efficient instruction issue while verifying that structural and data hazards between instructions have been resolved.

Abstract: An apparatus to facilitate thread scheduling is disclosed. In one embodiment the apparatus includes a processor comprising a plurality of multiprocessors comprising single-instruction multiple thread (SIMT) execution circuitry to simultaneously execute multiple threads, a shared local memory to be shared by the multiple threads, and scheduling hardware logic to schedule the multiple threads in a thread group for execution across the plurality of multiprocessors in accordance with barrier data. The instructions of the multiple threads are to produce shared data to be stored in the shared local memory when executed by the plurality of multiprocessors, wherein additional instructions of at least a first thread of the multiple threads are to use the shared data, and wherein, in accordance with the barrier data, the first thread is to wait for other threads of the multiple threads to finish producing the shared data before executing the additional instructions.

Abstract: A computer implemented method, performed in a data processing system comprising a performance monitoring unit. The method comprises receiving a set of computer-readable instructions to be executed by the data processing system to implement at least a portion of a neural network, wherein one or more of the instructions is labeled with one or more performance monitoring labels based upon one or more features of the neural network. The method further comprises configuring the performance monitoring unit to count one or more events occurring in one or more components of the data processing system based on the one or more performance monitoring labels.

Abstract: An image forming apparatus includes a housing having a first section and a second section opposite to the first section in a particular direction, a print engine, a user interface disposed at the first section, a memory interface having a plurality of ports including a first port disposed at the first section and a second port disposed at the second section, and a controller. The controller is configured to perform a storage printing process, prior to the storage printing process, set one of the plurality of ports as a dedicated port used in the storage printing process, when the second port is set as the dedicated port, determine whether the second port is in a notified status, and when determining that the second port is in the notified status, cause the user interface to display a notification screen.

Abstract: A method and system are provided for configurable computation and data processing. A logical processor includes an array of logic elements. The processor may be a combinatorial circuit that can be applied to modify computational aspects of an array of reconfigurable circuits. A memory stores a plurality of instructions, each instruction including an instruction-fetch data portion and an output data transfer data portion. One or more memory controllers are coupled to the memory and receive instructions and/or output data from the memory. A back buffer is coupled with the memory controller and receives instructions from the memory controller. The back buffer sequentially asserts each received instruction upon one or more memory controllers. The memory controllers transfer data received from the memory to a target, such as an array of reconfigurable logic circuits that are optionally coupled to the memory, the back buffer, and one or more additional memory controllers.

Abstract: A method for identifying a function of an operating system kernel of a virtual machine. The method includes: identifying an initial instruction included in the code of the operating system kernel of the virtual machine, and locating at least one following block of instructions belonging to a function of the operating system kernel of the virtual machine, the following block being situated in a memory area following the initial instruction; locating at least one preceding block of instructions belonging to a function of the operating system kernel, the proceeding block situated in a memory area preceding the initial instruction; identifying a first block and a last block of instructions of the function of the operating system kernel from among the at least one following and preceding blocks, and recording start and end function addresses in association with the function of the operating system kernel.

Abstract: According to one example, a method performed by a physical computing system includes, with a hypervisor, detecting that a guest system running on a virtual machine has executed a halt instruction for a virtual processor of the virtual machine. The method further includes, with a physical processor, switching from a context of the virtual machine to a context of the hypervisor. The method further includes re-entering the context of the virtual machine in response to determining that there are no tasks pending for processes outside the context of the virtual machine, the processes being for execution by the physical processor.

Abstract: Embodiments relate to a system, program product, and method for random generation of recoverable errors in the generated instruction stream for post-silicon validation testing. The intentional raising and handling of exceptions in post-silicon validation exercisers randomly creates recoverable errors in a generated instruction test stream. Multiple exceptions may be raised either in a single instruction or in multiple instructions, while the present instruction is permitted to fully execute. The errors responsible for raising the exceptions are automatically repaired.

Abstract: The present disclosure is directed to a system for on-demand binary translation state map generation. Instead of interpreting the native code to be executed, binary translation circuitry (BT circuitry) may execute a binary translation (BT) in place of the native code. When a stop occurs (e.g., due to an interrupt, a modification of the native code, etc.), the BT circuitry may generate a binary translation state map (BT state map) that allows the location of the stop to be mapped back to the native code. Generation of the BT state map may involve determining a location and offset for the stop, performing region formation based on the location, loading instructions from the region (e.g., while accounting for the need to emulate instructions), forming the BT state map based at least on the size of the loaded instructions, and then mapping the stop back to the native code utilizing the offset.

Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.

Abstract: Processing circuitry (8) processes software processes at one of a plurality of exception levels and in one of a plurality of realms, each realm corresponding to a portion of at least one software process and being associated with a boundary exception level indicating a most privileged exception level at which the realm can be processed by the processing circuitry (8). In response to a realm exiting exception condition during processing of a given realm, where the exception condition is to be handled by an exception handler at a more privileged exception level than the boundary exception level of the given realm, the processing circuitry (8) performs state masking to make inaccessible, to software processes processed at a more privileged exception level than the boundary exception level, architectural state of a subset of registers selected depending on the boundary exception level of the given realm.

Abstract: A system and technique are provided for providing a service address space. The system includes a service co-processor provided with a service address space. The service co-processor is attached to a main processor where the main processor is provided with a main address space. The service co-processor creates and maintains an independent copy of the main address space in the form of the service address space. The service co-processor receives from the main processor a command packet, determines a clock value for initiating a service function designated by the command packet, and updates the service address space until reaching the clock value. The service co-processor then performs the service function at the clock value.

Abstract: A method for debugging a software program is provided when the software program is executed on a processor. An asynchronous debug event is detected. The asynchronous debug event is tracked through a data pipeline to the processor. In one embodiment, the asynchronous debug event is acted on only when the processor is ready to consume a data element associated with the asynchronous debug event.

Abstract: For configuring and installing access control devices at an installation site, configuration data for unidentified access control devices of the installation site is stored (S10) in a cloud-based computer system (1). The cloud-based computer system (1) receives (S2) a registration assigning the installation site to a media identifier stored in a setup media device. A particular one of the access control devices (4) at the installation site reads (S40) the media identifier stored in the setup media device (5). The media identifier from the particular access control device (4) is received (S5) in the cloud-based computer system (1). In the cloud-based computer system (1), the particular access control device (4) is mapped to one of the unidentified access control devices of the installation site. The configuration data of the mapped access control device is transmitted (S80) from the cloud-based computer system (1) to the particular access control device (4).

Abstract: After a heuristic event counter in a processor has triggered a performance monitoring interrupt (PMI) when the processor was executing a target program in user mode, and after the processor has switched to kernel mode in response to the PMI, a heuristic event handler automatically performs preliminary analysis in kernel mode, without switching back to user mode, to determine whether heavyweight code analysis is warranted. The preliminary analysis comprises (a) obtaining an instruction pointer (IP) for the target program from a last branch record (LBR) buffer in the processor, (b) using transaction hardware in the processor to determine whether the IP from LBR buffer points to a readable page in memory, and (c) determining that heavyweight code analysis is not warranted in response to a determination that the page pointed to by the IP from LBR buffer is not readable. Other embodiments are described and claimed.

Abstract: An arithmetic processing unit includes an instruction decoder, first to fourth reservation stations, first and second computing units, first and second load-store units, and an allocation unit. The allocation unit, when the execution instruction is a first instruction that is executable in first and second computing units but not executable in first and second load-store units, allocates the first instruction to first or second reservation station based on a first allocation table, and when the execution instruction is a second instruction that is executable in the first and second load-store units but not executable in the first and second computing units, allocates the second instruction to third or fourth reservation station based on a second allocation table.

Abstract: A method, processor and system for processing data is disclosed that includes evicting one or more evicted fields from a logical register mapper; receiving, by a history buffer, the one or more evicted fields from the logical register mapper; determining whether two or more of the evicted fields from the mapper qualify to be written to a single entry in the history buffer; and in response to the two or more evicted fields qualifying, writing the two or more qualifying evicted fields received from the mapper to a single entry in the qualified history buffer. The method, processor, and/or system further includes in an embodiment, remapping the one or more qualified evicted fields, and further, in response to the two or more evicted fields not qualifying to be written to a single entry in the history buffer, writing the two or more evicted fields to multiple history buffer entries.

Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.

Abstract: A method for performing data processing for error handling in a memory device, the memory device and the controller thereof, and the associated electronic device are provided. The method may include: programming a codeword of a set of data into a non-volatile (NV) memory, wherein the codeword includes the set of data and a parity-check code; reading the codeword from a volatile memory to generate readout data of the codeword; determining whether the readout data is correct according to the readout version of the set of data and the readout version of the parity-check code; and when determining that the readout data is correct, outputting the readout version of the set of data as the set of data for further usage of the processing circuit, otherwise, sending a predetermined signal to the processing circuit and storing error information regarding the set of data into a register of the controller.

Abstract: One embodiment provides an accelerator module comprising a memory stack including multiple memory dies; a graphics processing unit (GPU) coupled with the memory stack via one or more memory controllers, the GPU including a plurality of multiprocessors having a single instruction, multiple thread (SIMT) architecture, the multiprocessors to execute at least one single instruction. The at least one single instruction is to cause at least a portion of the GPU to perform a floating point operation on input having differing precisions. The floating point operation is a two-dimensional matrix multiply and accumulate operation.

Abstract: The disclosure relates to a system, devices and methods for distributing and using a communication scheme to enable secure communication between communication nodes in a network. A method comprises determining, in the network node, a set of available IP addresses and a set of ports, dividing, in the network node, a time frame in time slots, associating, in the network node, each time slot with an IP address, with a port associated with the IP address and with a unique cryptographic key, distributing, from the network node, the communication scheme to the communication node, receiving, in the communication node, the communication scheme and communicating, in the communication node, with another communication node in possession of a corresponding communication scheme by hopping between the IP addresses and ports according to the communication scheme and encrypting the communication using the unique cryptographic key.

Abstract: A method for testing a multi-core integrated circuit device including a plurality of processing cores includes testing a first processing core on the integrated circuit device utilizing one or more tests. If a first feature on the first processing core fails a first test, the method includes performing a second test on the first processing core that tests the first processing core without the first feature. The method includes determining, based on the second test, if the first processing core is operable without the first feature. If the first processing core is operable without the first feature, the method includes storing information about the first processing core's capabilities in vital product data.

Abstract: A system for resolving a resource deadlock between processes. A shared data structure is maintained that includes process records of the processes. Process states and process priorities are defined for each of the processes. Values of the process states and process priorities are indicated in the process records. One or more aggregated states of the processes are defined. A respective state of the process is determined, by each process, based on at least one of the process states and process priorities of the process records, and the aggregated states of the processes. The respective state is used to allocate or deallocate resources to the process to mitigate and resolve the resource deadlock between the processes.

Abstract: The disclosure provides an approach for modifying a kernel by adding conditional halting points. The disclosure also provides an approach for modifying a kernel by implementing a virtual shared memory between an application running on a CPU and a workload running on a compute accelerator. The disclosure provides an approach for setting up the kernel and its working set on a compute accelerator, executing the workload, suspending the workload, and then resuming the workload at a later time, optionally on a different host computer.

Abstract: When executed, a transaction-hint instruction specifies a transaction-count-to-completion (CTC) value for a transaction. The CTC value indicates how far a transaction is from completion. The CTC may be a number of instructions to completion or an amount of time to completion. The CTC value is adjusted as the transaction progresses. When a disruptive event associated with inducing transactional aborts, such as an interrupt or a conflicting memory access, is identified while processing the transaction, processing of the disruptive event is deferred if the adjusted CTC value satisfies deferral criteria. If the adjusted CTC value does not satisfy deferral criteria, the transaction is aborted and the disruptive event is processed.

Abstract: In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.

Abstract: The invention relates to devices, methods, and computer program products for secure data communication according to a network protocol having a plurality of communication layers layered into a protocol stack. Said device comprises a processor system, in which a processor, controlled by a task scheduler, executes a plurality of autonomous software modules, which each run a communication layer of the protocol stack. The software modules are linked via communication channels to the protocol stack and the protocol stack is connected to an interface framework for data communication with an external network. At least one software module uses an assigned cryptographic key for secure data communication in its communication layer. The task scheduler is configured to obtain said key from the external network via the interface framework and to distribute said key to the assigned software module.

Abstract: A Computer-executable method, system, and computer program product for managing tiers of data storage in a data storage environment using a data storage system, the Computer-executable method, system, and computer program product comprising a non-transitory computer readable medium encoded with computer-executable program code for using read signatures in replication, the code configured to enable the execution of initializing a data stack, updating a map of the data stack; and distributing the map of the data stack to a compute node.

Abstract: The disclosure provides a method and a system for identifying and replacing code translations that generate spurious fault events. In one embodiment the method includes executing a first set and a second set of native instructions, performing a third translation of a target instruction to form a third set of native instructions in response to a determination that a fault occurrence is attributed to a first translation, wherein the third set of native instructions is not the same as the second set of native instructions, and the third set of native instructions is not the same as the first set of native instructions, and executing the third set of native instructions.

Abstract: Methods and systems to narrow a search for potential sources of problems in a distributed computing system are described. A volatile event type of event messages recorded in an event-log file is identified. The volatile event type is an event type that may have unexpectedly increased in frequency over an observation time window. An historical period of time may be selected to search for potential sources of the volatile event type. Frequencies of event messages in the event-log file with the same event type as the volatile event type are determined for time intervals of the historical period of time. A time interval of the historical period of time with a largest increase in frequency of event messages is identified. A list of event messages of the event-log file in a selected sub-time interval of the sub-time intervals of the time interval are displayed in a graphical user interface.

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes sorting logic to sort processing threads into thread groups based on bit depth of floating point thread operations.

Abstract: The present disclosure presents methods, apparatuses, and systems to bolster communication security, and more particularly to utilize a constant time cryptographic co-processor engine for such communication security. For example, the disclosure includes a method for secure communication, comprising receiving encrypted data at a receiving device; obtaining a randomization for at least one bit of the encrypted data; modifying an execution of a cryptographic algorithm on the at least one bit to obtain a randomized cryptographic algorithm based on the randomization; and executing the randomized cryptographic algorithm on the at least one bit of encrypted data to recover original data associated with the encrypted data.

Abstract: When executed, a transaction-hint instruction specifies a transaction-count-to-completion (CTC) value for a transaction. The CTC value indicates how far a transaction is from completion. The CTC may be a number of instructions to completion or an amount of time to completion. The CTC value is adjusted as the transaction progresses. When a disruptive event associated with inducing transactional aborts, such as an interrupt or a conflicting memory access, is identified while processing the transaction, processing of the disruptive event is deferred if the adjusted CTC value satisfies deferral criteria. If the adjusted CTC value does not satisfy deferral criteria, the transaction is aborted and the disruptive event is processed.

Abstract: A computer-implemented method includes, in a code transformation system, identifying save-to-return code instructions, function call code instructions, comparison code instructions, and exceptional code instructions. The function call code instructions are associated with the save-to-return code instructions. The comparison code instructions are associated with the save-to-return code instructions. The exceptional code instructions are associated with the comparison code instructions. A predefined proximity range based on a predefined proximity value as well as a proximity eligibility indicator are determined. The proximity eligibility indicator denotes whether the save-to-return code instructions and the comparison code instructions are within the predefined proximity range.

Abstract: When executed, a transaction-hint instruction specifies a transaction-count-to-completion (CTC) value for a transaction. The CTC value indicates how far a transaction is from completion. The CTC may be a number of instructions to completion or an amount of time to completion. The CTC value is adjusted as the transaction progresses. When a disruptive event associated with inducing transactional aborts, such as an interrupt or a conflicting memory access, is identified while processing the transaction, processing of the disruptive event is deferred if the adjusted CTC value satisfies deferral criteria. If the adjusted CTC value does not satisfy deferral criteria, the transaction is aborted and the disruptive event is processed.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices, where the load/store slices are coupled to the execution slices via a results bus. Operation of such a multi-slice processor includes: capturing first state information corresponding to a first set of control signals; monitoring state information of a plurality of logical components of the multi-slice processor; selecting, in dependence upon one or more selection criteria and upon the monitored state information, a second set of control signals; and capturing second state information corresponding to the second set of control signals, wherein the first set of control signals is different than the second set of control signals.

Abstract: Embodiments of the present invention provide a system for the utilization of a robotic process automation system for functional evaluation and improvement of back end instructional constructs. The system may scan a set of code to identify an exception comprising an exception tag and an exception string located at a first location within the set of code. The system may then transmit the set of code and the identified exception to a robotic process automation system, along with instructions for the robotic process automation system to compare the exception tag and exception string to a replacement code database to identify an exception string. The robotic process automation system can then replace the exception string in the set of code with the identified replacement string.

Abstract: A computing device for just-in-time cross-compiling compiled binaries of application programs that utilize graphics processing unit (GPU) executed programs configured to be executed on a first GPU having a first instruction set architecture (ISA), the computing device including a second GPU having a second ISA different from the first ISA of the first GPU, and a processor configured to execute an application program that utilizes a plurality of GPU-executed programs configured to be executed for the first ISA of the first GPU, execute a run-time executable cross-compiler configured to, while the application program is being executed, translate compiled binary of the plurality of GPU-executed programs from the first ISA to the second ISA, and execute the translated plurality of GPU-executed programs on the second GPU.

Abstract: Software-managed resources are used to utilize effective-to-real memory address translation for synchronization among processes executing on processor cores in a multi-core computing system. A failure to find a pre-determined effective memory address translation in an effective-to-real memory address translation table on a first processor core triggers an address translation exception in a second processor core and causes an exception handler on the second processor core to start a new process, thereby acting as a means to achieve synchronization among processes on the first processor core and the second processor core. The specific functionality is implemented in the exception handler, which is tailored to respond to the exception based on the address that generated it.

Abstract: Mechanisms for injecting code into embedded devices are provided. In some embodiments, once the code is injected into the embedded device, the injected code can analyze and modify the code of the embedded device (e.g., firmware) to create the execution environment for the injected code. For example, the injected code can identify program instruction locations in the code of the embedded device into which jump instructions can be placed. The injected code can also insert at least one jump instruction at an identified program instruction location in the code of the embedded device. In response to the execution of a jump instruction, the injected code can save a context of the code of the embedded device to memory and loading a payload context into a processor of the embedded device. The payload context can then be executed by the processor of the embedded device.

Abstract: A pipeline processor which meets a latency restriction on an equal model is provided. The pipeline processor includes a pipeline processing unit to process an instruction at a plurality of stages and an equal model compensator to store the results of the processing of some or all of the instructions located in the pipeline processing unit and to write the results of the processing in a register file based on the latency of each instruction.

Abstract: A method and a system for optimizing utilization of a programmable logic element for use in an electronic control unit for vehicles, wherein the programmable logic element has a soft CPU and/or an unused remaining area. A plurality of model variants is generated that reproduce functionality of the control unit, and generate a plurality of soft CPU configurations with differing configuration scope, which occupy an area corresponding to the configuration scope of the programmable logic element, and execute processor-in-the-loop simulations for the plurality of model variants and/or soft CPU configurations after instantiation of the soft CPU corresponding to the soft CPU configuration on a programmable logic element. The profiling data acquired for the soft CPU during the PIL simulation is used with regard to the processing of the input signal for optimizing utilization of the programmable logic element.

Abstract: State machine engines are disclosed, including those having an instruction insertion register. One such instruction insertion register may provide an initialization instruction, such as to prepare a state machine engine for data analysis. An instruction insertion register may also provide an instruction in an attempt to resolve an error that occurs during operation of a state machine engine. An instruction insertion register may also be used to debug a state machine engine, such as after the state machine experiences a fatal error.

Abstract: Technologies are generally described for task management on computing platforms. In some examples, a method performed under control of a task management system may include determining a relationship among a plurality of tasks executed on a first platform to identify one or more associated tasks; identifying at least one attribute of each of the one or more associated tasks; generating a job that includes the one or more associated tasks and the identified at least one attribute of each of the one or more associated tasks; and instantiating, on a second platform, the one or more associated tasks included in the job based on the at least one attribute of each of the one or more associated tasks, in response to a request to launch the job.

Abstract: A system and method for managing application performance includes a storage controller including a memory containing machine readable medium comprising machine executable code having stored thereon instructions for performing a method of managing application performance and a processor coupled to the memory. The processor is configured to execute the machine executable code to receive storage requests from a plurality of first applications via a network interface, manage QoS settings for the storage controller and the first applications, and in response to receiving an accelerate command associated with a second application from the first applications, increase a first share of a storage resource allocated to the second application, decrease unlocked second shares of the storage resource of the first applications, and lock the first share. The storage resource is a request queue or a first cache. In some embodiments, the second application is a throughput application or a latency application.

Abstract: One embodiment of the present disclosure sets forth an effective way to maintain fairness and order in the scheduling of common resource access requests related to replay operations. Specifically, a streaming multiprocessor (SM) includes a total order queue (TOQ) configured to schedule the access requests over one or more execution cycles. Access requests are allowed to make forward progress when needed common resources have been allocated to the request. Where multiple access requests require the same common resource, priority is given to the older access request. Access requests may be placed in a sleep state pending availability of certain common resources. Deadlock may be avoided by allowing an older access request to steal resources from a younger resource request. One advantage of the disclosed technique is that older common resource access requests are not repeatedly blocked from making forward progress by newer access requests.

Abstract: Techniques described herein are generally related to thread migration across processing cores of a multi-core processor. Execution of a thread may be migrated from a first processing core to a second processing core. Selective state data required for execution of the thread on the second processing core can be identified and can be dynamically acquired from the first processing core. The acquired state data can be utilized by the thread executed on the second processing core.

Abstract: Network traffic that includes an Operations, Administration, and Maintenance (OAM) unit is received. A first data flow to which the OAM data unit belongs is identified from among a plurality of data flows of network traffic. Based on identifying the first flow of communication traffic to which the OAM data unit belongs, a first entry corresponding to the first flow is retrieved from a memory that stores OAM action data including a plurality of entries indicating how OAM data units in different flows of communication traffic are to be processed. The first entry is from among the plurality of entries and indicates how OAM data units in the first flow are to be processed, including whether the network device should modify the data unit as part of an OAM action. The OAM data unit is processed in accordance with the first entry.

Abstract: Embodiments relate to speculative branch handling for transaction abort. An aspect includes detecting a beginning of a current execution of a transaction. Another aspect includes, based on detecting the beginning of the transaction, disabling speculative execution based on branch prediction of an initial branch instruction of the transaction, wherein the initial branch instruction branches to two possible paths, and wherein a first path of the two possible paths comprises an abort handler. Another aspect includes disabling updating of a history table for the initial branch instruction.