Exeception Processing (e.g., Interrupts And Traps) Patents (Class 712/244)
  • Patent number: 9983932
    Abstract: A pipeline processor which meets a latency restriction on an equal model is provided. The pipeline processor includes a pipeline processing unit to process an instruction at a plurality of stages and an equal model compensator to store the results of the processing of some or all of the instructions located in the pipeline processing unit and to write the results of the processing in a register file based on the latency of each instruction.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: May 29, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Heejun Shim, Yenjo Han, Jae-Young Kim, Yeon-Gon Cho, Jinseok Lee
  • Patent number: 9977417
    Abstract: A method and a system for optimizing utilization of a programmable logic element for use in an electronic control unit for vehicles, wherein the programmable logic element has a soft CPU and/or an unused remaining area. A plurality of model variants is generated that reproduce functionality of the control unit, and generate a plurality of soft CPU configurations with differing configuration scope, which occupy an area corresponding to the configuration scope of the programmable logic element, and execute processor-in-the-loop simulations for the plurality of model variants and/or soft CPU configurations after instantiation of the soft CPU corresponding to the soft CPU configuration on a programmable logic element. The profiling data acquired for the soft CPU during the PIL simulation is used with regard to the processing of the input signal for optimizing utilization of the programmable logic element.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: May 22, 2018
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventor: Olaf Grajetzky
  • Patent number: 9934075
    Abstract: Technologies are generally described for task management on computing platforms. In some examples, a method performed under control of a task management system may include determining a relationship among a plurality of tasks executed on a first platform to identify one or more associated tasks; identifying at least one attribute of each of the one or more associated tasks; generating a job that includes the one or more associated tasks and the identified at least one attribute of each of the one or more associated tasks; and instantiating, on a second platform, the one or more associated tasks included in the job based on the at least one attribute of each of the one or more associated tasks, in response to a request to launch the job.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 3, 2018
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Yang-Won Jung
  • Patent number: 9934034
    Abstract: State machine engines are disclosed, including those having an instruction insertion register. One such instruction insertion register may provide an initialization instruction, such as to prepare a state machine engine for data analysis. An instruction insertion register may also provide an instruction in an attempt to resolve an error that occurs during operation of a state machine engine. An instruction insertion register may also be used to debug a state machine engine, such as after the state machine experiences a fatal error.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: April 3, 2018
    Assignee: Micron Technology, Inc.
    Inventor: David R. Brown
  • Patent number: 9930133
    Abstract: A system and method for managing application performance includes a storage controller including a memory containing machine readable medium comprising machine executable code having stored thereon instructions for performing a method of managing application performance and a processor coupled to the memory. The processor is configured to execute the machine executable code to receive storage requests from a plurality of first applications via a network interface, manage QoS settings for the storage controller and the first applications, and in response to receiving an accelerate command associated with a second application from the first applications, increase a first share of a storage resource allocated to the second application, decrease unlocked second shares of the storage resource of the first applications, and lock the first share. The storage resource is a request queue or a first cache. In some embodiments, the second application is a throughput application or a latency application.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: March 27, 2018
    Assignee: NetApp, Inc.
    Inventors: Sai Rama Krishna Susarla, Scott Hubbard, William Patrick Delaney, Rodney A. Dekoning
  • Patent number: 9836325
    Abstract: One embodiment of the present disclosure sets forth an effective way to maintain fairness and order in the scheduling of common resource access requests related to replay operations. Specifically, a streaming multiprocessor (SM) includes a total order queue (TOQ) configured to schedule the access requests over one or more execution cycles. Access requests are allowed to make forward progress when needed common resources have been allocated to the request. Where multiple access requests require the same common resource, priority is given to the older access request. Access requests may be placed in a sleep state pending availability of certain common resources. Deadlock may be avoided by allowing an older access request to steal resources from a younger resource request. One advantage of the disclosed technique is that older common resource access requests are not repeatedly blocked from making forward progress by newer access requests.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: December 5, 2017
    Assignee: NVIDIA Corporation
    Inventors: Michael Fetterman, Shirish Gadre, John H. Edmondson, Omkar Paranjape, Anjana Rajendran, Eric Lyell Hill, Rajeshwaran Selvanesan, Charles McCarver, Kevin Mitchell, Steven James Heinrich
  • Patent number: 9804896
    Abstract: Techniques described herein are generally related to thread migration across processing cores of a multi-core processor. Execution of a thread may be migrated from a first processing core to a second processing core. Selective state data required for execution of the thread on the second processing core can be identified and can be dynamically acquired from the first processing core. The acquired state data can be utilized by the thread executed on the second processing core.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: October 31, 2017
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Sriram Vajapeyam
  • Patent number: 9680720
    Abstract: Network traffic that includes an Operations, Administration, and Maintenance (OAM) unit is received. A first data flow to which the OAM data unit belongs is identified from among a plurality of data flows of network traffic. Based on identifying the first flow of communication traffic to which the OAM data unit belongs, a first entry corresponding to the first flow is retrieved from a memory that stores OAM action data including a plurality of entries indicating how OAM data units in different flows of communication traffic are to be processed. The first entry is from among the plurality of entries and indicates how OAM data units in the first flow are to be processed, including whether the network device should modify the data unit as part of an OAM action. The OAM data unit is processed in accordance with the first entry.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: June 13, 2017
    Assignee: Marvell Israel (M.I.S.L.) Ltd.
    Inventors: Tal Mizrahi, David Melman
  • Patent number: 9619237
    Abstract: Embodiments relate to speculative branch handling for transaction abort. An aspect includes detecting a beginning of a current execution of a transaction. Another aspect includes, based on detecting the beginning of the transaction, disabling speculative execution based on branch prediction of an initial branch instruction of the transaction, wherein the initial branch instruction branches to two possible paths, and wherein a first path of the two possible paths comprises an abort handler. Another aspect includes disabling updating of a history table for the initial branch instruction.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: April 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael Billeci, James J. Bonanno, Adam B. Collura, Christian Jacobi, Anthony Saporito, Timothy J. Slegel
  • Patent number: 9594648
    Abstract: In one embodiment, the present invention includes a method for controlling redundant execution such that if an exceptional event occurs, the redundant execution is stopped, non-redundant execution is performed in one of the threads until the exceptional event has been-resolved, after which a state of the threads is synchronized, and redundant execution is continued. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: March 14, 2017
    Assignee: Intel Corporation
    Inventors: Glenn J. Hinton, Steven E. Raasch, Sebastien Hily, John G. Holm, Ronak Singhal, Avinash Sodani, Deborah T. Marr
  • Patent number: 9558001
    Abstract: Methods and reservation stations for selecting instructions to issue to a functional unit of an out-of-order processor. The method includes classifying each instruction into one of a number of categories based on the type of instruction. Once classified an instruction is stored in an instruction queue corresponding to the category in which it was classified. Instructions are then selected from one or more of the instruction queues to issue to the functional unit based on a relative priority of the plurality of types of instructions. This allows certain types of instructions (e.g. control transfer instructions, flag setting instructions and/or address generation instructions) to be prioritized over other types of instructions even if they are younger.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: January 31, 2017
    Assignee: Imagination Technologies Limited
    Inventors: Anand Khot, Hugh Jackson
  • Patent number: 9552250
    Abstract: Discovering a hardware failure in a processor is disclosed. When an operating system or application fails, a function containing the instruction that failed along with the register set of the CPU at the failure is recorded. The function is analyzed into its basic blocks. The failing instruction, the failing basic block, the definitions that reach the failing instruction, and the CPU register set at the failure provide information to determine whether the failure was caused by hardware or software. If, after a complete search of the definitions reaching the failing instruction, the search discovers a first definition defining the failing instruction and a second definition defining the first definition such that the second definition reaches the failing instruction and the first definition assigns a register value that does not match a register value in the failing instruction, then a hardware failure is the cause of the crash.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: January 24, 2017
    Assignee: VMware, Inc.
    Inventors: Hariprakash Govindarajalu, Yujie Chen, Sowgandh Sunil Gadi, Ravi Parimi
  • Patent number: 9552285
    Abstract: Micro-execution is the ability to run any code segment in isolation. Implementations for micro-execution of code segments are described. A test engine determines an effective address of a memory operation of an instruction of an executable program. The test engine determines, prior to performing the memory operation and based on a memory policy, that the effective address is to be replaced with a replacement address. Based on determining that the effective address is to be replaced, the test engine allocates the replacement address and executes the instruction based on the allocated replacement address.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: January 24, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Patrice Godefroid
  • Patent number: 9547595
    Abstract: A transactional memory system salvages hardware lock elision (HLE) transactions. A computer system of the transactional memory system records information about locks elided to begin HLE transactional execution of first and second transactional code regions. The computer system detects a pending cache line conflict of a cache line, and based on the detecting stops execution of the first code region of the first transaction and the second code region of the second transaction. The computer system determines that the first lock and the second lock are different locks and uses the recorded information about locks elided to acquire the first lock of the first transaction and the second lock of the second transaction. The computer system commits speculative state of the first transaction and the second transaction and the computer system continues execution of the first code region and the second code region non-transactionally.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: January 17, 2017
    Assignee: International Business Machines Corporation
    Inventors: Harold W. Cain, III, Michael Karl Gschwind, Maged M. Michael, Chung-Lung K. Shum
  • Patent number: 9535926
    Abstract: A server computer system performs a first set of operations for a first transaction. The first transaction pertaining to data stored in a file system. The server computer system delays a second set of operations for the first transaction and identifies a second transaction pertaining to the data. In response to identifying the second transaction, the server computer system cancels the second set of operations for the first transaction, and cancels a first set of operations for the second transaction.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: January 3, 2017
    Assignee: Red Hat, Inc.
    Inventors: Anand Vishweswaran Avati, Pranith Kumar Karampuri
  • Patent number: 9535697
    Abstract: The present embodiments provide a system that facilitates lazy register window fills in a processor. During program execution, when the system encounters a restore instruction for a register window, the system determines if the restore instruction causes an underflow condition that requires the register window to be filled from a stack in memory. If so, the system completes the restore instruction by updating state information for the register window to indicate that the restore instruction is complete without actually filling the individual registers that comprise the register window from the stack. During subsequent program execution, the system lazily fills registers in the register window from the stack as the registers are accessed by the program.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: January 3, 2017
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventor: Yuan C. Chou
  • Patent number: 9521952
    Abstract: A position of a light absorber existing in a subject and an initial sound pressure of an acoustic wave generated at the light absorber are calculated from an electric signal converted from the received acoustic wave generated in response to irradiation of the subject with light. An optical absorption coefficient and an optical scattering coefficient of the subject are calculated using the position of the light absorber and the initial sound pressure of the acoustic wave generated at the position of the light absorber. A light quantity distribution in the subject is calculated using the optical absorption coefficient and the optical scattering coefficient of the subject. An optical absorption coefficient distribution in the subject is calculated using the light quantity distribution in the subject and an initial sound pressure distribution in the subject obtained from the electric signal.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: December 20, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takuro Miyasato
  • Patent number: 9483323
    Abstract: Providing unblocked read operations concurrent with write operations with respect to shared data resources in parallel processing systems. In an embodiment, for each data resource, a pair of fields and an index field is maintained. The index field indicates which of the two fields (e.g., first field) stores a current value for the data resource. However, when a new value is to be stored for the data resource, the value is first stored in the second field using a execution entity, while ensuring exclusive access for the execution entity to the second field. The index field is then updated to indicate that the second field stores the current value, such that the new value in the second field is thereafter available as the current value for read operations. All read operations by any corresponding concurrent execution entities, during the write operation, are continued unblocked.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: November 1, 2016
    Assignee: Oracle International Corporation
    Inventor: Giridhar Narasimhamurthy
  • Patent number: 9454377
    Abstract: Embodiments relate to speculative branch handling for transaction abort. An aspect includes detecting a beginning of a current execution of a transaction. Another aspect includes, based on detecting the beginning of the transaction, disabling speculative execution based on branch prediction of an initial branch instruction of the transaction, wherein the initial branch instruction branches to two possible paths, and wherein a first path of the two possible paths comprises an abort handler. Another aspect includes disabling updating of a history table for the initial branch instruction.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: September 27, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael Billeci, James J. Bonanno, Adam B. Collura, Christian Jacobi, Anthony Saporito, Timothy J. Siegel
  • Patent number: 9424090
    Abstract: Systems and methods provide a processing task load and type adaptive manycore processor architecture, enabling flexible and efficient information processing. The architecture enables executing time variable sets of information processing tasks of differing types on their assigned processing cores of matching types. This involves: for successive core allocation periods (CAPs), selecting specific processing tasks for execution on the cores of the manycore processor for a next CAP based at least in part on core capacity demand expressions associated with the processing tasks hosted on the processor, assigning the selected tasks for execution at cores of the processor for the next CAP so as to maximize the number of processor cores whose assigned tasks for the present and next CAP are associated with same core type, and reconfiguring the cores so that a type of each core in said array matches a type of its assigned task on the next CAP.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: August 23, 2016
    Assignee: THROUGHPUTER, INC.
    Inventor: Mark Henrik Sandstrom
  • Patent number: 9405544
    Abstract: A system and method for efficient branch prediction. A processor includes a next fetch predictor to generate a fast branch prediction for branch instructions at an early pipeline stage. The processor also includes a main return address stack (RAS) at a later pipeline stage for predicting the target of return instructions. When a return instruction is encountered, the prediction from the next fetch predictor is replaced by the top of the main RAS. If there are any recent call or return instructions in flight toward the main RAS, then a separate prediction is generated by a mini-RAS.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: August 2, 2016
    Assignee: Apple Inc.
    Inventors: Douglas C. Holman, Ramesh B. Gunna, Conrado Blasco-Allue
  • Patent number: 9405637
    Abstract: An embodiment of the invention provides a method for changing a multi-processor system from a performance mode to a safety mode while the system continues to run software. When an external event or exception occurs, context is switched from the performance mode to the safety mode. After context is switched, at least one pair of CPUs is synchronized to operate in the safety mode. In addition, a multi-processor system may be switched form the safety mode to the performance mode while the software continues to operate.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: August 2, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Alexandre Pierre Palus
  • Patent number: 9348598
    Abstract: A hierarchical cache with at least a unified cache is used to store both instructions and data values, and a further cache coupled between processing circuitry and a unified cache. The unified cache has a plurality of cache lines identified as an instruction cache line or a data cache line. Each data cache line stores at least one data value and the associated information. Pre-decode circuitry is associated with the unified cache and performs a first pre-decode operation on a received instruction for that instruction cache line in order to generate a corresponding partially pre-decoded instruction for storing in the instruction cache line. Further pre-decode circuitry is associated with the further cache, and, when a partially pre-decoded instruction is routed to the further cache, performs a further pre-decode operation on the partially pre-decoded instruction to generate a corresponding pre-decoded instruction for storage in the further cache.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: May 24, 2016
    Assignee: ARM Limited
    Inventor: Peter Richard Greenhalgh
  • Patent number: 9336341
    Abstract: A simulation technique that handles accesses to a frame of memory via a proxy object provides improved throughput in simulation environments. The proxy object, if present, processes the access at a head of a linked list of frames. If a check frame is not inserted in the list, the memory frame handles the request directly, but if a check frame is inserted, then the check operation is performed. The check frame can be a synchronization frame that blocks access to a memory frame while the check frame is present, or the check frame may be a breakpoint, watch or exception frame that calls a suitable handling routine. Additional check frames may be chained between the interface and the memory subsystem to handle synchronization, breakpoints, memory watches or other accesses to or information gathering associated with the memory frame.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: May 10, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tracy Bashore, Ahmed Gheith, Aditya Kumar, Andrew R. Malota, Ronald L. Rockhold
  • Patent number: 9323874
    Abstract: A simulation technique that handles accesses to a frame of memory via a proxy object provides improved throughput in simulation environments. The proxy object, if present, processes the access at a head of a linked list of frames. If a check frame is not inserted in the list, the memory frame handles the request directly, but if a check frame is inserted, then the check operation is performed. The check frame can be a synchronization frame that blocks access to a memory frame while the check frame is present, or the check frame may be a breakpoint, watch or exception frame that calls a suitable handling routine. Additional check frames may be chained between the interface and the memory subsystem to handle synchronization, breakpoints, memory watches or other accesses to or information gathering associated with the memory frame.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: April 26, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tracy Bashore, Ahmed Gheith, Aditya Kumar, Andrew R. Malota, Ronald L. Rockhold
  • Patent number: 9311259
    Abstract: A transaction is initiated within a computing environment, and based on detecting a program event recording event, an interrupt is presented for the transaction. Subsequent to the interrupt, one or more controls are set to inhibit presentation of another interrupt based on detecting another PER event. Thereafter, the transaction is re-executed and PER events detected during execution of the transaction are ignored.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: April 12, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Damian L. Osisek, Timothy J. Slegel
  • Patent number: 9304769
    Abstract: A method and apparatus for enabling a Software Transactional Memory (STM) with precompiled binaries is herein described. Upon encountering an access operation in a transaction, an annotation field associated with a memory location referenced by the access is checked. In response to the memory location representing a previous similar access within the transaction, the access is performed without access barriers. However, if the annotation field is in a default state representing no previous access during a pendancy of the transaction, then a mode of the processor is determined. If the processor mode is in implicit mode, an access handler/barrier is asynchronously executed. Conversely, in an explicit mode, a flag is set instead of asynchronously executing the handler. In addition, during compilation convert explicit and convert implicit instructions are inserted to intelligently convert modes for precompiled and newly compiled binaries.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: April 5, 2016
    Assignee: Intel Corporation
    Inventors: Bratin Saha, Ali-Reza Adl-Tabatabai, Quinn A. Jacobson
  • Patent number: 9292364
    Abstract: A technique is described providing offline support to business applications. Offline support allows a business application running on a portable electronic device without connectivity to a backend server to operate as though the business application has access to a backend server. The technique receives a client request to operate the application in an offline mode. The technique then retrieves a business object to be utilized in the offline mode and an event trigger for interacting with the business object. The native programming language is then determined and then an event handler written in a native language of the client device and that is associated with the event trigger is retrieved. The event trigger is then modified to point to the event handler. The business object, event trigger, and event handler are then packaged together.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: March 22, 2016
    Assignee: SAP SE
    Inventors: Mario Linge, Ananda Kumar Gajula, Jianxun Zhou, Oscar Marquez, Xiaojun Feng, Yang-cheng Fan, Ming Zhu, Paul Xi, Marco Eidinger, Mohamed Elzankaly
  • Patent number: 9262170
    Abstract: Reclaiming checkpoints in a system in an order that differs from the order when the checkpoints are created. Reclaiming the checkpoints includes: creating one or more checkpoints, each of which having an initial state using system resources and holding the checkpoints state; identifying the completion of all the instructions associated with the checkpoint; reassigning all the instructions associated with the identified checkpoint to an immediately preceding checkpoint; and freeing the resources associated with the identified checkpoint. The checkpoint is created when the instruction that is checked is a conditional branch having a direction that cannot be predicted with a predetermined confidence level.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Anil Krishna, Ganesh Balakrishnan, Gordon B. Bell
  • Patent number: 9235539
    Abstract: A transaction is initiated within a computing environment, and based on detecting a program event recording event, an interrupt is presented for the transaction. Subsequent to the interrupt, one or more controls are set to inhibit presentation of another interrupt based on detecting another PER event. Thereafter, the transaction is re-executed and PER events detected during execution of the transaction are ignored.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: January 12, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Damian L. Osisek, Timothy J. Slegel
  • Patent number: 9223974
    Abstract: In one general embodiment, a computer program product for compiling code includes a computer readable storage medium having computer readable code stored/encoded thereon. The computer readable code is readable/executable by a processor to: receive computer readable code to compile, the code including one or more functions, each function including one or more call functions; and build a stack frame for one of the call functions in the code. The stack frame includes: a return address sequence, logic configured to define local variables, logic configured to define a first guard variable and a second guard variable, logic configured to compare the first guard variable to the second guard variable, logic configured to execute the return address sequence when the first and second guard variables match, and logic configured to abort prior to executing the return address sequence when the first and second guard variables do not match.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: December 29, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Gregory T. Kishi
  • Patent number: 9218029
    Abstract: A method for resetting a so-called System on Chip SoC is described as well as a system adapted and configured to perform the method. A reset signal applied to the SoC resets the system but at the same time prevents loss and corruption of data that was processed at the time of signal application.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: December 22, 2015
    Assignee: Infineon Technologies AG
    Inventors: Richard Knight, Tim Weyland, Juergen Karmann
  • Patent number: 9213828
    Abstract: A data processing apparatus includes processing circuitry and a data store including a plurality of regions including a secure region and a less secure region. The secure region is configured to store sensitive data accessible by the circuitry when operating in a secure domain and not accessible by the circuitry when operating in a less secure domain. The data store includes a plurality of stacks with a secure stack in the secure region. Stack access circuitry is configured to store predetermined processing state to the secure stack. The processing circuitry further comprises fault checking circuitry configured to identify a first fault condition if the data stored in the predetermined relative location is the first value. This provides protection against attacks from the less secure domain, for example performing a function call return from an exception, or an exception return from a function call.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: December 15, 2015
    Assignee: ARM Limited
    Inventors: Thomas Christopher Grocutt, Richard Roy Grisenthwaite, Simon John Craske
  • Patent number: 9207979
    Abstract: A method for pipelined data stream processing of packets includes determining a task to be performed on each packet of a data stream, the task having a plurality of task portions including a first task portion. Determining the first task portion is to process a first packet. In response to determining a first storage location stores a first barrier indicator, enabling the first task portion to process the first packet and storing a second barrier indicator at the first location. Determining the first task portion is to process a second next-in-order packet. In response to determining the first location stores the second barrier indicator, preventing the first task portion from processing the second packet. In response to a first barrier clear indicator, storing the first barrier indicator at the first location, and in response, enabling the first task portion to process the second packet.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: December 8, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: James C. Holt, Joseph P. Gergen, David B. Kramer, William C. Moyer
  • Patent number: 9158544
    Abstract: A method and system are provided for deriving a resultant software code from an originating ordered list of instructions that does not include overlapping branch logic. The method may include deriving a plurality of unordered software constructs from a sequence of processor instructions; associating software constructs in accordance with an original logic of the sequence of processor instructions; determining and resolving memory precedence conflicts within the associated plurality of software constructs; resolving forward branch logic structures into conditional logic constructs; resolving back branch logic structures into loop logic constructs; and/or applying the plurality of unordered software constructs in a programming operation by a parallel execution logic circuitry. The resultant plurality of unordered software constructs may be converted into programming reconfigurable logic, computers or processors, and also by means of a computer network or an electronics communications network.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: October 13, 2015
    Inventor: Robert Keith Mykland
  • Patent number: 9116777
    Abstract: A method for performing process instance migration between a source workflow environment and a target workflow environment is provided. The method includes a server computing system, exporting a source workflow environment to a target workflow environment. The method further includes the server computing system, migrating process instances from the source workflow environment to the target workflow environment. The method further includes, if a jump function of the target workflow environment is restricted to an activity sequence, a target computing system of the target workflow environment, adjusting the exported process models. The method further includes the target computing system, initializing another process instance, from the exported process models in the target workflow environment.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: August 25, 2015
    Assignee: International Business Machines Corporation
    Inventors: Plamen Kiradjiev, Dieter Koenig, Michael Lackerbauer, Michael Redert
  • Patent number: 9075692
    Abstract: Embodiments of the present invention provide a method, a device and a system for activating an on-line patch. The method comprises: positioning an address of a patch function and an entry address of a to-be-patched function; writing, in a middle segment, a long-jump instruction for jumping to the patch function based on the address of the patch function and the entry address of the to-be-patched function, where the middle segment is a storage space, which is located before or after the entry position of the to-be-patched function and can at least store one long-jump instruction; and modifying an instruction at the entry position of the to-be-patched function to a short-jump instruction for jumping to the middle segment, so as to jump to the middle segment after the short jump instruction is executed, and then to jump to and execute the patch function through that instructions in the middle segment are executed.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: July 7, 2015
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jiaqiang Yu, Wei Zheng
  • Patent number: 9047193
    Abstract: A digital system is provided. The digital system includes an execution unit, a level-zero (L0) memory, and an address generation unit. The execution unit is coupled to a data memory containing data to be used in operations of the execution unit. The L0 memory is coupled between the execution unit and the data memory and configured to receive a part of the data in the data memory. The address generation unit is configured to generate address information for addressing the L0 memory. Further, the L0 memory provides at least two operands of a single instruction from the part of the data to the execution unit directly, without loading the at least two operands into one or more registers, using the address information from the address generation unit.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: June 2, 2015
    Assignee: SHANGHAI XIN HAO MICRO ELECTRONICS CO. LTD.
    Inventors: Kenneth Chenghao Lin, Haoqi Ren
  • Patent number: 9041513
    Abstract: A system and method is disclosed for communicating with sensors/loggers in integrated radio frequency identification (RFID) tags. An RFID reader uses a Communicate With Data Logger Command to communicate with a data logger in an RFID tag. The RFID reader performs data access processes using an Index Register and a Data Register of the RFID tag. The RFID reader selects one of (1) Index Read access (2) Index Write access (3) Data Write access (4) Data Read access with parity and (5) Data Read access with cyclic redundancy check (CRC). The RFID tag performs the requested data access and then performs an error detection process.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: May 26, 2015
    Assignee: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Srinath B. Pai, K. Krishna Moorthy
  • Publication number: 20150143089
    Abstract: Mechanisms for providing enhanced system performance and reliability on multi-core computing devices are discussed. Embodiments use modified hardware and/or software so that when a System Management Interrupt (SMI#) is generated, only a single targeted CPU core enters System Management Mode (SMM) in response to the SMI while the remaining CPU cores continue operating in normal mode. Further, a multi-threaded SMM environment and mutual exclusion objects (mutexes) may allow guarding of key hardware resources and software data structures to enable individual CPU cores among the remaining CPU cores to subsequently also enter SMM in response to a different SMI while the originally selected CPU core is still in SMM.
    Type: Application
    Filed: November 20, 2014
    Publication date: May 21, 2015
    Inventors: Timothy Andrew LEWIS, Kevin Dale DAVIS
  • Publication number: 20150106604
    Abstract: A system and method for efficiently performing program instrumentation. A processor processes instructions stored in a memory. When the processor processes a given instruction of a given instruction type, the processor updates a corresponding performance counter. When the performance counter reaches a threshold, the processor generates an interrupt and compares a location of the given instruction with stored locations in a given list. If a match is not found, then the processor processes an instruction following the given instruction in the computer program without processing intermediate instrumentation code. If a match is found, then the processor processes instrumentation code. Regardless of whether or not the instrumentation code is processed, when control flow returns to the computer program, the corresponding performance counter is initialized with a random value.
    Type: Application
    Filed: October 15, 2013
    Publication date: April 16, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Joseph L. Greathouse, David S. Christie
  • Patent number: 8997099
    Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 31, 2015
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Dion Rodgers, Richard A. Uhlig, Lawrence O. Smith, Barry E. Huntley
  • Publication number: 20150067307
    Abstract: A microprocessor a plurality of processing cores, wherein each of the plurality of processing cores instantiates a respective architecturally-visible storage resource. A first core of the plurality of processing cores is configured to encounter an architectural instruction that instructs the first core to update the respective architecturally-visible storage resource of the first core with a value specified by the architectural instruction. The first core is further configured to, in response to encountering the architectural instruction, provide the value to each of the other of the plurality of processing cores and update the respective architecturally-visible storage resource of the first core with the value. Each core of the plurality of processing cores other than the first core is configured to update the respective architecturally-visible storage resource of the core with the value provided by the first core without encountering the architectural instruction.
    Type: Application
    Filed: May 19, 2014
    Publication date: March 5, 2015
    Inventors: G. Glenn Henry, Stephan Gaskins
  • Patent number: 8959317
    Abstract: A microcomputer includes: a plurality of register lists having a plurality of register patterns, respectively, wherein each of plurality of register patterns designates registers, data of which are to be saved in a data memory; an instruction fetch control circuit configured to fetch instruction code from an instruction memory in response to an interrupt request issued based on occurrence of an interrupt factor; and a register data saving control circuit configured to acquire one register pattern from one of the plurality of register lists in response to the interrupt request, and issue a microinstruction based on the acquired register pattern in response to the interrupt request. An instruction executing section is configured to execute the microinstruction prior to the fetched instruction code, to save the data of registers designated based on the acquired register pattern in the data memory.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: February 17, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Hideki Matsuyama
  • Patent number: 8938608
    Abstract: A method for allowing portions of programs to be executed on a System z Integrated Information Processor (zIIP). A service call is inserted at the beginning of the zIIP eligible code to enable enclave Service Request Block (SRB)-mode execution on the zIIP processor. An additional service call is inserted at the end of the zIIP eligible code to disable the enclave SRB-mode execution. A module in the operating system, referred to herein as the “zIIP shifter module,” is configured to detect these service calls thereby implementing and terminating the SRB-mode execution so that the zIIP processor executes the zIIP eligible code for the appropriate duration of time. In this manner, only a portion of the programs that contain eligible zIIP executable code is executed on the zIIP processor without requiring the programs to be entirely restructured thereby reducing development cost and improving software development productivity.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Wayne E. Driscoll, Paul E. Kenney, Ben P. Marino, Hong Zhou
  • Publication number: 20150019847
    Abstract: A central processing unit (CPU) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same number of CPU registers, a switching unit for coupling a selected register set within the CPU, wherein the switching unit switches to a predetermined register set of the plurality of context defining register sets upon occurrence of an exception, and a control register configured to control selection of a register set of the plurality of context defining register initiated by an instruction and further operable to indicate a currently used context.
    Type: Application
    Filed: March 7, 2014
    Publication date: January 15, 2015
    Inventors: Michael I. Catherwood, Bryan Kris, David Mickey, Joseph Kanellopoulos
  • Patent number: 8935699
    Abstract: Architectures and techniques for substantially maintaining performance of hyperthreads within processing cores of processors. One technique can include determining that a first thread is scheduled for execution on one of two or more hyperthreads, where the first instruction thread has a first priority. Such a technique also includes determining that a second instruction thread is one of executing or scheduled for execution on another of the two or more hyperthreads, where the second instruction thread has a second priority that is less than the first priority The technique can further include preempting execution of the second instruction thread based at least in part on the second instruction thread having the second priority that is less than the first priority.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: January 13, 2015
    Assignee: Amazon Technologies, Inc.
    Inventors: Pradeep Vincent, Darek J. Mihocka
  • Patent number: 8935516
    Abstract: A system and computer program product for allowing portions of programs to be executed on a System z Integrated Information Processor (zIIP). A service call is inserted at the beginning of the zIIP eligible code to enable enclave Service Request Block (SRB)-mode execution on the zIIP processor. An additional service call is inserted at the end of the zIIP eligible code to disable the enclave SRB-mode execution. A module in the operating system, referred to herein as the “zIIP shifter module,” is configured to detect these service calls thereby implementing and terminating the SRB-mode execution so that the zIIP processor executes the zIIP eligible code for the appropriate duration of time. In this manner, only a portion of the programs that contain eligible zIIP executable code is executed on the zIIP processor without requiring the programs to be entirely restructured thereby reducing development cost and improving software development productivity.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Wayne E. Driscoll, Paul E. Kenney, Ben P. Marino, Hong Zhou
  • Patent number: 8930638
    Abstract: A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by the performance-improving processes commonly used in coherency controllers such as dropping, merging, invalidating, forwarding, and snooping. This is done by ensuring that requests marked for target-side security checking and any other requests to overlapping addresses are forwarded directly to the target-side security filter without modification or side effects.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: January 6, 2015
    Assignee: QUALCOMM Technologies, Inc.
    Inventors: Laurent Moll, Jean-Jacques Lecler, Philippe Boucard
  • Patent number: 8930682
    Abstract: In one embodiment, the present invention is directed to a bit processor that includes an execution unit to, responsive to an instruction for access of data of a first bit width, access data of a second bit width, the second bit width having a different number of bits than the first bit width when some of the data accessed includes non-stream data. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: January 6, 2015
    Assignee: Intel Corporation
    Inventors: Raul Gutierrez, Suryaprasad Kareenahalli, Daniel Nemiroff, Balaji Vembu