Abstract: A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch resolutions and predictions is accessed and hashed with the first branch address, creating a first hash result. The first hash result is used to index a branch history table (BHT) of previous first branch resolutions. As a result, a first branch prediction is made, and the SGHR is updated with the first branch prediction. A non-speculative global history record (NSGHR) of branch resolutions is updated with the resolution of the first branch operation, and if the first branch prediction is incorrect, the SGHR is corrected using the NSGHR.

Abstract: An execution time estimation device includes a program partitioning section that extracts partial programs partitioned by a conditional branch instruction or a function call instruction from a target program, a partial program execution time estimation calculating section that calculates the execution time of each of the partial programs to associate the leading instruction and the end instruction of each of the partial programs, and the calculated execution time with one another, a branch history information generating section that generates a branch history bit sequence which is a sequence of the true-false of the conditional branch instruction of when the target program is executed, an execution trace reproducing section that generates the execution sequences of the partial programs based on the branch history bit sequence, and an execution time estimation calculating section that adds the execution time of the partial programs based on the execution sequences of the partial programs.

Abstract: Embodiments of the invention provide an apparatus of storing branch prediction information. In one embodiment, an integrated circuit device includes a first table for storing local branch prediction information, a second table for storing global branch prediction information, and circuitry. The circuitry is configured to receive a branch instruction and store local branch prediction information for the branch instruction in the first table. The local branch prediction information includes a local predictability value for the local branch prediction information. The circuitry is further configured to store global branch prediction information for the branch instruction in the second table only if the local predictability value is below a threshold value of predictability.

Abstract: A method and data processing system allocates entries in a branch target buffer (BTB). Instructions are fetched from a plurality of instructions and one of the plurality of instructions is determined to be a branch instruction. A corresponding branch target address is determined. A determination is made whether the branch target address is stored in a branch target buffer (BTB). When the branch target address is not stored in the branch target buffer, an entry in the branch target buffer is identified for allocation to receive the branch target address based upon stored metrics such as data processing cycle saving information and branch prediction state. In one form the stored metrics are stored in predetermined fields of the entries of the BTB.

Abstract: An instruction fetch control apparatus includes an instruction completion notifier, and an entry designation unit predicting a return address of a subroutine during an instruction fetching. The entry designation unit computes a designate entry position in a return address stack by, changing the designate entry to indicate a one-step shallower entry when a call instruction is predicted during the instruction fetching, changing the designate entry independently of a push or pop operation to indicate a one-step deeper entry when a return instruction is predicted during an instruction fetching, and changing the designate entry depending upon a push and a pop operation when a call and return instruction is completed, thereby keeping a position of the designate entry. The entry designation unit designates an entry as predicted return address of a subroutine when the fetched instruction hitsin a branch history and determined as a return instruction.

Abstract: A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch resolutions and predictions is accessed and hashed with the first branch address, creating a first hash result. The first hash result is used to index a branch history table (BHT) of previous first branch resolutions. As a result, a first branch prediction is made, and the SGHR is updated with the first branch prediction. A non-speculative global history record (NSGHR) of branch resolutions is updated with the resolution of the first branch operation, and if the first branch prediction is incorrect, the SGHR is corrected using the NSGHR.

Abstract: A microprocessor includes a branch target address cache (BTAC), each entry thereof configured to store branch prediction information for at most N branch instructions. An execution unit executes a branch instruction previously fetched in a fetch quantum. Update logic determines whether the BTAC is already storing information for N branch instructions within the fetch quantum (N is at least two), updates the BTAC for the branch instruction if the BTAC is not already storing information for N branch instructions, determines whether a type of the branch instruction has a higher replacement priority than a type of the N branch instructions if the BTAC is already storing information for N branch instructions, and updates the BTAC for the branch instruction if the type of the branch instruction has a higher replacement priority than the type of the N branch instructions already stored in the BTAC.

Abstract: A system for predicting multiple targets for a single branch includes: a branch target buffer that includes a previous next address for an instruction and that receives an indirect instruction address to provide a first branch target prediction; a first branch table for capturing local past target information of an indirect branch in an encoded form; a second branch table which is a correlation table for storing potential branch targets based on a local branch history and which provides a second branch target prediction when the first branch target prediction is not successful; an exclusion predictor for inhibiting updates of inefficient entries; and a multiplexer to select the predicted target as output.

Abstract: A system and method provides branch target buffer (BTB) allocation. When a branch instruction is received, a branch target address that corresponds to the branch instruction is determined. A determination is made whether the branch target address is presently stored in a branch target buffer (BTB). When the branch target address is not presently stored in the branch target buffer, an entry in the branch target buffer is identified to receive the branch target address. A value in a field within the identified entry in the branch target buffer, such as a postponement flag (PF), is used to selectively override a replacement decision defined by predetermined branch target buffer allocation criteria. In one form, if a branch is taken, the identified entry is replaced with the branch target address in response to determining that the value in the field within the identified entry has a predetermined value.

Abstract: This invention combines a loop support mechanism and a branch prediction mechanism. After an instruction execution unit executes an end block instruction of a block repeat, the loop control unit branches to the first instruction in the loop and sends a pseudo branch instruction to the instruction execution unit. The instruction execution unit acts as if the last instruction in the block is an instruction for branching to the start address of the block. This is stored in the branch prediction unit and branch prediction is performed thereafter.

Abstract: In a method of linking to information in a deduplication data sequence, a branching point is identified. The branching point is a place where a branch data sequence diverges from a parent data sequence that has been previously stored in a data deduplication process. A signature value associated with a subsequence of the information represented in the branch data sequence is determined. A branch location where the information of the branch data sequence begins is identified. Link information is stored in association with the branching point. The link information is stored in a computer memory. The link information comprises a link to the branch location and also comprises a portion of the signature value.

Abstract: A branch prediction mechanism 16, 18 within a multithreaded processor having hardware scheduling logic 6, 8, 10, 12 uses a shared global history table 18 which is indexed by respective branch history registers 20, 22 for each program thread. Different mappings are used between preceding branch behavior and the prediction value stored within respective branch history registers 20, 22. These different mappings may be provided by inverters placed into the shift in paths for the branch history registers 20, 22 or by adders 40, 42 or in some other way. The different mappings help to equalise the probability of use of the particular storage locations within the global history table 18 such that the plurality of program threads are not competing excessively for the same storage locations corresponding to the more commonly occurring patterns of preceding branch behavior.

Abstract: In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit. The instruction sequencing logic including branch target address prediction circuitry that stores a branch target address prediction associating a first instruction fetch address with a branch target address to be used as a second instruction fetch address. The branch target address prediction circuitry includes delay logic that, in response to at least a tag portion of a third instruction fetch address matching the first instruction fetch address, delays access to the memory system utilizing the second instruction fetch address if no branch target address prediction was made in an immediately previous cycle of operation.

Abstract: An out-of-order execution in-order retire microprocessor includes a branch information table comprising N entries. Each of the N entries stores information associated with a branch instruction. The microprocessor also includes a reorder buffer comprising M entries. Each of the M entries stores information associated with an unretired instruction within the microprocessor. Each of the M entries includes a field that indicates whether the unretired instruction is a branch instruction and, if so, a tag identifying one of the N entries in the branch information table storing information associated with the branch instruction. N is significantly less than M such that the overall die space and power consumption is reduced over a processor in which each reorder buffer entry stores the branch information.

Abstract: A branch target buffer (BTB) receives, from a processor, a current fetch group address which corresponds to a current fetch group including a plurality of instructions. In response to the current fetch group address resulting in a group hit in the BTB, the BTB provides to the processor a branch target address corresponding to a branch instruction within the current fetch group which is indicated by a control field as valid and predicted taken. The BTB generates the branch target address using an unshared lower order target portion, corresponding to the branch instruction and located within the entry of the BTB which caused the group hit, and one of a shared higher order target portion located within the entry of the BTB which caused the group hit or a higher order portion of the current fetch group address based on a value of the control field.

Abstract: In at least one embodiment, a processor includes an execution unit and instruction sequencing logic that fetches instructions from a memory system for execution by the execution unit. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a branch target address prediction circuitry concurrently holding a first entry providing storage for a first branch target address prediction associating a first instruction fetch address with a first branch target address to be used as an instruction fetch address and a second entry providing storage for a second branch target address prediction associating the first instruction fetch address with a different second branch target address. The first entry indicates a first instruction address type for the first instruction fetch address, and the second entry indicates a second instruction address type for the first instruction fetch address.

Abstract: Provided is a means for accessing multiple entries from a branch history table (BHT) in a single clock cycle, in the context of pipelined instruction processing. In a first clock cycle, a plurality of conditional branch instructions is fetched. A value is accessed from a global history record (GHR) of conditional branch resolutions and predictions for a fetched conditional branch instruction. An associated instruction address is hashed with a left-shifted GHR value. The result is used to access a word in an indexed BHT stored in a single-port random access memory (RAM). The word comprises a branch direction count for the plurality of fetched conditional branch instructions. In a second clock cycle a conditional branch instruction is executed at an execute stage and the BHT is written with an updated branch direction count in response to a resolution of the executed conditional branch instruction.

Abstract: An adaptive prediction threshold scheme for dynamically adjusting prediction thresholds of entries in a Pattern History Table (PHT) by observing global tendencies of the branch or branches that index into the PHT entries. A count value of a prediction state counter representing a prediction state of a prediction state machine for a PHT entry is obtained. Count values in a set of counters allocated to the entry in the PHT are changed based on the count value of the entry's prediction state counter. The prediction threshold of the prediction state machine for the entry may then be adjusted based on the changed count values in the set of counters, wherein the prediction threshold is adjusted by changing a count value in a prediction threshold counter in the entry, and wherein adjusting the prediction threshold redefines predictions provided by the prediction state machine.

Abstract: An information processor includes a first recording unit which stores first information indicating correspondence between an instruction address and a branch destination address of a most recent branch instruction, a computation of the most recent branch instruction having been completed and a branch for the most recent branch prediction having been taken, a second recording unit which stores a second information indicating correspondence between an instruction address and a branch destination address of each of past branch instructions including the most recent branch instruction, computations of the past branch instructions having been completed and branches for the past branch instructions having been taken, and a control unit which makes a branch prediction based on the first information or the second information, and stops supply of a clock to the second recording unit and makes a branch prediction based on the first information when an instruction sequence enters a loop.

Abstract: A system and method are disclosed for correlating instruction sequences. A plurality of instructions is processed to parse a first sequence of instructions comprising a first area of interest. A first instruction sequence pattern is then generated from the first sequence of instructions. Pattern matching operations are performed with the first instruction sequence pattern. A second sequence of instructions are parsed, comprising a second instruction sequence pattern and a second address of interest that is a substantially equivalent match to the first instruction sequence pattern.

Abstract: In at least one embodiment, a processor includes at least one execution unit and instruction sequencing logic that fetches instructions for execution by the execution unit. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a branch target address cache (BTAC) having at least one direct entry providing storage for a direct branch target address prediction associating a first instruction fetch address with a branch target address to be used as a second instruction fetch address immediately after the first instruction fetch address and at least one indirect entry providing storage for an indirect branch target address prediction associating a third instruction fetch address with a branch target address to be used as a fourth instruction fetch address subsequent to both the third instruction fetch address and an intervening fifth instruction fetch address.

Abstract: A system and method are provided for updating a global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts a microprocessor instruction of consecutive operations, including a conditional branch operation with an associated branch address, at a first stage in a pipelined microprocessor execution process. A global history record (GHR) of conditional branch resolutions and predictions is accessed and hashed with the branch address, creating a first hash result. The first hash result is used to access an indexed branch history table (BHT) of branch direction counts and the BHT is used to make a branch prediction. If the branch prediction being “taken”, the current GHR value is left-shifted and hashed with the branch address, creating a second hash result which is used in creating an updated GHR.

Abstract: A data processing system 2 incorporating an instruction pipeline 14 and a prefetch unit 16 is provided with a branch prediction mechanism using both a branch prediction memory 20 storing 1-bit values indicating strongly taken or strongly not taken together with a branch prediction cache indicating for certain selected branch history values either weakly taken or weakly not taken predictions. When a conditional branch instruction is encountered, then the preceding branch prediction history is used to access a first prediction within the branch prediction memory 20 and is looked up to check for a hit within the branch prediction cache 22. If a hit occurs, then a second prediction within the branch prediction cache 22 is used in preference to the first prediction, otherwise the first prediction is used.

Abstract: A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced.

Abstract: A two-level branch prediction apparatus includes branch bias logic for predicting whether a branch instruction will result in a branch being taken. Upon receipt of a first address portion of a branch instruction's address, a first store outputs a corresponding first branch bias value. A history store stores history data identifying an actual branch outcome for preceding branch instructions. A second store stores multiple entries, each entry including a replacement branch bias value and a TAG value. An index derived from the history data causes the second store to output a corresponding entry. The first branch bias value is selected unless the TAG value corresponds to a comparison TAG value derived from a second address portion of the branch instruction's address, in which event, the replacement branch bias value is selected.

Abstract: A branch prediction apparatus reads out a branch history table 15 by an index calculated by the output of a branch history register 14 containing a plurality of the latest branch result of a branch instruction. The branch prediction apparatus comprises frequency detection units 18-20 for detecting the appearance frequency of a branch instruction with a different address and data width modification units 16 and 21 for modifying the number of valid bits of the branch history register, based on the detected appearance frequency. Even a program in which a branch result strongly depends on the latest branch history or even a program having a plenty of branch instructions can maintain high prediction accuracy with a small capacity of the branch history table.

Abstract: A data processor (200) includes an instruction cache (220) and a secondary cache (250). The instruction cache (220) has a plurality of cache lines. Each of the plurality of cache lines stores a first plurality of bits (222) corresponding to at least one instruction and a second plurality of bits (224, 226) associated with the execution of the at least one instruction. The secondary cache (250) is coupled to the instruction cache (220) and stores cache lines from the instruction cache (250) by storing the first plurality of bits (222) and a third plurality of bits (255, 257) corresponding to the second plurality of bits (224, 226). The third plurality of bits (255, 257) is fewer in number than the second plurality of bits (224, 226).

Abstract: Mechanisms, in a processor, are provided for detecting and handling short forward branch conversion candidates. The mechanisms identify a conditional branch in the computer code and determine if the short forward conditional branch is to be converted to a non-branching conditional sequence of instructions. Moreover, the mechanisms convert the conditional branch to a non-branching conditional sequence of instructions comprising a resolve instruction and one or more conditional instructions dependent on the resolve instruction. In addition, the mechanisms execute the non-branching conditional sequence of instructions in place of the conditional branch in the computer code and generate an output of the computer code based on the execution of the non-branching conditional sequence of instructions.

Abstract: A data processing apparatus has processing circuitry for performing processing operations including high priority operations and low priority operations, events occurring during performance of those processing operations. Prediction circuitry includes a history storage having a plurality of counter entries for storing count values, and index circuitry for identifying, dependent on the received event, at least one counter entry and for causing the history storage to output the count value stored in that at least one counter entry, with the prediction data being derived from the output count value. Update control circuitry modifies at least one count value stored in the history storage in response to update data generated by the processing circuitry. The update control circuitry has a priority dependent modification mechanism such that the modification is dependent on the priority of the processing operation with which that update data is associated.

Abstract: A method, system, and computer program product are provided, for maintaining a path history register of register indirect branches. A set of bits is generated based on a set of target address bits using a hit selection and/or a hash function operation, and the generated set of bits is inserted into a path history register by shifting bits in the path history register and/or applying a hash operation, information corresponding to prior history is removed from the path history register, using a shift out operation and/or a hash operation. The path, history register is used to maintain a recent target, table and generate register-indirect branch target address predictions based on path history correlation between register-indirect branches captured by the path history register.

Abstract: Systems and methods for history based pipelined branch prediction. In one embodiment, access to prediction information to predict a plurality of branches within an instruction block is initiated in a same clock cycle of the computer processor as a fetch of the instruction block. The prediction information may be available to the predictor not later than a clock cycle of the computer processor in which the plurality of branches are decoded.

Abstract: A processor (1700) for processing instructions has a pipeline (1710, 1736, 1740) including a fetch stage (1710) and an execute stage (1870), a first storing circuit (aGHR 2130) associated with said fetch stage (1710) and operable to store a history of actual branches, and a second storing circuit (wGHR 2140) associated with said fetch stage (1710) and operable to store a pattern of predicted branches, said second storing circuit (wGHR 2140) coupled to said first storing circuit (aGHR 2130), said execute stage (1870) coupled back to said first storing circuit (aGHR 2130). Other processors, wireless communications devices, systems, circuits, devices, branch prediction processes and methods of operation, processes of manufacture, and articles of manufacture, as disclosed and claimed.

Abstract: A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch resolutions and predictions is accessed and hashed with the first branch address, creating a first hash result. The first hash result is used to index a branch history table (BHT) of previous first branch resolutions. As a result, a first branch prediction is made, and the SGHR is updated with the first branch prediction. A non-speculative global history record (NSGHR) of branch resolutions is updated with the resolution of the first branch operation, and if the first branch prediction is incorrect, the SGHR is corrected using the NSGHR.

Abstract: A method for recovering global history shift register (GHSR) and return address stack (RAS) is provided, which is applicable to an instruction pipeline of a processor and includes the following steps. First, provide a branch recovery table (BRT) and a backup stack. Whenever a branch instruction enters a predetermined stage of the instruction pipeline, add a record in the BRT according to the branch instruction. Whenever a return address is popped from the RAS of the instruction pipeline, push the return address into the backup stack. When flushing the instruction pipeline, determine a removal range of the BRT according to the condition which triggers the pipeline flush. Recover the RAS according to the records in the removal range and the backup stack. Remove all records in the removal range. Recover the GHSR of the instruction pipeline according to the removed records.

Abstract: A processor core and method for managing program counter redirection in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline control logic. Operation of the instruction fetch portion is decoupled from operation of the instruction execution portion. Following detection of a control transfer misprediction, operation of the instruction fetch portion is halted and instructions residing in the instruction fetch portion are invalidated. When the instruction associated with the misprediction reaches a selected pipeline stage, instructions residing in the instruction execution portion of the pipeline are invalidated and the flow of instructions from the instruction fetch portion to the instruction execution portion of the processor pipeline is restarted.

Abstract: A processor incorporates a branch prediction mechanism which acts to predict branch outcomes for predicted type branch instructions. The processor also supports non-predicted type branch instructions which are ignored by the branch prediction mechanism and are not subject to prediction. The impact of mispredictions degrading overall performance of the prediction mechanism is reduced by employing non-prediction type branch program instructions to represent/control branch operations when it is known that misprediction is likely for those branch operations.

Abstract: In a processor executing instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, line and counter index addresses are formed that access every counter in a branch history table (BHT), and reduce the number of index address bits that are multiplexed based on the current instruction set execution mode. In one embodiment, counters within a BHT line are arranged and indexed in such a manner that half of the BHT can be powered down for each access in one instruction set execution mode.

Abstract: A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch resolutions and predictions is accessed and hashed with the first branch address, creating a first hash result. The first hash result is used to index a branch history table (BHT) of previous first branch resolutions. As a result, a first branch prediction is made, and the SGHR is updated with the first branch prediction. A non-speculative global history record (NSGHR) of branch resolutions is updated with the resolution of the first branch operation, and if the first branch prediction is incorrect, the SGHR is corrected using the NSGHR.

Abstract: A global history vector (GHV) mechanism maintains a folded (XORed) GHV with higher order entries and an unfolded (no XORed) GHV with lower order entries. When a new entry arrives at the GHV, the GHV mechanism performs an XOR of the oldest unfolded entry in the unfolded GHV with the new entry. The XOR result is then shifted into the folded GHV as the newest folded entry. The oldest folded entry is discarded during the shift in of the newest folded entry. The GHV mechanism thus provides a resulting folded GHV that is current and can be utilized for XORing with an IFAR by performing an XOR operation. Only a single XOR logic is required to perform a single bit XOR operation between the oldest entry and the youngest entry, resulting in reducing the cycle time required to complete the folding (XORing) operation on a GHV.

Abstract: A parallel testing system with shared golden calibration table includes: a storage unit, multiple testing platforms, and a server. The storage unit is used for storing the golden calibration table, and the testing platforms are used to test a device under test (DUT) respectively by utilizing the golden calibration table. The server is connected to the storage unit and the testing platforms to send the golden calibration table to the testing platforms, and then, to cumulatively record calibration data produced after the testing platforms respectively test the DUTs, so that the server can further perform a weighted arithmetic operation to the calibration data so as to update the golden calibration table. Thereby, the purpose of accelerating the convergence speed of the golden calibration table can be achieved.

Abstract: The present invention provides a data processor capable of automatically discriminating a loop program and performing a reduction in power by size-variable lock control on an instruction buffer. The instruction buffer of the data processor includes a buffer controller for controlling a memory unit that stores each fetched instruction therein. When an execution history of a fetched condition branch instruction suggests condition establishment, and in the case that the branch direction of the fetched condition branch instruction is a direction opposite to the order of an instruction execution and the difference of instruction addresses from the branch source to the branch target based on the condition branch instruction is a range held in the storage capacity of the instruction buffer, the buffer controller retains an instruction sequence from a branch source to a branch target based on the condition branch instruction in the instruction buffer.

Abstract: A method and apparatus enable supplementing a Branch Target Buffer (BTB) table with a recent entry queue that prevents unnecessary removal of valuable BTB table data of multiple entries for another entry. The recent entry queue detects when the startup latency of the BTB table prevents it from asynchronously aiding the microprocessor pipeline as designed for and thereby can delay the pipeline in the required situations such that the BTB table latency on startup can be overcome. The recent entry queue provides a quick access to BTB table entries that are accessed in a tight loop pattern where the throughput of the standalone BTB table cannot track the throughput of the microprocessor execution pipeline. By using the recent entry queue, the modified BTB table processes information at the rate of the execution pipeline which provides acceleration thereof.

Abstract: In a processor executing instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, line and counter index addresses are formed that access every counter in a branch history table (BHT), and reduce the number of index address bits that are multiplexed based on the current instruction set execution mode. In one embodiment, counters within a BHT line are arranged and indexed in such a manner that half of the BHT can be powered down for each access in one instruction set execution mode.

Abstract: The invention relates to a microprocessor device and to a branch prediction method that determines which of a plurality of predetermined branch classes a respective branch instruction to be executed is assigned to, and determines whether the branch is likely to be taken or not, depending on the branch class determined. Advantageously, a respective adaptive branch prediction device assigned to the determined branch class is used for determining whether the branch is likely to be taken or not.

Abstract: Software hints embedded in branch instructions direct selection of one of a plurality of branch predictors to use when processing the branch instructions, leading to improved branch prediction (i.e. fewer mis-predictions) over conventional schemes. A software agent assembles branch instructions having associated respective branch predictor control fields compatible with a branch predictor selector and a plurality of branch predictors. Each branch predictor control field is used to perform branch predictor selection, branch predictor control, or both. Branch predictor selection enables selective branch prediction according to an appropriate one of the branch predictors as determined by the software agent by examining context surrounding the branch instruction. Branch predictor control enables control of operation of one or more of the branch predictors.

Abstract: A method, of manipulating a raw branch history (RBH), can include: providing a RBH relevant to a conditional branching instruction in a program; and filtering the RBH to obtain a filtered branch-prediction predicate. A related method, of making a branch prediction, can include: manipulating, as in the above-mentioned method, a RBH relevant to a given conditional branching instruction (CBI) to obtain a corresponding filtered branch-prediction predicate; and predicting a branching direction of the given CBI based upon the corresponding filtered branch-prediction predicate. Such methods operate upon data provided by a memory representing a Branch Register-Dependency Table (Br_RDT) that includes: entries corresponding to registers in a CPU, respectively; each entry in the Br_RDT being indicative of how content of a corresponding register in the CPU is dependent or not upon other ones among the plurality of registers in the CPU.

Abstract: Embodiments of the present invention provide a system that executes program code in a processor. The system starts by executing the program code in a normal mode using a primary strand while concurrently executing the program code ahead of the primary strand using a subordinate strand in a scout mode. Upon resolving a branch using the subordinate strand, the system records a resolution for the branch in a speculative branch resolution table. Upon subsequently encountering the branch using the primary strand, the system uses the recorded resolution from the speculative branch resolution table to predict a resolution for the branch for the primary strand. Upon determining that the resolution of the branch was mispredicted for the primary strand, the system determines that the subordinate strand mispredicted the branch. The system then recovers the subordinate strand to the branch and restarts the subordinate strand executing the program code.

Abstract: Embodiments of the present invention provide a system that executes program code in a processor. The system starts by executing the program code in a normal mode using a primary strand while concurrently executing the program code ahead of the primary strand using a subordinate strand in a scout mode. Upon resolving a branch using the subordinate strand, the system records a resolution for the branch in a speculative branch resolution table. Upon subsequently encountering the branch using the primary strand, the system uses the recorded resolution from the speculative branch resolution table to predict a resolution for the branch for the primary strand. Upon determining that the resolution of the branch was mispredicted for the primary strand, the system determines that the subordinate strand mispredicted the branch. The system then recovers the subordinate strand to the branch and restarts the subordinate strand executing the program code.

Abstract: The invention relates to a method and apparatus for controlling the instruction flow in a computer system and more particularly to the predicting of outcome of branch instructions using branch prediction arrays, such as BHTs. In an embodiment, the invention allows concurrent BHT read and write accesses without the need for a multi-ported BHT design, while still providing comparable performance to that of a multi-ported BHT design.

Abstract: A branch history stores execution history information of branch instructions, and predicts presence of a branch instruction and a corresponding branch destination. A first return address stack stores, when an execution of a call instruction of a subroutine is completed, address information of a return destination of a corresponding return instruction. A second return address stack stores, when presence of a call instruction of a subroutine is predicted, address information of a return destination of a corresponding return instruction. An output selecting unit selects, when presence of a return instruction is predicted, if address information is stored in the second return address stack, the address information as a result of the branch prediction with a highest priority, and outputs the address information selected.