Abstract: In a branch instruction target address cache, an entry associated with a fetched block of instructions includes a target address of a branch instruction residing in the next sequential block of instructions. The entry will include a sequential address associated with the branch instruction and a prediction of whether the target address is taken or not taken.

Abstract: The outcome of a plurality of branch instructions in a computer program is predicted by fetching a plurality or group of instructions in a given slot, along with a corresponding prediction. A group global history (gghist) is maintained to indicate of recent program control flow. In addition, a predictor table comprising a plurality of predictions, preferably saturating counters. A particular counter is updated when a branch is encountered. The particular counter is associated with a branch instruction by hashing the fetched instruction group's program counter (PC) with the gghist. To predict multiple branch instruction outcomes, the gghist is hashed with the PC to form an index which is used to access naturally aligned but randomly ordered predictions in the predictor table, which are then reordered based on value of the lower gghits bits. Preferably, instructions are fetched in blocks of eight instructions.

Abstract: A branch prediction scheme predicts whether a computer instruction will cause a branch to a non-sequential instruction. A prediction counter is selected by performing an exclusive or (XOR) operation between bits from an instruction address and a hybrid history. The hybrid history, in turn, is derived by concatenating bits from a global history register with bits from a local branch history table. The bits from the local branch history table are accessed by using bits from the instruction address.

Abstract: A branch prediction mechanism for predicting the outcome and the branch target address of the next possible branch instruction of a current instruction. Each of the entry of the branch target buffer (“BTB”) of the present invention provides a next possible branch instruction address, and the corresponding branch target address. By checking the TAG portion of each entry of the BTB with the current instruction address, the branch prediction mechanism can predict the next possible branch instruction and the corresponding branch target address.

Abstract: A branch prediction unit stores a set of branch prediction history bits and branch selectors corresponding to each of a group of contiguous instruction bytes stored in an instruction cache. While only one bit is used to represent branch prediction history, three distinct states are represented in conjunction with the absence of a branch prediction. This provides for the storage of fewer bits, while maintaining a high degree of branch prediction accuracy. Each branch selector identifies the branch prediction to be selected if a fetch address corresponding to that branch selector is presented. In order to minimize the number of branch selectors stored for a group of contiguous instruction bytes, the group is divided into multiple byte ranges. The largest byte range may include a number of bytes comprising the shortest branch instruction in the instruction set (exclusive of the return instruction). For example, the shortest branch instruction may be two bytes in one embodiment.

Abstract: A computing system contains an apparatus having an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch prediction entries, each branch prediction entry containing information for predicting whether a branch designated by a branch instruction stored in the instruction memory will be taken when the branch instruction is executed. Each branch prediction entry includes a branch target field for indicating a target address of a line containing a target instruction to be executed if the branch is taken, a destination field indicating where the target instruction is located within the line indicated by the branch target address, and a source field indicating where the branch instruction is located within the line corresponding to the target address.

Abstract: In one embodiment, a processor includes thread management logic including a thread predictor having state machines to indicate whether thread creation opportunities should be taken or not taken. The processor includes a predictor training mechanism to receive retired instructions and to identify potential threads from the retired instructions and to determine whether a potential thread of interest meets a test of thread goodness, and if the test is met, one of the state machines that is associated with the potential thread of interest is updated in a take direction, and if the test is not met, the state machine is updated in a not take direction. The thread management logic may control creation of an actual thread and may further include reset logic to control whether the actual thread is reset and wherein if the actual thread is reset, one of the state machines associated with the actual thread is updated in a not take direction.

Abstract: In one embodiment of the invention, a processor includes an execution pipeline to execute instructions, wherein at least some of the instructions are executed speculatively. The processor also includes a trace buffer outside the execution pipeline to hold the instructions, and wherein instructions that are associated with speculation errors are replayed in the execution pipeline from the trace buffer. In another embodiment, the processor includes an execution pipeline to execute instructions, wherein at least some of the instructions are executed speculatively. The processor also includes a trace buffer outside the execution pipeline to hold instructions and results of the execution of the instructions, wherein at least some of the instructions are subject to an initial retirement following execution in the pipeline, but remain in the trace buffer until a final retirement.

Abstract: An embodiment of the invention is directed at a method for accessing a cache by detecting a branch instruction having an address and containing a first set of bits representing a displacement value, and generating a modified instruction containing a second set of bits representing a combination based on the first set of bits and the address.

Abstract: An apparatus and method are shown for collecting a branch history value of a program executing in a processor. A current start address register latches a program count value in response to a trace termination condition, such as an indirect branch instruction. A current branch history register is cleared in response to the trace termination condition and shifts in a branch outcome value of the processor in response to a conditional direct branch instruction. A last trace start address latches the content of the current trace start address and a last branch history register latches the content of the current branch history register when a trace termination condition occurs.

Abstract: In a computer a system for branch prediction is arranged. The branch prediction system uses a scanning mechanism (303) for scanning the program memory for conditional branch instructions during the running of the program. When finding such an instruction the system records during a preset time interval (311) the statistics for that specific conditional branch instruction and sets a branch prediction but in the instruction accordingly (321). The system then starts to scan for the next conditional branch instruction in the program memory. The system can also be used for updating a BHT during the running of a program. The use of the system is particularly useful in applications when a program is run for a relatively long time such as a program used in a telephone switch. The use of the system also allows for changing branch predictions during the run of a program.

Abstract: An apparatus and method for improving the execution of conditional branch instructions is provided. A static branch predictor makes predictions about the outcomes of branch instructions based upon a combination of the test type (such as jump on overflow, jump if negative, jump if zero, jump on carry, etc.) and the sign of the displacement of the branch instruction. If the test type of the branch instruction is one of a subset of test types from which the branch outcome can accurately be predicted solely from the test type, then the predictor makes such a prediction. Otherwise, the predictor makes a prediction based upon the sign of the displacement used to calculate the branch target address. In this case, backward jumps are predicted taken and forward jumps are predicted not taken.

Abstract: A method and circuit is provided for preloading a branch prediction unit within a microprocessor. In one embodiment of the method, a branch history storage device such as branch history shift register is written with a predetermined multibit predicter in response to the microprocessor receiving and executing a special write branch history storage device instruction for writing the predetermined multibit predicter into the branch history storage device. The branch history storage device is contained within a prediction circuit of the microprocessor, and generally the contents of the branch history storage device is used in the process of predicting the results of executing conditional branch instructions prior to their execution.

Abstract: An apparatus and method for improving microprocessor performance by improving the prediction accuracy of conditional branch instructions is provided. A dynamic branch predictor speculatively updates global branch history information based on the prediction of a first branch instruction so that the predictor can predict the outcome of a second branch instruction following closely in the pipeline with the benefit of the first prediction. This improves the prediction accuracy where the first branch has not been resolved prior to the time when the second prediction is ready to be made. If the first prediction turns out to be incorrect, the global branch history is restored from a previously saved copy and updated with the first branch instruction's actual outcome.

Abstract: A microprocessor with an execution stage (26) including a plurality of execution units and an instruction memory (32) for storing instructions. The microprocessor further includes circuitry for retrieving (14) instructions from the instruction memory. This retrieving circuitry may retrieve one instruction simultaneously with the execution of another instruction by one of the plurality of execution units. Further, this retrieving circuitry includes a branch target memory (30) for storing a plurality of information fields (30r) corresponding to a branch instruction. The information fields include at least a target instruction address (Tn), a prediction field (Pn) indicating whether or not program flow should pass to the target instruction address, and an accuracy measure (PPAn) indicating accuracy for past prediction fields.

Abstract: Systems, apparatus, and methods are disclosed for generating pairs of conditional instructions corresponding to special predicate sequences from single instructions having a predicate. These pairs of conditional instructions update a destination register regardless of the truth or falsity of the predicate. The destination register is renamed to a new physical location. In this manner, register renaming can be used with predicate sequences to gain performance efficiencies and to overcome limitations of the prior attempted approaches.

Abstract: A branch prediction unit stores a set of branch selectors corresponding to each of a group of contiguous instruction bytes stored in an instruction cache. Each branch selector identifies the branch prediction to be selected if a fetch address corresponding to that branch selector is presented. In order to minimize the number of branch selectors stored for a group of contiguous instruction bytes, the group is divided into multiple byte ranges. The largest byte range may include a number of bytes comprising the shortest branch instruction in the instruction set (exclusive of the return instruction). For example, the shortest branch instruction may be two bytes in one embodiment. Therefore, the largest byte range is two bytes in the example. Since the branch selectors as a group change value (i.e. indicate a different branch instruction) only at the end byte of a predicted-taken branch instruction, fewer branch selectors may be stored than the number of bytes within the group.

Abstract: One embodiment of the present invention provides a system for predicting an address of an instruction following a branch instruction in a computer instruction stream. This system concurrently performs a fast single-cycle branch prediction operation to produce a first predicted address, and a more-accurate multiple-cycle branch prediction operation to produce a second predicted address. The system assumes that the first predicted address is correct and proceeds with a subsequent instruction fetch operation using the first predicted address. If the first predicted address is the same as the second predicted address, the subsequent instruction fetch operation is allowed to proceed using the first predicted address. Otherwise, the subsequent fetch operation is delayed so that it can proceed using the second predicted address.

Abstract: Each execution unit within a superscalar processor has an associated completion table that contains a copy of the status of all instructions dispatched but not completed. A central completion table maintains the status of every dispatched instruction as reported by the dispatch unit and the individual execution units. Execution units send finish signals to the completion table responsible for retiring a particular type of instruction. The central completion table retires instructions that may cause an interrupt and instructions whose results may target the same register. The execution units' associated completion tables retire the balance of the instructions and the execution units send instruction status to the central completion table and to each execution unit. This reduces the number of instructions that are retired by the central completion table, increasing the number of instructions retired per clock cycle.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A millimode capable computer system provides control to millicode to allow the BHT operations to continue except when the these special situations occur that require control of instruction fetch operations must be provided and the BHT can be turned off for some sections of code execution, but not disabled for all. A single free running BHT functions for both a normal mode and a millimode for the central processor which can execute in millimode with a branch history table directing instruction fetch for which both a global BHT disable and millicode disables exist. Hit detection logic receives input from the global BHT disable, as well as from an initialized control register bit and a processor control register bit to select the correct set target information and generate a "branch history table hit detected" control signal.

Abstract: Provided is a method for estimating statistics of properties of interactions among instructions processed in a pipeline of a computer system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. A set of instructions are randomly selected from the fetched instructions, a subset of the set of selected instructions concurrently executing with each other. A distances between the set of selected instructions is specified, and state information of the computer system is recorded while the set of selected instructions is being processed by the pipeline. The recorded state information is communicated to software where it is statistically analyzed for a plurality of sets of selected instructions to estimate statistics of the interactions among sets of selected instructions.

Abstract: A millimode capable computer system provides control to millicode to allow the BHT operations to continue except when the these special situations occur that require control of instruction fetch operations must be provided and the BHT can be turned off for some sections of code execution, but not disabled for all. A single free running BHT functions for both a normal mode and a millimode for the central processor which can execute in millimode with a branch history table directing instruction fetch for which both a global BHT disable and millicode disables exist. Hit detection logic receives input from the global BHT disable, as well as from an initialized control register bit and a processor control register bit to select the correct set target information and generate a "branch history table hit detected" control signal.

Abstract: In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding.

Abstract: A branch prediction unit stores as set of branch selectors corresponding to each of a group of contiguous instruction bytes stored in an instruction cache. Each branch selector identifies a branch prediction to be selected if a fetch address corresponding to that branch selector is presented. The branch prediction unit additionally stores a set of return selectors corresponding to one or more branch predictions. The return selectors identify the type of branch selection. For example, the branch predictions may include a sequential branch prediction and a branch instruction branch prediction. The return selectors may identify whether the branch instruction branch prediction is associated with the return instruction or a non-return branch instruction.

Abstract: A microprocessor (10) and a system (300) incorporating the same is disclosed, in which branch prediction is effected in response to the type of program in which branching instructions are contained. A fetch unit (26) includes a branch target buffer (56) and a plurality of pattern history tables (53). Select logic (80) receives signals indicating, for each branching instruction, the type of program containing the instruction, and selects one of the pattern history tables (53) for use in generating a prediction code in response to a portion of a branch history field (BH) in an entry (63) of the branch target buffer (56) corresponding to the instruction address. Disclosed examples of the signals used in selecting the pattern history table (53) include an indication (U/S) of the privilege level (e.g., user-level or supervisor-level) of the instruction.

Abstract: A microprocessor includes an instruction cache having a cache access time greater than the clock cycle time employed by the microprocessor. The instruction cache is banked, and access to alternate banks is pipelined. The microprocessor also includes a branch prediction unit. The branch prediction unit provides a branch prediction in response to each fetch address. The branch prediction predicts a non-consecutive instruction block within the instruction stream being executed by the microprocessor. Access to the consecutive instruction block is initiated prior to completing access to a current instruction block. Therefore, a branch prediction for the consecutive instruction block is produced as a result of fetching a prior instruction block. A branch prediction produced as a result of fetching the current instruction block predicts the non-consecutive instruction block, and the fetch address of the non-consecutive instruction block is provided to the instruction cache access pipeline.

Abstract: Instruction prediction based upon confidence and priority levels. A filtering effect is achieved by providing for prediction of an instruction by one of a plurality of predictors having (1) a confidence level satisfying a predetermined threshold value and (2) the highest priority level among the plurality of predictors. A default predictor is provided should no predictor satisfy this criteria. Efficient use of predictor memory is achieved through selective updating of predictors.

Abstract: A microprocessor capable of predicting program branches includes a fetching unit, a branch prediction unit, and a decode unit. The fetching unit is configured to retrieve program instructions, including macro branch instructions. The branch prediction unit is configured to receive the program instructions from the fetching unit, analyze the program instructions to identify the macro branch instructions, determine a first branch prediction for each of the macro branch instructions, and direct the fetching unit to retrieve the program instructions in an order corresponding to the first branch predictions.

Abstract: One aspect of the invention relates to a method for operating a processor. In one version of the invention, the method includes the steps of dispatching an instruction; determining a presently architected RMAP entry for the architectural register targeted by the dispatched instruction; selecting the RMAP entries which are associated with physical registers that contain operands for the dispatched instruction; updating a use indicator in the selected RMAP entries; determining whether the dispatched instruction is interruptible; and updating an architectural indicator and a historical indicator in the presently architected RMAP entry if the dispatched instruction is uninterruptible.

Abstract: An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the pipeline units processing a plurality of instructions including branch instructions. The instruction pipeline further includes a plurality of storage device which store a respective branch information data. Each of the storage devices are associated with at least one of pipeline units. Each respective branch information data is determined as a function of at least one of the branch instructions processed. Two of the pipeline units include branch prediction circuitry for predicting branch direction as a function of the stored branch information data.

Abstract: A method for a prediction correlation between a first group of branch instructions in a bunch of instructions and a second group of branch instructions in a bunch of instructions is disclosed. The method includes indicating a direction of a plurality of branch instructions in a bunch of instructions. More particularly, the method includes building an address composed of an instruction fetch address and bits in a history register. The method accesses a bunch of instructions using the fetch address and accesses a prediction bits set from a branch history table using the composed address. The accessed bunch of instructions are processed. Further, the history register and the branch history table are updated to correlate a first group of a branch instructions in the accessed bunch of instructions to a second group of branch instructions in a next group of branch instructions in the bunch of instructions.

Abstract: A mechanism is described that predicts the success or failure of prefetching instructions based on the previous performance of the instructions. A prefetching instruction is successful if the block of information prefetched into the cache is used by the processor before it is discarded from the cache. A prefetching instruction is unsuccessful, a failure, if the block of information prefetched into the cache is not used while in the cache. The prediction regarding the success or failure of the prefetching instruction is performed utilizing a table that records the history regarding the usefulness of each prefetch made by a prefetching instruction at a given memory location. The table is called a Touch-History-Table (THT). The THT is preferably accessed during the decode phase of each instruction using the memory location of the instruction. The table records the history of previous outcomes (success or failure) of the prefetching instruction up to the table size.

Abstract: To provide a branch prediction apparatus and its method that accesses BTB using IP of an instruction whose interval between the branch instruction is the smallest, on the basis of a branch instruction's fetch among the instructions that can be fetched prior to one cycle, and also that fetches the branch target after N cycle, after BTB accessing, storing the information of the cycle interval N1 between the branch access instruction and branch instruction inside BTB entry.

Abstract: A trace branch prediction unit includes a trace branch target buffer connected to a trace cache. The trace cache stores traces of micro-ops, with the micro-ops being stored non-sequentially. The trace branch target buffer generally reads a buffer entry corresponding to a particular trace line one clock cycle before the trace line is read to a processor. Using the entry, the trace branch target buffer predicts whether the trace cache should follow the existing trace or leave the trace. If the trace branch target buffer predicts that the trace cache should leave a trace, the trace branch target buffer provides a target address for a new trace. The trace branch target buffer also predicts when a trace is ending and provides a target address for the next trace.

Abstract: An apparatus for performing speculative stores is provided. The apparatus reads the original data from a cache line being updated by a speculative store, storing the original data in a restore buffer. The speculative store data is then stored into the affected cache line. Should the speculative store later be canceled, the original data may be read from the restore buffer and stored into the affected cache line. The cache line is thereby returned to a pre-store state. In one embodiment, the cache is configured into banks. The data read and restored comprises the data from one of the banks which comprise the affected cache line. Instead of forwarding store data to subsequent load memory accesses, the store is speculatively performed to the data cache and the loads may subsequently access the data cache. Dependency checking between loads and stores prior to the speculative performance of the store may stall the load memory access until the corresponding store memory access has been performed.

Abstract: A computer instruction supply system has store and fetch circuitry for obtaining a sequence of instructions, test circuitry for locating the first instruction in the sequence to be enabled, and for testing separately successive instructions in the sequence to locate any branch instruction which is predicted to be taken and control circuitry to disregard target addresses of branch instructions in the sequence prior to the first instruction to be executed.

Abstract: A branch prediction unit includes a first branch target buffer, a second branch target buffer, and a static predictor. The first branch target buffer is adapted for storing a first plurality of branch history entries. The second branch target buffer is adapted for storing a second plurality of branch history entries. The static predictor is adapted for determining a static branch prediction for an encountered branch instruction. The second branch target buffer is further adapted to allocate a branch history entry based on the static prediction. A method for predicting program branches in a microprocessor includes fetching a program instruction to be executed by the microprocessor. It is determined if an entry corresponding to the program instruction is stored in a first branch target buffer, and if an entry corresponding to the program instruction is stored in a second branch target buffer. It is determined if the program instruction is a branch instruction.

Abstract: An apparatus and a method for performing subroutine call and return operations in a computer having a processor with an instruction prefetch mechanism which includes a branch history table for storing target addresses of a plurality of branch instructions found in an instruction stream. The branch history table 22 contains a potential call instruction tag 37 and a return instruction tag 39. For each potential subroutine call instruction found in a prefetch instruction stream an address pair containing the call target address and the next sequential instruction address of the instruction is stored in a return identification stack 24. Subsequently detected branch instructions initiate an associative search on the next sequential instruction part in the return identification stack where a matching entry identifies the branch instruction as a return instruction. The address pair contained in the matching entry is then transferred to a return cache 30 which is arranged in parallel to the branch history table.

Abstract: A microprocessor is provided with an instruction fetch mechanism that simultaneously predicts multiple control-flow instructions. The instruction fetch unit further is capable of handling multiple types of control-flow instructions. The instruction fetch unit uses predecode data and branch prediction data to select the next instruction fetch bundle address. If a branch misprediction is detected, a corrected branch target address is selected as the next fetch bundle address. If no branch misprediction occurs and the current fetch bundle includes a taken control-flow instruction, then the next fetch bundle address is selected based on the type of control-flow instruction detected. If the first taken control-flow instruction is a return instruction, a return address from the return address stack is selected as the next fetch bundle address.

Abstract: An apparatus for predicting branch behavior during execution of branch instructions in a computer program. The apparatus comprises a branch table buffer (BTB) to store a plurality of branch addresses that are each generated during a function call and a plurality of branch histories associated with the branch addresses, the branch histories indicating whether or not an associated branch was previously taken. The apparatus further comprises circuitry coupled to the BTB to generate an index into the BTB using at least one level of context of the function call.

Abstract: A computing system that contains an apparatus comprising an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch prediction entries, each branch prediction entry containing information for predicting whether a branch designated by a branch instruction stored in the instruction memory will be taken when the branch instruction is executed. Each branch prediction entry includes a branch target field for indicating a target address of a line containing a target instruction to be executed if the branch is taken, a destination field indicating where the target instruction is located within the line indicated by the branch target address, and a source field indicating where the branch instruction is located within the line corresponding to the target address.

Abstract: A microprocessor includes an instruction fetch unit, a branch prediction unit, and a decode unit. The instruction fetch unit is adapted to retrieve a plurality of program instructions. The program instructions include serialization initiating instructions and branch instructions. The branch prediction unit is adapted to generate branch predictions for the branch instructions, direct the instruction fetch unit to retrieve the program instructions in an order corresponding to the branch predictions, and redirect the instruction fetch unit based on a branch misprediction. The branch prediction unit is further adapted to store a redirect address corresponding to the branch misprediction. The decode unit is adapted to decode the program instructions into microcode.

Abstract: A processor architecture is disclosed including a fetcher, packet unit and branch target buffer. The branch target buffer is provided with a tag RAM that is organized in a set associative fashion. In response to receiving a search address, multiple sets in the tag RAM are simultaneously searched for a branch instruction that is predicted to be taken. The packet unit has a queue into which fetched cache blocks are stored containing instructions. Sequentially fetched cache blocks are stored in adjacent locations of the queue. The queue entries also have indicators that indicate whether or not a starting or final data word of an instruction sequence is contained in the queue entry and if so, an offset indicating the particular starting or final data word. In response, the packet unit concatenates data words of an instruction sequence into contiguous blocks. The fetcher generates a fetch address for fetching a cache block from the instruction cache containing instructions to be executed.

Abstract: A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.

Abstract: The outcome of a given branch instruction is predicted using early and late branch history addressing modes. In an early addressing process, a first subset of bits from a branch history register is used to first address a branch history table to obtain a plurality of candidate predictions. In a late addressing process, a second subset of bits from the branch history register is used to again address the branch history table to select one of the plurality of candidate predictions, the second subset of bits including additional branch history information loaded into the branch history register subsequent to the early addressing mode. In this way, more recent branch history information is used to predict the outcome of the given branch instruction.

Abstract: A microprocessor (10) and a system (300) incorporating the same is disclosed, in which branch prediction is effected in response to the type of program in which branching instructions are contained. A fetch unit (26) includes a branch target buffer (56) and a plurality of pattern history tables (53). Select logic (80) receives signals indicating, for each branching instruction, the type of program containing the instruction, and selects one of the pattern history tables (53) for use in generating a prediction code in response to a portion of a branch history field (BH) in an entry (63) of the branch target buffer (56) corresponding to the instruction address. Disclosed examples of the signals used in selecting the pattern history table (53) include an indication (U/S) of the privilege level (e.g., user-level or supervisor-level) of the instruction.