Abstract: The present invention relates to an information processing apparatus provided with a branch history. An object of the present invention is to automatically designate a way in which an entry to be data-processed exists among a plurality of ways with which the branch history is provided, and is to speed up the process. In order to accomplish this objective, the present invention comprises an instruction fetch unit attaching way designation information designating a way in which the entry to be data-processed exists to the address of an instruction, and provides the information to an instruction execution unit in preparation for the case where the instruction fetched from a storage unit is a branch instruction and the data process of a branch history corresponding to the branch instruction is required.

Abstract: A pipeline process system, a super-scalar process system, or an out-of-order-execution process system is applied to an information processing device. A sequence of instructions containing a branch instruction, especially a subroutine, can be processed at a high speed using a branch history and a return address stack storing a return address corresponding to a subroutine call instruction. To successfully perform the process, when an instruction detected as a bit in the branch history is a subroutine return instruction, an address of a branched-to instruction registered in the branch history is compared with all return addresses stored in valid entries in the return address stack. A unit is provided to transmit a matching address as a return address of the return instruction to an instruction fetch unit for fetching an instruction.

Abstract: To provide a data processing apparatus that allows the occurrence of a gate disturb effect to be reduced and the reliability of data processing using the internal flash memory to be improved. A loop process section of a program stored in flash memory is held in a storage area in SRAM that corresponds to a range from an address specified by the SRAM start address storage to a value specified by a SRAM size storage, thereby the section is read only from the SRAM when the loop process is performed the subsequent times. Thus, if the program is looped, the flash memory is not accessed and therefore the frequency of normal reads from the flash memory decreases to minimize the occurrence of the gate disturb effect, allowing the flash memory to hold data that is stable for an extended period of time.

Abstract: A branch prediction scheme predicts whether a computer instruction will cause a branch to a non-sequential instruction. A prediction counter is selected by performing an exclusive or (XOR) operation between bits from an instruction address and a hybrid history. The hybrid history, in turn, is derived by concatenating bits from a global history register with bits from a local branch history table. The bits from the local branch history table are accessed by using bits from the instruction address.

Abstract: A branch prediction unit includes a local branch prediction and a global branch prediction. A global branch prediction utilizes a global history shift register to record the behavior of conditional branches. In some cases, a conditional branch may behave in a static manner, either always being taken or not taken, while resident in an instruction cache. Such static behaving conditional branches do not need a global history for prediction and contend with other conditional branches for global branch history training. By utilizing a dynamic branch classification scheme, branches requiring global history prediction can be identified and static behaving conditional branches may be prevented from polluting the global history. All conditional branches are initially classified as local and do not participate in global history training. Only after two mispredictions are branches recognized as exhibiting dynamic behavior and classified as global.

Abstract: An apparatus and method are provided for accurately predicting the outcome of branch instructions prior to their execution by a pipeline microprocessor. The apparatus includes a first table, a second table, and selection logic. The first table stores branch histories for a first set of branch instructions. The second table stores branch histories for a second set of branch instructions. The first set of branch instructions, when executed, exhibit a tendency toward being taken. The second set of branch instructions, when executed, exhibit a tendency toward being not taken. The selection logic is coupled to the first and second tables. When a branch instruction is executed by the microprocessor, the selection logic selects a particular branch history to predict the outcome of the branch instruction. The particular branch history is selected based upon the branch instruction's exhibited outcome tendency.

Abstract: An apparatus for branch prediction includes a history register which stores therein history of previous branch instructions, an index generation circuit which generates a first index from an instruction address and the history stored in the history register, a history table which stores therein a portion of the instruction address as a tag and a first value indicative of likelihood of branching in association with the first index, a branch destination buffer which stores therein a branch destination address or predicted branch destination address of an instruction indicated by the instruction address and a second value indicative of likelihood of branching in association with a second index that is at least a portion of the instruction address, and a selection unit which makes a branch prediction by selecting one of the first value and the second value.

Abstract: A memory cache method and apparatus with two memory execution pipelines, each having a translation lookaside buffer (TLB). Memory instructions are executed in the first pipeline (324) by searching a data cache (310) and a prefetch cache (320). A large data TLB (330) provides memory for storing address translations for the first pipeline (324) A second pipeline (328) executes memory instructions by accessing the prefetch cache (320). A second micro-TLB (340) is associated with the second pipeline (328). It is loaded in anticipation of data that will be referenced by the second pipeline (328). A history file (360) is also provided to retain information on previous instructions to aid in deciding when to prefetch data. Prefetch logic (370) determines when to prefetch data, and steering logic (380) routes certain instructions to the second pipeline (328) to increase system performance.

Abstract: Improved conditional branch instruction prediction by detecting branch aliasing in a branch history table. Each entry in an aliasing table is associated with only one of a plurality of conditional branch instructions tracked by the branch history table. Prior to executing a conditional branch instruction, outcome of the execution of the conditional branch instruction is predicted utilizing the branch history table entry associated with the conditional branch instruction. Outcome of the execution of the conditional branch instruction is also predicted utilizing the aliasing table entry associated with the conditional branch instruction. Branch aliasing is detected by comparing the prediction made utilizing the branch history table with the prediction made utilizing the aliasing table.

Abstract: A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction unit (BPU) (28). The instruction buffer (20) and/or the completion unit (24) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) bits. The branch prediction unit contains a plurality of branch prediction buffers (28a-28c). The SID bits are used to associate the pending and executing instructions in the units (20 and 24) into instruction streams related to predicted branches located in the buffers (28a-28c). The SID bits as well as age bits associated with the buffers (28a-28c) are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.

Abstract: A DAG trace cache includes traces, each storing information about interdependent instructions and the interdependency among the instructions. The interdependent instructions include a criterion instruction and are part of a program sequence that is stored in an instruction cache. The information is in the form of a directed acyclic graph. The interdependent instructions include the criterion instruction and instructions preceding the criterion instruction in the program sequence. The information in the DAG trace is used to accelerate executions of the instructions on a processor.

Abstract: A superscalar processor and method are disclosed for improving the accuracy of predictions of a destination of a branch instruction utilizing a cache. The cache is established including multiple entries. Each of multiple branch instructions are associated with one of the entries of the cache. One of the entries of the cache includes a stored predicted destination for the branch instruction associated with this entry of the cache. The predicted destination is a destination the branch instruction is of predicted to branch to upon execution of the branch instruction. The stored predicted destination is updated in the one of the entries of the cache only in response to two consecutive mispredictions of the destination of the branch instruction, wherein the two consecutive mispredictions were made utilizing the one of the entries of the cache.

Abstract: Each of plural rows in an aligned Instruction cache (AIC) contains a plurality of aligned sectors, each sector having space for a block of sequentially-addressed instructions in an executing program. A “fetch history table” (FHT) contains FHT sets of FHT entries for specifying execution sequences of the sectors in associated AIC rows. Each FHT entry in a FHT set specifies an AIC row and a sector sequence arrangement to be outputted from that row. In this manner, each FHT entry can associate itself with any row in the AIC and is capable of specifying any output order among the sectors in its associated row. Unique fields are selected in each instruction address for locating an associated FHT set, and for associating the instruction address with an AIC sector through a unique “sector distribution table” (SDT) to locate the sector which starts with the instruction having this instruction address.

Abstract: A microprocessor having a correlated address predictor, and methods of performing correlated address prediction. A first table memory can be populated by a plurality of buffer entries. Each buffer entry can include a first buffer field to store a first tag based on an instruction pointer and a second buffer field to store an address history. A second table memory can be populated by a plurality of link entries. Each link entry can include a first link field to store a link tag based on an address history and a second link field to store a predicted address. A first comparator can be in communication with the first table memory and an instruction pointer input. A second comparator can be in communication with the first table memory and the second table memory. An output in communication with the second table memory.

Abstract: A microprocessor is disclosed. The microprocessor includes a branch prediction table that has at least one branch entry. The at least one branch entry includes a prediction field to indicate whether a branch is predicted taken. The at least one branch entry also includes a history register that stores history information. Moreover, the branch prediction table includes a prediction update logic that updates the prediction field and the history register except when a branch is strongly predicted statically.

Abstract: An apparatus is presented for expediting the execution of dependent micro instructions in a pipeline microprocessor having design characteristics-complexity, power, and timing—that are not significantly impacted by the number of stages in the microprocessor's pipeline. In contrast to conventional result distribution schemes where an intermediate result is distributed to multiple pipeline stages, the present invention provides a cache for storage of multiple intermediate results. The cache is accessed by a dependent micro instruction to retrieve required operands. The apparatus includes a result forwarding cache, result update logic, and operand configuration logic. The result forwarding cache stores the intermediate results. The result update logic receives the intermediate results as they are generated and enters the intermediate results into the result forwarding cache.

Abstract: Instruction prediction based upon confidence and priority levels. A filtering effect is achieved by providing for prediction of an instruction by one of a plurality of predictors having (1) a confidence level satisfying a predetermined threshold value and (2) the highest priority level among the plurality of predictors. A default predictor is provided should no predictor satisfy this criteria. Efficient use of predictor memory is achieved through selective updating of predictors.

Abstract: The inventive mechanism provides fast profiling and effective trace selection. The inventive mechanism partitions the work between hardware and software. The hardware automatically detects which code is executed very frequently, e.g. which code is hot code. The hardware also maintains the branch history information. When the hardware determines that a section or block of code is hot code, the hardware sends a signal to the software. The software then forms the trace from the hot code, and uses the branch history information in making branch predictions.

Abstract: A branch predicting apparatus is disclosed that reduces branch mispredictions in a processor. The branch prediction apparatus includes a base misprediction history register. The branch prediction apparatus includes a meta predictor that receives an index value and a branch prediction to generate a misprediction value in accordance with the base misprediction history register. The branch prediction apparatus also includes a logic gate that receives the branch prediction and the misprediction value to generate a final prediction. The final prediction may be used to predict whether a branch is taken or not taken.

Abstract: Apparatus and methods implemented in a processor semiconductor logic chip for providing novel “hint instructions” that uniquely preserve and reuse branch predictions replaced in a branch history table (BHT). A branch prediction is lost in the BHT after its associated instruction is replaced in an instruction cache. The unique “hint instructions” are generated and stored in a unique instruction cache which associates each hint instruction with a line of instructions. The hint instructions contains the latest branch history for all branch instructions executed in an associated line of instructions, and they are stored in the instruction cache during instruction cache hits in the associated line. During an instruction cache miss in an instruction line, the associated hint instruction is stored in a second level cache with a copy of the associated instruction line being replaced in the instruction cache.

Abstract: To make a branch prediction, a branch prediction apparatus determines a trigger load instruction whose value feeds into the branch instruction. A hash value is associated with the branch instruction. The branch prediction apparatus computes the hash value based on the trigger load instruction. If the hash value has not changed, the branch prediction apparatus predicts the branch to be chosen based on past predictions for the hash value.

Abstract: A computer system has a processor that has a prediction array that avoids conflicts when the prediction array is accessed twice in once clock cycle to retrieve predictions for two separate conditional branch instructions. The prediction array is included as part of a branch prediction logic circuit that includes a bank control logic coupled to the prediction array. The bank control logic assures the conflict noted above is avoided. The prediction array preferably comprises multiple (e.g., 4) single-ported bank memory elements, each bank comprising multiple predictions. The bank control logic uses information associated with a previously fetched and branch predicted conditional branch instruction to generate a bank number for a current branch instruction. The generated bank number corresponds to one of the banks in the prediction array. The processor preferably fetches two (or more) groups (also called “slots”) of instructions each cycle.

Abstract: A technique for managing register assignments. The technique involves maintaining, in a register list memory circuit having entries that respectively correspond to physical registers, a list of register assignments that assign logical registers to the physical registers. The technique further involves maintaining, in a vector memory circuit having bits that respectively correspond to the physical registers, a valid vector that forms, in combination with the list of register assignments, a list of valid register assignments. Furthermore, the technique involves storing, for an instruction that is mapped by the data processor, a copy of the valid vector from the vector memory circuit to a silo memory circuit. Preferably, the processor using the technique has the ability to execute branches of instructions speculatively, and to recover if it is determined that the processor executed down an incorrect instruction branch.

Abstract: A method and apparatus for ensuring that information transfers from memory to a peripheral device are complete prior to the peripheral device executing instructions responsive to the content of the information is described. The method includes identifying lines of data to be written, determining a unique start code to be used for that data, and embedding that start code into that data. When the proper number of lines of data have arrived in peripheral device memory, the pending operation is executed.

Abstract: A method and circuit is provided for preloading a branch prediction unit within a microprocessor. In one embodiment of the method, a branch history storage device such as branch history shift register is written with a predetermined multibit predicter in response to the microprocessor receiving and executing a special write branch history storage device instruction for writing the predetermined multibit predicter into the branch history storage device. The branch history storage device is contained within a prediction circuit of the microprocessor, and generally the contents of the branch history storage device is used in the process of predicting the results of executing conditional branch instructions prior to their execution.

Abstract: A system which permits dynamic verification of the availability of a desired time at which to load a data requested by a load instruction. The system comprises (i) means for appending a time dependency value to the load instruction, where the time dependency value corresponds to the desired time, (ii) means for verifying that said desired time is available for loading said data, and (iii) means for sending an acknowledgement (ACK) when the desired time is available, where a processor reserves the system resources for accepting the data at the desired time in response to the ACK.

Abstract: A transfer tag is generated by the Instruction Fetch Unit and passed to the decode unit in the instruction pipeline with each group of instructions fetched during a branch prediction by a fetcher. Individual instructions within the fetched group for the branch pipeline are assigned a concatenated version (group tag concatenated with instruction lane) of the transfer tag which is used to match on requests to flush any newer instructions. All potential instruction or Internal Operation latches in the decode pipeline must perform a match and if a match is encountered, all valid bits associated with newer instructions or internal operations upstream from the match are cleared. The transfer tag representing the next instruction to be processed in the branch pipeline is passed to the Instruction Dispatch Unit. The Instruction Dispatch Unit queries the branch pipeline to compare its transfer tag with transfer tags of instructions in the branch pipeline.

Abstract: In branch prediction in accordance with the present invention, in order to reduce the storage capacity for storing branch prediction information and simplify an information retrieval circuit while minimizing reduction in branch prediction accuracy, the position of an instruction is stored in advance and an instruction is decoded for execution, the relative position of the instruction decoded for execution is obtained on the basis of the position of the stored instruction, and when the decoded instruction is a branch instruction the result of branch by the branch instruction is recorded as history information in correspondence with the relative position of the branch instruction.

Abstract: In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically In software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding.

Abstract: In one method, a predicted predicate value for a predicate is determined. A predicated instruction is then conditionally executed depending on the predicted predicate value. For example, in accordance with one embodiment of the present invention, a predicate table stores historical information corresponding to a predicate. A pipeline coupled to the table receives a predicted predicate value calculated from the historical information. The pipeline may use this predicted predicate value to conditionally execute a predicated instruction. The actual predicate value is provided back to the predicate table from the pipeline.

Abstract: Interference in a branch history table of a microprocessor is reduced by methods and apparatus which predict the outcome of branch instructions (taken or not taken) through a combination of static and dynamic prediction techniques. Static prediction information (e.g., a compiler hint) may be stored in instruction memory, and dynamic prediction information is stored in a branch history table. A branch prediction results from an exclusive OR of static and dynamic prediction information. After execution of a branch instruction, an indication as to whether a branch was taken or not taken is exclusively ORed with the static prediction information for the branch instruction, and the result of this exclusive OR is used to update an appropriate entry in the branch history table.

Abstract: Methods and apparatus for storing data in a multi-level memory hierarchy having at least a lower level cache and a higher level cache. Relevancy information is maintained for various data values stored in the lower level cache, the relevancy information indicating whether the various data values stored in the lower level cache, if lost, could only be generated from corresponding data stored in the higher level cache. If one of the various data values stored in the lower level cache is to be updated, a determination as to whether corresponding data should be stored in the higher level cache is based at least in part on 1) the status of the relevancy information corresponding to the one of the various data values stored in the lower level cache which is to be updated, and 2) whether the updated value which is to be written into the lower level cache matches one or more select data value patterns.

Abstract: This invention is a method and system for hybride prediction of load addresses and/or values. The new scheme for value prediction allows to predict last values, strides as well as values out of context without the use of a sophisticated switching scheme between several predictors. The system collects patterns of deltas of subsequent values instead of the values itself in a first table (40). Thus, a last value prediction can be achieved by predicting a ‘pattern’ of just one stride which is zero. A stride predictor uses a pattern of one constant stride. And a certain pattern of values is modelled by recording the pattern of deltas between the values and adding the deltas to the last value. The switching scheme inherently includes the system itself and operates basically by immediate evaluation of counters in the pattern history table (44).

Abstract: The inventive mechanism provides fast profiling and effective trace selection. The inventive mechanism partitions the work between hardware and software. The hardware automatically detects which code is executed very frequently, e.g. which code is hot code. The hardware also maintains the branch history information. When the hardware determines that a section or block of code is hot code, the hardware sends a signal to the software. The software then forms the trace from the hot code, and uses the branch history information in making branch predictions.

Abstract: Disclosed is a circuit and method for multiple access of a branch history table during a single clock cycle. In accordance thereto, a first branch history table index is generated which is used for accessing the branch history table. A first counter value is read from the branch history table in response to accessing the branch history table using the first branch history table index. A second branch history table index is also generated for accessing the branch history table. A pair of counter values are read from the branch history table in response to accessing the branch history table using the second branch history table index. One of the pair of counter values is selected based upon the value of the first counter value read from the branch history table. The first and second counter values in turn are used for predicting corresponding first and second branch instructions. The first and second branch history table indexes are generated in the same cycle.

Abstract: A line predictor is configured to speculatively fetch instructions following a branch instruction. The line predictor stores a plurality of lines that each contain instruction line information. Each line stored by the line predictor includes a fetch address, information regarding one or more instructions, and one or more next fetch addresses. In response to receiving a fetch address, the line predictor is configured to provide instruction line information corresponding to the one or more instructions located at the fetch address to an alignment unit. The line predictor is also configured to provide a next fetch address associated with the fetch address to an instruction cache for speculative fetching and to a branch prediction unit for a branch prediction. The next fetch address is further fed back into the line predictor to generate the instruction line information associated with it and a subsequent next fetch address.

Abstract: In branch prediction in a superscalar processor, a fetch block address is stored in a program counter (31) to make an access to a prediction table (32) not only when a branch instruction is predicted but also when an execution history (prediction information) of the branch instruction is registered or updated on the basis of the executed result of the branch instruction.

Abstract: A branch prediction architecture is disclosed, having a branch predictor, a target address register, first and second multiplexors, a cache memory, and a trace cache. The branch predictor may advantageously be a series-parallel branch predictor, and alternatively may be a serial-BLG branch predictor or a choosing branch predictor. The first multiplexor receives an input from the target address register, and provides an output to the cache memory. The cache memory receives output from both the branch predictor and the first multiplexor, and provides an output to the second multiplexor. The trace cache receives the output from the branch predictor, and provides an output received by the second multiplexor. The second multiplexor, receiving input from both the trace cache and the cache memory, outputs branch predictions and instruction bundles.

Abstract: Disclosed is a method for creating a verification environment to drive a Branch History Table. It consists of two components. First, a method for creating instruction streams for controlling the stress on branch history table logic. The second is a method for pre-loading the branch history array to allow for interesting simulations at the beginning of the test.

Abstract: Disclosed is a predictive instruction cache system, and the method it embodies, for a VLIW processor. The system comprises: a first cache; a real or virtual second cache for storing a subset of the instructions in the second cache; and a real or virtual history look-up table for storing relations between first instructions and second instructions in the second cache. If a first instruction is located in a stage of the pipeline, then one of the relations will predict that a second instruction will be needed in the same stage a predetermined time later. The first cache can be physically distinct from the second cache, but preferably is not, i.e., the second cache is a virtual array. The history look-up table can also be physically distinct from the first cache, but preferably is not, i.e., the history look-up table is a virtual look-up table. The first cache is organized as entries.

Abstract: A profiler that operates in a multi-stage environment is disclosed. As program code undergoes a series of transformations, branches of interest are selected and tracked. Regardless of how many transformations are involved only a single instrumentation/data gathering phase is required. The gathered profile data is then used to perform various optimizations at the differing transformation stages.

Abstract: The present invention efficiently and accurately predicts indirect branch target addresses in computer code, thereby significantly increasing processing speed. According to the present invention, an optimizing compiler inserts indirect branch target address hints in advance of their corresponding indirect branches, thereby allowing the processor time to execute and utilize the hints. The present invention avoids the processor pipeline flushes associated with previous hardware solutions by allowing more accurate prediction of indirect branch target addresses. In addition, the present invention is not dependent upon having a large cache memory associated with the microprocessor or repeatedly encountering the same indirect branch within a certain preset period of time. Moreover, the present invention avoids the performance and compile time problems of the software solutions of the prior art by maintaining the indirect branch constructs.

Abstract: In one method, a predicted predicate value for a predicate is determined. A predicated instruction is then conditionally executed depending on the predicted predicate value.

Abstract: A method and apparatus for prefetching superblocks in a computer processing system having a fetch mechanism for fetching instructions for execution includes the step of controlling the fetch mechanism to begin fetching at a starting address of a current superblock. A superblock includes a set of instructions in consecutive address locations terminated by a branch instruction known to have been taken. A Superblock Target Buffer (STB) is supplied with the starting address of the current superblock. The STB has a plurality of entries each indexed by a starting address of a superblock and including a run length of the superblock and a target address of the terminating branch of the superblock. The run length corresponds to the sum of a length of the terminating branch and the difference between a starting address of the terminating branch of the superblock and the starting address of the superblock.

Abstract: A branch predictor generates an index to access a branch prediction table storing branch prediction reference data therein, considering a branch history, a branch instruction address, and a process ID. Accordingly, although context switching frequently occurs and a plurality of processes are under operation simultaneously in single microprocessor, the branch predictor has a high hit ratio of branch prediction. From the standpoint of an operating system of a computer system, the hit ratio is enhanced to reduce a stall phenomenon in the pipeline. As a result, program execution time can be shortened.

Abstract: A method for associating subroutine calls with corresponding targets includes the step of maintaining a first table of entries. Each entry in the first table includes: a first table first address identifying an entry point address for a corresponding subroutine; and a first table second address identifying a return address of a return for the corresponding subroutine. A second table of entries is also maintained. Each entry in the second table includes: a second table first address identifying a return address of a return for a respective subroutine called by a corresponding subroutine call instruction; a second table second address identifying a target address of the return for the respective subroutine; and a second table third address identifying an entry point address for the respective subroutine. It is determined whether the second table stores an entry whose second table first address corresponds to a return address of a return for a considered subroutine.

Abstract: A method and apparatus for performing multiple branch predictions per cycle is disclosed. The method and apparatus according to the present invention determine, within one fetch cycle, which instructions in a plurality of fetch instructions are branches and whether such branches are taken or not taken thereby finding the oldest taken branch, which has a target address that is fetched within the same fetch cycle.

Abstract: The data processor that addresses instructions as groups of commands which may contain more than one branch command, such as VLIW instructions that contain several commands for parallel execution. The processor selects an expected taken branch command from the branch commands in a group. The processor also selects a tentative target for the expected taken branch command and tentatively redirects control flow to a further group of commands identified by the tentative target. The processor contains an associative target memory for storing targets of previously executed branch commands. Targets are retrieved with an associative address that identifies a command in the group, the tentative target being selected on the basis of a match between the associative address associated with the tentative target and an indication of the expected taken command.

Abstract: In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding.

Abstract: A branch prediction unit stores a set of branch selectors corresponding to each of a group of contiguous instruction bytes stored in an instruction cache. Each branch selector identifies the branch prediction to be selected if a fetch address corresponding to that branch selector is presented. In order to minimize the number of branch selectors stored for a group of contiguous instruction bytes, the group is divided into multiple byte ranges. The largest byte range may include a number of bytes comprising the shortest branch instruction in the instruction set (exclusive of the return instruction). For example, the shortest branch instruction may be two bytes in one embodiment. Therefore, the largest byte range is two bytes in the example. Since the branch selectors as a group change value (i.e. indicate a different branch instruction) only at the end byte of a predicted-taken branch instruction, fewer branch selectors may be stored than the number of bytes within the group.