Abstract: An instruction control apparatus, and method, used with a device including a cache memory, a lower memory, an instruction fetch device issuing an instruction fetch request for a target of a first branch instruction to the cache memory, and an instruction control device processing a instruction sequence stored in the cache memory. The apparatus and method pre-prefetch a target instruction sequence for a target of a second branch instruction. A predetermined instruction sequence based on a past history is preliminarily transferred from the lower memory to the cache memory when the target instruction sequence for the target of the first branch instruction is not in the cache memory.

Abstract: A microcontroller, connected to a memory which stores instructions and data, includes an instruction execution unit for reading instructions and data from the memory and processing the read instructions and a prefetch circuit unit that receives the instructions and data read from the memory and detects pseudo instructions included in the instructions and data. A pseudo instruction precedes a branch instruction and indicates the existence of the branch instruction and the branch to address. The prefetch circuit unit includes a prefetch buffer connected between the instruction execution unit and the memory for temporarily storing instructions and data being transferred from the memory to the instruction execution unit and a pseudo instruction buffer for temporarily storing instructions and data located at the address of the branch instruction which follows the pseudo instruction.

Abstract: A branch predictor generates an index to access a branch prediction table storing branch prediction reference data therein. The index is generated in response to a combination of a branch history, a branch instruction address, and a process ID. The process ID is derived from one of multiple processes operating on a multi-processing computer with which the branch predictor is associated.

Abstract: A system and method for pre-fetching data. A computer program comprising multiple basic blocks is submitted to a processor for execution. Tables or other data structures are associated with some or all of the basic blocks (e.g., a table is associated with, or stores, an instruction address of a particular basic block). During execution of a basic block, memory locations of data elements accessed during the executions are stored in the associated table. After a threshold number of executions, differences between memory locations of the data elements in successive executions are then computed. The differences are applied to the last stored memory locations to generate estimates of the locations for the data elements for a subsequent execution. Using the estimated locations, the data elements can be pre-fetched before, or as, the basic block is executed.

Abstract: According to one embodiment a computer system is disclosed. The computer system includes a microprocessor and a chipset coupled to the microprocessor. The microprocessor removes stale branch instructions prior to the execution of a first cache line by finding existing branch prediction data for the first cache line.

Abstract: In a conventional information processor that performs speculative execution of a following instruction having a data dependency, since an arithmetic and logical unit is used in performing the speculative execution and the same ALU is used again when the prediction is wrong, the frequency of use of the ALU increases. To prevent this, a history ALU for outputting a past execution result of an instruction, as it is, as an execution result of the instruction and an instruction issue circuit for issuing an instruction whose operand is the same as a past value to the history ALU are provided with an intention of omitting the actual speculative execution. A Guard cache provided in the history cache stores addresses of instructions that give low prediction accuracy, whereby any instruction whose address has been registered in the Guard cache is prevented from being registered again in the history cache.

Abstract: The present invention relates to a branch prediction logic and method for generating a branch bias providing a prediction as to whether execution of a branch instruction will result in a branch being taken or not taken. The branch prediction logic comprises a first branch bias storage operable to store for each of a plurality of first address portions a corresponding first branch bias value, the first branch bias storage being operable upon receipt of a first address portion of the branch instruction's address to output the corresponding first branch bias value from the first branch bias storage. The history storage is also provided for storing history data identifying an outcome for a number of preceding branch instructions.

Abstract: Toggling between accessing an entry in a global history with a stew created from branch predictions implied by the ordering of instructions within a trace of a trace cache when a trace is read out of a trace cache, and accessing an entry in a global history with repeatable variations of a stew when there is more than branch instruction within a trace within the trace cache and at least a second branch instruction is read out.

Abstract: A processor including a branch prediction unit, wherein various techniques can be used to decrease branch prediction unit access, possibly saving power. Whether or not a branch prediction target needs updating may be stored, and thus it may be known whether or not the branch prediction unit needs to be accessed after the initial access. Which way corresponds to the prediction may be stored, decreasing the amount of subsequent accesses. Use information (e.g., least recently used information) may be updated at the time of the first access of the branch prediction unit, possibly eliminating the need for a later use information update. A branch prediction unit update or allocate, or update or allocate attempt, may be performed prior to the execute stage.

Abstract: For each predicted branch within a processor, an entry is maintained within a branch history table. The entry within the branch history table also includes an indication of the past record for that particular branch instruction, which indicates how correct the branch prediction has been in the past. When the field value associated with the predicted branch exceeds a certain threshold, indicating that the past predictions associated with that branch instruction have been at an unacceptable level, then the speculative branch instructions dispatching is suspended for that particular branch instruction. Alternative embodiments utilize a global indicator for suspending or cancelling instruction dispatch when the frequency of previous incorrect branch predictions increases beyond a preselected threshold.

Abstract: An invention is disclosed for a layer structure that facilitates configuring a Fiber Channel driver. In one embodiment, the layer structure includes a hardware layer directory that includes code for communicating with a Fiber Channel controller. In addition, a wrapper layer directory is included in the layer structure. The wrapper layer directory includes code for communicating with the code associated with the hardware layer directory, and also includes a wrapper header file that defines a particular value setting in a first state, such as a compiler directive set a particular value. The layer structure further includes a global header directory that defines a group of value settings. The group of value settings is defined for the code associated with each of the hardware directory and the wrapper layer directory. The particular value setting in the first state is also included in the group of value settings.

Abstract: Associated with an instruction in a program is a computation history. The computation history represents all objects that affect the result of the instruction, such objects including (but not limited to) registers, memory locations, static values, and instruction program counters. The computation history may be used to make a prediction about a property of the instruction.

Abstract: When a branch instruction for awaiting an event is detected in an information processing apparatus which performs a pipeline process including a branch prediction, a branch prediction for the branch instruction is suppressed. As a result, a prefetch operation for an instruction subsequent to the branch instruction is promoted, and the subsequent instruction is immediately executed when the event to be awaited occurs.

Abstract: A system and method for recovering a global history vector is implemented. In deeply pipelined central processing unit (CPU) architecture instruction fetches may precede execution by several processor cycles. A global history vector (GHV) may be used in predicting the branches in a current fetch cycle. Fetch redirection events, such as a cache miss, or a branch misprediction may lead to loss of synchronization of instruction fetches and the GHV. To recover the GHV following a redirection event, registers are provided to hold a GHV being used to predict branches in a current fetch cycle and two subsequent GHVs. On the occurrence of a redirection event, a fetch redirection is generated. GHV update logic detects the fetch redirection and resets the current GHV to a selected one of the stored values.

Abstract: A method is disclosed for selecting data in a computer system having a cache memory and a branch history table, where the method includes predicting an address corresponding to the data, selecting data at the predicted address in the cache memory, translating an address corresponding to the data, comparing the translated address with the predicted address, and if they are different, re-selecting data at the translated address in the cache memory and appending the translated address to the branch history table.

Abstract: A method for improving prediction of an outcome for a branch instruction in a set of instructions includes storing local branch history data for the branch instruction, using the local branch history data to predict the outcome of the branch instruction, and speculatively updating the local branch history data with the predicted outcome of the branch instruction. An apparatus for improving prediction of an outcome for a branch instruction in a set of instructions includes a memory for storing local branch history data for the branch instruction and a processor for using the local branch history data to predict the outcome of the branch instruction and speculatively updating the local branch history data with the predicted outcome of the branch instruction.

Abstract: A next address computing section contains a selector and is connected to an instruction cache. The instruction cache maintains a predecode result of a branch instruction or predefined settings for a field in this branch instruction. Based on this information maintained in the instruction cache, the selector determines whether the compiler performed a branch prediction about the branch instruction or could not perform that branch prediction. When the compiler could not perform the branch prediction, the selector selects an output from a conditional branch prediction device (saturation counter section). When the compiler performed the branch prediction, the selector selects a prediction result by the compiler for a prediction in Agree mode. These selection results are used for setting a value of a register holding the next address. Based on this next-address register value, an instruction is fetched from the cache then inserted into a pipeline.

Abstract: Mechanisms and techniques allow a host computer system to control caching operations within a data storage system. In a typical implementation, the system of the invention operates within a host computer system to intercept requests for access to data stored within a data storage system that originate from applications, programs or other processes that perform (e.g., execute) on the host computer system or another computer system. Once intercepted, the host computer can examine such a request for access to data to determine if the request matches any prefetch criteria defined within a prefetch database provided by the system of the invention. As an example, prefetch criteria defined in a prefetch database can specify various requestors (e.g., applications, programs, processes, users, or the like) that can access data (e.g., specific files, databases, volumes, data types or the like) stored within the data storage system according to various data access techniques (e.g.

Abstract: An indirect branch predictor includes a buffer storing branch target addresses corresponding to previously executed indirect branch instructions. The buffer is indexed with an index derived from history information corresponding to previously predicted indirect branch instructions and from the PC of the particular indirect branch instruction being predicted. In one embodiment, the buffer may be tagless and/or direct mapped. In various embodiments, the indirect branch target predictor may generate the index to the buffer using one or more techniques to improve the accuracy of the prediction: (i) offsetting the history information from the various previously predicted indirect branch instructions; (ii) weighting the history information based on the age of the previously predicted indirect branch instructions; and/or (iii) reversing the bit order of the PC of the particular indirect branch instruction being predicted.

Abstract: An indirect branch predictor includes a buffer storing branch target addresses corresponding to previously executed indirect branch instructions. The buffer is indexed with an index derived from history information corresponding to previously predicted indirect branch instructions and from the PC of the particular indirect branch instruction being predicted. In one embodiment, the buffer may be tagless and/or direct mapped. In various embodiments, the indirect branch target predictor may generate the index to the buffer using one or more techniques to improve the accuracy of the prediction: (i) offsetting the history information from the various previously predicted indirect branch instructions; (ii) weighting the history information based on the age of the previously predicted indirect branch instructions; and/or (iii) reversing the bit order of the PC of the particular indirect branch instruction being predicted.

Abstract: In one aspect, a method for managing program flow in a computer system having a processor having a prefetch mechanism and an instruction pipeline includes providing a set of program instructions having a conditional branch instruction and an system fault-causing instruction, prefetching at least one instruction into the instruction pipeline, the instruction including at least a conditional branch instruction, predicting the outcome of the conditional branch instruction; and prefetching instructions into the instruction queue based upon the result of the predicting step. The branch instruction is configured to direct program flow into or beyond the system fault instruction depending on the result of a predetermined condition.

Abstract: A method and apparatus for predicting the outcome of a branch instruction based on the branch history of preceding branch instruction. As a sequence of instructions passes through an instruction execution pipeline, a base branch instruction is chosen, a history index is generated for the base branch instruction and subsequent branch instructions, and a transform is created for the branch instruction to be predicted. When the sequence of instructions subsequently passes through the pipeline again, the transform is used to operate on the history index of the base branch instruction to produce a history index for the branch to be predicted. The result is used as an index into a prediction array to access the prediction logic for the branch instruction being predicted. By using the predetermined transform, a branch status prediction can be made before the branch to be predicted reaches the normal prediction stage in the pipeline.

Abstract: A processor supports a first processing mode in which the address size is greater than 32 bits. The address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the first processing mode. The first processing mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Other combinations of the first operating mode indication and the second operating mode indication may be used to provide compatibility modes for 32 bit and 16 bit processing compatible with the x86 processor architecture (with the enable indication remaining in the enabled state). To call code operating in the first processing mode from the 32 bit or 16 bit code, a call gate descriptor is defined which occupies two entries in a segment descriptor table.

Abstract: In a method for predicting whether a branch will be taken when a computational circuit executes a conditional branch instruction, a branch prediction field is associated with the conditional branch instruction. The branch prediction field includes at least a first state and a different second state. Upon accessing the conditional branch instruction, if the branch prediction field is in the first state the conditional branch instruction is prepared to execute as though the branch will result. If the branch prediction field is in the second state, the conditional branch instruction is prepared to execute as though the branch will not result.

Abstract: A processor, data processing system, and a related method of execution are disclosed. The processor is suitable for receiving a set of instructions and organizing the set of instructions into an instruction group. The instruction group is then dispatched for execution. Upon executing the instruction group, instruction history information indicative of an exception event associated with the instruction group is recorded. Thereafter, the execution of the instruction is modified responsive to the instruction history information to prevent the exception event from occurring during a subsequent execution of the instruction group. The processor includes a storage facility such as an instruction cache, an L2 cache or a system memory, a cracking unit, and a basic block cache. The cracking unit is configured to receive a set of instructions from the storage facility. The cracking unit is adapted to organize the set of instructions into an instruction group.

Abstract: An apparatus and method are provided for accurately predicting the outcome of branch instructions prior to their execution by a pipeline microprocessor. The apparatus includes a first table, a second table, and selection logic. The first table stores branch histories for a first set of branch instructions where the first branch instructions are categorized within the first table according to a first outcome bias. The second table stores branch histories for a second set of branch instructions, where the second branch instructions are categorized within the second table according to a second outcome bias. The selection logic is coupled to the first and second tables. When a branch instruction is executed by the microprocessor, the selection logic selects a particular branch history to predict the outcome of the branch instruction.

Abstract: Disclosed is a parallel processing apparatus capable of reducing power consumption by efficiently executing a fork instruction for activating a plurality of processors. The parallel processing apparatus has a processor element (10) for generating (forking) a thread consisting of a plurality of instructions of an external unit. The processor element comprises a fork-instruction predicting section (14) which includes a predicting section for predicting whether or not the fork condition of a fork-conditioned fork instruction is satisfied after fetching but before executing the instruction.

Abstract: A two level branch history table (TLBHT) is substantially improved by providing a mechanism to prefetch entries from the very large second level branch history table (L2 BHT) into the active (very fast) first level branch history table (L1 BHT) before the processor uses them in the branch prediction process and at the same time prefetch cache misses into the instruction cache. The mechanism prefetches entries from the very large L2 BHT into the very fast L1 BHT before the processor uses them in the branch prediction process. A TLBHT is successful because it can prefetch branch entries into the L1 BHT sufficiently ahead of the time the entry is needed. This feature of the TLBHT is also used to prefetch instructions into the cache ahead of their use. In fact, the timeliness of the prefetches produced by the TLBHT can be used to remove most of the cycle time penalty incurred by cache misses.

Abstract: One embodiment of the present invention provides a system that prefetches instructions by using an assist processor to perform prefetch operations in advance of a primary processor. The system operates by executing executable code on the primary processor, and simultaneously executing a reduced version of the executable code on the assist processor. This reduced version of the executable code executes more quickly than the executable code, and performs prefetch operations for the primary processor in advance of when the primary processor requires the instructions. The system also stores the prefetched instructions into a cache that is accessible by the primary processor so that the primary processor is able to access the prefetched instructions without having to retrieve the prefetched instructions from a main memory. In one embodiment of the present invention, prior to executing the executable code, the system compiles source code into executable code for the primary processor.

Abstract: A processor having an execution result prediction function for an instruction that performs a branch/value prediction by which a high percentage of correct predictions can be realized ought to be provided. Accordingly, in a branch/value prediction circuit having a set associative, a priority of an entry used for a prediction is increased only when an execution result is referred to for the prediction and the prediction is correct, and the execution result is registered in the entry of the lowest priority when the execution result for the instruction is newly registered in a history table. Thus, the entry of a low percentage of correct predictions becomes easy to erase and prediction accuracy can be increased by updating the priority only when the prediction is correct.

Abstract: A technique for managing register assignments. The technique involves maintaining, in a register list memory circuit having entries that respectively correspond to physical registers, a list of register assignments that assign logical registers to the physical registers. The technique further involves maintaining, in a vector memory circuit having bits that respectively correspond to the physical registers, a valid vector that forms, in combination with the list of register assignments, a list of valid register assignments. Furthermore, the technique involves storing, for an instruction that is mapped by the data processor, a copy of the valid vector from the vector memory circuit to a silo memory circuit. Preferably, the processor using the technique has the ability to execute branches of instructions speculatively, and to recover if it is determined that the processor executed down an incorrect instruction branch.

Abstract: A branch history memory stores the branch history. The branch history represents the results in the past. When processing of a branch instruction is finished, a branch history update section updates the branch history corresponding to the branch instruction, based on the processing result. A branch history table update section updates the branch history in a branch history table. The branch history stores the number of recent continuous branching successful and the number recent of continuous branching failures.

Abstract: In correspondence with an address of a branch instruction, a branch target address Apb, a valid bit V as branch history information, and delay slot information POS on the last position of delay slot instructions are stored in a branch target buffer 241. A branch prediction circuit 23 outputs hit information H/M as to whether or not an input address Ao is coincident with the branch instruction address, the valid bit which is also a branch prediction bit, the information POS, and the branch target address Apb. When a prediction error signal ERR is inactive, the address selection circuit 22 selectively outputs the output of an incrementer 21 and the branch target address Apb, based on the hit information H/M, the delay slot information POS, and the valid bit V.

Abstract: A processor having improved branch prediction accuracy includes at least one execution unit that executes sequential instructions and branch processing circuitry that processes branch instructions. The branch processing circuitry includes a number of branch prediction circuits that are each capable of providing a branch prediction for a conditional branch instruction and a selector that selects a branch prediction of a branch prediction circuit based upon the type of condition upon which the conditional branch instruction depends. The selector preferably includes hardware that determines the type of condition upon which the conditional branch instruction depends by reference to an instruction context defined by one or more instructions adjacent the conditional branch instruction in programmed sequence. The branch processing circuitry further includes path address logic that determines a path address of the selected branch prediction.

Abstract: The inventive mechanism provides fast profiling and effective trace selection. The inventive mechanism partitions the work between hardware and software. The hardware automatically detects which code is executed very frequently, e.g. which code is hot code. The hardware also maintains the branch history information. When the hardware determines that a section or block of code is hot code, the hardware sends a signal to the software. The software then forms the trace from the hot code, and uses the branch history information in making branch predictions.

Abstract: A branch prediction apparatus to minimize branch penalties in pipeline or concurrent processing of a sequence of instructions correctly predicts a pattern in which “branch taken” and “branch not taken” alternately appear. The apparatus includes a branch prediction table to keep one history bit and a 2-bit counter for each branch instruction, a prediction generator to output a value of the history bit when the counter has a value of 0 or 2 and to output a value obtained by reversing the history bit when the counter has a value of 1 or 3, and a counter controller which compares a result of branch with a value of the history bit. The counter controller sets 0 to the counter value when the result matches the value and adds one to the counter value when the result does not match the value and the counter value is other than 3.

Abstract: The data-transfer latency of a cache-miss load instruction is shortened in a processor having a cache memory. A load history table wherein a transfer address of the cache-miss load instruction is registered is provided between the processor and a memory system. When access addresses are sequential, a request for hardware prefetch to a successive address is issued and the address is registered into a prefetch buffer. Further, when a cache-miss load request to the successive address is issued, the data are transferred from the prefetch buffer directly to the processor. The system may include multiple simultaneous prefetches and a prefetch variable optimized using software.

Abstract: A mechanism for maintaining reuse invalidation information includes a reuse buffer and a reuse invalidation buffer. The reuse buffer stores multiple instances of the reuse region. Each instance stored in the reuse buffer is identified by one or more versions. The reuse invalidation buffer contains multiple entries. Each entry in the reuse invalidation buffer includes one or more pairs of pointers pointing to instances and versions of instances held in the reuse buffer.

Abstract: A branch target structure predicts a branch target address for an instruction flow. To conserve space, only a portion of the branch target address is stored. The branch target address is reconstructed assuming that an unspecified portion of a current branch instruction address matches corresponding bits of the branch target address. A comparator determines if the unspecified portion of the current branch instruction address matches corresponding bits of the branch target address. If the unspecified portion of the current branch instruction address does not match the corresponding bits of the branch target address, update of the branch target structure is inhibited. Otherwise update allowed.

Abstract: A data address prediction structure for a superscalar microprocessor is provided. The data address prediction structure predicts a data address that a group of instructions is going to access while that group of instructions is being fetched from the instruction cache. The data bytes associated with the predicted address are placed in a relatively small, fast buffer. The decode stages of instruction processing pipelines in the microprocessor access the buffer with addresses generated from the instructions, and if the associated data bytes are found in the buffer they are conveyed to the reservation station associated with the requesting decode stage. Therefore, the implicit memory read associated with an instruction is performed prior to the instruction arriving in a functional unit. The functional unit is occupied by the instruction for a fewer number of clock cycles, since it need not perform the implicit memory operation.

Abstract: Enables a processor to quickly recover reliable use of a multi-cycle index used in a branch prediction mechanism for certain types of flush events occurring in the processor pipeline, whether the flush event occurs for a non-branch instruction or for a branch instruction contained in the same dispatch group. A GHV (global history vector) value is used in the generation of a multi-cycle index required for locating a prediction in a GBHT (global branch history table) for the instruction associated with the GHV value. The GHV value is captured in a BIQ (branch information queue) element representing each branch instruction selected for execution of a program. The BIQ element also captures an associated GHV count when the GHV value is captured.

Abstract: There is disclosed an apparatus for loading instructions into the instruction execution pipeline of a pipelined processor. The apparatus for loading instructions comprises: 1) an instruction loading circuit that loads instructions from a first instruction thread into the instruction execution pipeline; and 2) a branch instruction detection circuit that detects a branch instruction in the first instruction thread. In response to the branch instruction detection, the instruction loading circuit stops loading instructions from the first instruction thread into the instruction execution pipeline and begins loading instructions from a second instruction thread into the instruction execution pipeline.

Abstract: A method and apparatus for generating an optimized intermediate representation of source code for a computer program are described. An initial intermediate representation is extracted from the source code by organizing it as a plurality of basic blocks that each contain at least one program instruction ordered according to respective estimated profit values. A goal function that measures the degree of optimization of the program is calculated in accordance with its intermediate representation. The effect on the goal function of modifying the intermediate representation by moving an instruction from one of the basic blocks to each of its predecessors is tested iteratively and adopting the modified intermediate representation if it causes a reduction in the goal function.

Abstract: A Next Return Target Address stack to maintain return addresses for call and return operations. The invention accommodates both definite return addresses and speculative return address in a single stack. Return addresses are written into the stack and read out of the stack at an entry/exit register interior to the stack. The stack has a lower portion below the entry/exit register for maintaining both actual and speculative return addresses, and an upper portion above the entry/exit register for maintaining return addresses that have been speculatively popped out. A branch history register keeps an ongoing record of the most recent calls and returns. In the event of a pipeline flush, such as would be caused by a branch mispredict, the contents of the branch history register are examined to determine how to adjust the contents of the stack. One or more depth counters keep track of which contents in the branch history register are to be examined.

Abstract: The problem is to branch back to an appropriate location within a memory tester test program, and also restore its state of algorithmic control, when an error associated therewith occurs later in time at the DUT. Owing to delays in pipelines connecting the program execution environment to the DUT and back again. These delays allow the program to arbitrarily advance beyond where the stimulus was given. The arbitrary advance makes it difficult to determine the exact circumstances that were associated with the error. A branch based on the error signal can restart a section of the test program, but it is likely only a template needing further test algorithm control information that varies dynamically as the test program executes. The solution is to equip the memory tester with History FIFO's whose depths are adjusted to account for the sum of the delays of the pipelines, relative to the location of that History FIFO.

Abstract: A pipeline process system, a super-scalar process system, or an out-of-order-execution process system is applied to an information processing device. A sequence of instructions containing a branch instruction, especially a subroutine, can be processed at a high speed using a branch history and a return address stack storing a return address corresponding to a subroutine call instruction. To successfully perform the process, when an instruction detected as a bit in the branch history is a subroutine return instruction, an address of a branched-to instruction registered in the branch history is compared with all return addresses stored in valid entries in the return address stack. A unit is provided to transmit a matching address as a return address of the return instruction to an instruction fetch unit for fetching an instruction.

Abstract: A mechanism is described that prefetches instructions and data into the cache using a branch instruction as a prefetch trigger. The prefetch is initiated if the predicted execution path after the branch instruction matches the previously seen execution path. This match of the execution paths is determined using a branch history queue that records the branch outcomes (taken/not taken) of the branches in the program. For each branch in this queue, a branch history mask records the outcomes of the next N branches and serves as an encoding of the execution path following the branch instruction. The branch instruction along with the mask is associated with a prefetch address (instruction or data address) and is used for triggering prefetches in the future when the branch is executed again. A mechanism is also described to improve the timeliness of a prefetch by suitably adjusting the value of N after observing the usefulness of the prefetched instructions or data.

Abstract: A method and apparatus for scheduling jump and store operations using a dependency matrix and for scheduling operations in-order using a dependency matrix. A child operation, such as a jump or store micro-operation, is received for scheduling. The child operation is dependent on the completion of a parent operation, such as when all jump operations in an instruction stream must be executed in-order. An entry corresponding to the child operation is placed in a scheduling queue and the child operation is compared with other entries in the scheduling queue. The result of this comparison is stored in a dependency matrix. Each row in the dependency matrix corresponds to an entry in the scheduling queue, and each column corresponds to a dependency on an entry in the scheduling queue. Entries in the scheduling queue can then be scheduled based on the information in the dependency matrix, such as when the entire row associated with an entry is clear.

Abstract: A branch predictor. A first branch prediction table is coupled to an instruction pointer generator to store tagged branch prediction entries and to provide branch predictions at high speed. A second branch prediction table is also coupled to the instruction pointer generator to store untagged branch prediction entries and to provide branch predictions for a much larger working set of branches, albeit at a slower speed.

Abstract: An apparatus and method are provided for accurately predicting the outcome of branch instructions prior to their execution by a pipeline microprocessor. The apparatus includes a bias indicator and a dynamic branch predictor. The bias indicator receives a branch instruction from an instruction buffer and provides an output indicating a particular outcome bias category for the branch instruction. The bias indicator provides the output as a function of a branch type and a displacement, where the branch type and the displacement are prescribed by the branch instruction The dynamic branch predictor is coupled to the bias indicator.