Exeception Processing (e.g., Interrupts And Traps) Patents (Class 712/244)
  • Patent number: 8813077
    Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: August 19, 2014
    Assignee: Intel Corporation
    Inventors: Steven Bennett, Andrew Anderson, Gilbert Neiger, Scott Rodgers, Richard Uhlig, Lawrence Smith, III, Barry Huntley
  • Patent number: 8806104
    Abstract: In one embodiment, a processor includes an access logic to determine whether an access request from a virtual machine is to a device access page associated with a device of the processor and if so, to re-map the access request to a virtual device page in a system memory associated with the VM, based at least in part on information stored in a control register of the processor. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: August 12, 2014
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Stephan J. Robinson
  • Publication number: 20140223151
    Abstract: A method for executing kernels in a hybrid system includes running a program on a host computer and identifying in an instruction stream of the program a first instruction including a function of a target classification. The method includes generating a first kernel including the function and transmitting the first kernel to a client system to execute the first kernel based on identifying the first instruction as being of the target classification. The method also includes determining whether to store results of executing the first kernel in a read-only buffer of the client system based on determining whether a subsequent instruction of the target classification relies upon results of the first instruction.
    Type: Application
    Filed: February 4, 2013
    Publication date: August 7, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: D. Gary Chapman, Rajaram B. Krishnamurthy, Deborah A. Odell, Benjamin P. Segal
  • Patent number: 8799929
    Abstract: A system, apparatus, and method for allocation mode switching on an event-driven basis are described herein. The allocation mode switching method includes detecting an event, selecting a bandwidth allocation mode associated with the detected event, and allocating a plurality of execution cycles of an instruction execution period of a processor core among a plurality of instruction execution threads based at least in part on the selected bandwidth allocation mode. Other embodiments may be described and claimed.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: August 5, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Jack Kang, Yu-Chi Chuang
  • Publication number: 20140215194
    Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.
    Type: Application
    Filed: April 1, 2014
    Publication date: July 31, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Hidemi OYAMA, Masanobu KAWAMURA, Takuya IKEGUCHI, Masanori MATSUMOTO, Hiroyuki KAWAJIRI
  • Patent number: 8793689
    Abstract: A redundant multithreading processor is presented. In one embodiment, the processor performs execution of a thread and its duplicate thread in parallel and determines, when in a redundant multithreading mode, whether or not to synchronize an operation of the thread and an operation of the duplicate thread.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: July 29, 2014
    Assignee: Intel Corporation
    Inventors: Glenn J. Hinton, Steven E. Raasch, Avinash Sodani, Sebastien Hily, John G. Holm, Ronak Singhal, Deborah T. Marr
  • Publication number: 20140208087
    Abstract: A microprocessor architecture having extendible logic. One or more customized applications are available to the instruction pipeline. The customizable applications may include software, extension logic instruction or register, dynamically configurable hardware logic, or combinations of these. In order to enable the operating system to interface with the customized extension applications, at least one software extension is provided to the operating system. When a specific extension is requested a software exception is generated by the OS. In response to the exception, the least one software extension is called to handle context switch and dynamic configuration of the extendible logic of the microprocessor.
    Type: Application
    Filed: March 21, 2014
    Publication date: July 24, 2014
    Applicant: SYNOPSYS, INC.
    Inventors: James Robert-Howard Hakewill, Richard A. Fuhler
  • Publication number: 20140208086
    Abstract: Vector exception handling is facilitated. A vector instruction is executed that operates on one or more elements of a vector register. When an exception is encountered during execution of the instruction, a vector exception code is provided that indicates a position within the vector register that caused the exception. The vector exception code also includes a reason for the exception.
    Type: Application
    Filed: January 23, 2013
    Publication date: July 24, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel
  • Publication number: 20140189333
    Abstract: A processor comprising: execution logic to execute a first thread including an accelerator invocation instruction to invoke an accelerator command; an accelerator to execute an accelerator thread in response to the accelerator command, the accelerator to store state data associated with the accelerator thread in a application memory area in memory, wherein prior to executing the accelerator thread, the accelerator is to lock entries in a translation lookaside buffer (TLB) associated with the accelerator thread to prevent an exception which might otherwise result.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Oren Ben-Kiki, Ilan Pardo, Eliezer Weissmann
  • Publication number: 20140189332
    Abstract: An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why the command could not be executed; execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands; and one or more accelerators to read the command data from the command register and responsively attempt to execute the command identified by the command data.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Oren Ben-Kiki, Ilan Pardo, Robert Valentine, Eliezer Weissmann, Dror Markovich, Yuval Yosef
  • Patent number: 8769250
    Abstract: In general, the invention relates to a method. The method includes receiving notification, which includes context information, of a trap. The method further includes accessing, based at least partially upon the context information, a particular instruction that caused the trap, determining, based at least partially upon the context information, a particular address that is to be accessed by the particular instruction, updating a set of log information to indicate accessing of the particular address, causing subsequent accesses of the particular address to not give rise to a trap, after causing subsequent accesses of the particular address to not give rise to a trap, accessing the particular address, after accessing the particular address, causing subsequent accesses of the particular address to give rise to a trap, and causing the particular instruction to not be executed.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: July 1, 2014
    Assignee: Oracle America, Inc.
    Inventors: Nedim Fresko, Dean R. Long, Jiangli Zhou
  • Patent number: 8762694
    Abstract: Method, apparatus, and system for a programmable event-driven yield mechanism. The mechanism may disrupt processing of a program to deliver a yield event. The event may be treated as a fault-like yield event or a trap-like event. For a fault-like yield event, the faulting instruction is canceled before retirement and processor state is not updated before the yield event is delivered. For a trap-like yield event the instruction causing the trap is retired and the yield event is delivered on an interrupt boundary. Multiple pending yield events may be handled according to priority. Other embodiments are also described and claimed.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: June 24, 2014
    Assignee: Intel Corporation
    Inventors: Xiang Zou, Hong Wang, Robert Knight, Robert Geva, Gautham Chinya, Scott Dion Rodgers, Chris Newburn, Bryant E. Bigbee, Per Hammarlund, Ittai Anati, Jim B. Crossland, John P. Shen
  • Patent number: 8752064
    Abstract: Provided herein is a method for optimizing communication for system calls. The method includes storing a system call for each work item in a wavefront and transmitting said stored system calls to a processor for execution. The method also includes receiving a result to each work item in the wavefront responsive to said transmitting.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: June 10, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Benjamin Thomas Sander, Michael Houston, Newton Cheung, Keith Lowery
  • Publication number: 20140156972
    Abstract: In an embodiment, the present invention includes a processor having an execution logic to execute instructions and a control transfer termination (CTT) logic coupled to the execution logic. This logic is to cause a CTT fault to be raised if a target instruction of a control transfer instruction is not a CTT instruction. Other embodiments are described and claimed.
    Type: Application
    Filed: November 30, 2012
    Publication date: June 5, 2014
    Inventors: Vedyvas Shanbhogue, Jason W. Brandt, Uday R. Savagaonkar, Ravi L. Sahita
  • Publication number: 20140122848
    Abstract: Systems and methods for instruction entity allocation and scheduling on multi-processors is provided. In at least one embodiment, a method for generating an execution schedule for a plurality of instruction entities for execution on a plurality of processing units comprises arranging the plurality of instruction entities into a sorted order and allocating instruction entities in the plurality of instruction entities to individual processing units in the plurality of processing units. The method further comprises scheduling instances of the instruction entities in scheduled time windows in the execution schedule, wherein the instances of the instruction entities are scheduled in scheduled time windows according to the sorted order of the plurality of instruction entities and organizing the execution schedule into execution groups.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 1, 2014
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Arvind Easwaran, Srivatsan Varadarajan
  • Publication number: 20140122849
    Abstract: Processing circuitry 4 has a plurality of exception states EL0-EL3 for handling exception events, the exception states including a base level exception state EL0 and at least one further level exception state EL1-EL3. Each exception state has a corresponding stack pointer indicating the location within the memory of a corresponding stack data store 35. When the processing circuitry is in the base level exception state EL0, stack pointer selection circuitry 40 selects the base level stack pointer as a current stack pointer indicating a current stack data store for use by the processing circuitry 4. When the processing circuitry 4 is a further exception state, the stack pointer selection circuitry 40 selects either the base level stack pointer or the further level stack pointer corresponding to the current further level exception state as a current stack pointer.
    Type: Application
    Filed: January 7, 2014
    Publication date: May 1, 2014
    Applicant: ARM LIMITED
    Inventor: Richard Roy GRISENTHWAITE
  • Patent number: 8713294
    Abstract: A method and system for providing a memory access check on a processor including the steps of detecting accesses to a memory device including level-1 cache using a wakeup unit. The method includes invalidating level-1 cache ranges corresponding to a guard page, and configuring a plurality of wakeup address compare (WAC) registers to allow access to selected WAC registers. The method selects one of the plurality of WAC registers, and sets up a WAC register related to the guard page. The method configures the wakeup unit to interrupt on access of the selected WAC register. The method detects access of the memory device using the wakeup unit when a guard page is violated. The method generates an interrupt to the core using the wakeup unit, and determines the source of the interrupt. The method detects the activated WAC registers assigned to the violated guard page, and initiates a response.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas M. Gooding, David L. Satterfield, Burkhard Steinmacher-Burow
  • Publication number: 20140101642
    Abstract: An approach is provided in which a set of common instructions are each executed by at least two processor cores. Each of the processor cores queues values resulting from at least one of the common instructions (a critical section). The queued values are compared by a queued comparator. An exception is issued in response to the comparison revealing unequal values having been queued by the processor cores.
    Type: Application
    Filed: October 10, 2012
    Publication date: April 10, 2014
    Inventors: Gary R. Morrison, Brian C. Kahne, Anthony M. Reipold
  • Publication number: 20140095851
    Abstract: A mechanism is provided for completing of set of instructions while receiving interrupts. The mechanism executes a set of instructions. Responsive to receiving an interrupt and determining that the interrupt requires processing within an implementation time frame, the mechanism delays the interrupt for a predetermined time period. Responsive to completing the set of instructions within the predetermined time period, the mechanism processes the interrupt.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: International Business Machines Corporation
    Inventors: Guenter Gerwig, Christian Jacobi, Frank Lehnert
  • Patent number: 8688964
    Abstract: A digital processor with programmable exception processing latency, may have a central processing unit (CPU) of a digital processor, an exception controller coupled with the CPU, and a control register coupled with the CPU, wherein the control register is operable to set the operation mode of the CPU in at least one of two modes, wherein in the first mode the CPU has a fixed exception processing latency time, and in a second mode the CPU has a variable exception processing latency time.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: April 1, 2014
    Assignee: Microchip Technology Incorporated
    Inventors: Michael I. Catherwood, David Mickey
  • Patent number: 8689215
    Abstract: Methods, data structures, instructions, and techniques for structured exception handling for user-level threads in a multi-threading system are provided. Registered filter routines may be dispatched to a thread unit not managed by the operating system (OS). The dispatch may occur by allowing an OS-managed thread unit (proxy) to invoke the OS-provided structured exception handling service (including dispatcher) on behalf of the sequestered thread unit. Alternatively, an OS-managed thread unit may include dispatch code and may, without OS intervention, dispatch the filter routine to the sequestered thread unit. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: April 1, 2014
    Assignee: Intel Corporation
    Inventors: Richard A. Hankins, Gautham N. Chinya, Hong Wang, David K. Poulsen, Shirish Aundhe, Baiju V. Patel, Sanjiv M. Shah
  • Patent number: 8677107
    Abstract: Processing circuitry 4 has a plurality of exception states EL0-EL3 for handling exception events, the exception states including a base level exception state EL0 and at least one further level exception state EL1-EL3. Each exception state has a corresponding stack pointer indicating the location within the memory of a corresponding stack data store 35. When the processing circuitry is in the base level exception state EL0, stack pointer selection circuitry 40 selects the base level stack pointer as a current stack pointer indicating a current stack data store for use by the processing circuitry 4. When the processing circuitry 4 is a further exception state, the stack pointer selection circuitry 40 selects either the base level stack pointer or the further level stack pointer corresponding to the current further level exception state as a current stack pointer.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: March 18, 2014
    Assignee: ARM Limited
    Inventor: Richard Roy Grisenthwaite
  • Publication number: 20140068289
    Abstract: A technique for operating a processor includes detecting an interrupt having a first core of the processor as a destination core. The technique includes handling the interrupt by a second core of the processor in response to the first core being in a low-power state. The first core may be capable of executing a greater number of instructions-per-cycle than the second core and the second core may consume less power than the first core. The first core may be coupled to a first voltage plane and the second core may be coupled to a second voltage plane having lower power than the first voltage plane.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 6, 2014
    Inventor: Noah B. Beck
  • Publication number: 20140068573
    Abstract: A condition detected by a virtual routine may be treated by setting an error code or raising an exception, depending on circumstances. Enhanced vtable layouts promote availability of both error-ID-based and exception-based virtual routines, while maintaining compatibility. Compilers treat virtual routines based on their circumstances. One enhanced vtable includes error-ID-based routine pointers in a COM-layout-compatible portion and exception-based routine pointers in an extension. For a virtual routine not overridden by a derived class, a compiler generates a direct call. For an object instance of a specific type, the compiler generates a direct exception-based call for the object's routine. For a factory-sourced object's routine, the compiler generates a virtual exception-based call. When the virtual routine belongs to a component having an enhanced vtable, the compiler may generate a virtual call using the exception-based routine pointer. Code wrappers between COM and native format may also be used.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 6, 2014
    Applicant: MICROSOFT CORPORATION
    Inventors: Deon Brewis, James Springfield, Sridhar S. Madhugiri
  • Publication number: 20140059334
    Abstract: A processor performance profiler is enabled to for identify specific instructions causing performance issues within a program being executed by a microprocessor through random sampling to find the worst-case offenders of a particular event type such as a cache miss or a branch mis-prediction. Tracking all instructions causing a particular event generates large data logs, creates performance penalties, and makes code analysis more difficult. However, by identifying and tracking the worst offenders within a random sample of events without having to hash all events results in smaller memory requirements for the performance profiler, lower performance impact while profiling, and decreased complexity to analyze the program to identify major performance issues, which, in turn, enables better optimization of the program in shorter developer time.
    Type: Application
    Filed: October 30, 2013
    Publication date: February 27, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Venkat Rajeev Indukuru, Daniel Owen, Alexander Erik Mericas, John Fred Spannaus
  • Publication number: 20140059333
    Abstract: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software.
    Type: Application
    Filed: February 2, 2012
    Publication date: February 27, 2014
    Inventors: Martin G. Dixon, Ravi Rajwar, Konrad K. Lai, Robert S. Chappell, Rajesh S. Parthasarathy, Alexandre J. Farcy, Ilhyun Kim, Prakash Math, Matthew Merten, Vijaykumar Kadgi
  • Patent number: 8661232
    Abstract: In a data processing apparatus 1 having registers 6, when a state saving trigger event occurs while a result value of a data processing operation is still to be written to a destination register then saving and restoring control circuitry 12 selects a state saving sequence defining a temporal order for saving register values to a backup data store 10. The sequence is selected to provide the destination register with a position within the sequence corresponding to a time after the result value has been written to the destination register. The register values are then saved to the backup data store 10 in the order of the selected state saving sequence. A similar technique can be used when a state restoring trigger event triggers loading of the data values from the backup data store 10 to the registers 6.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: February 25, 2014
    Assignee: ARM Limited
    Inventors: Antony John Penton, Simon Axford
  • Patent number: 8656145
    Abstract: A multithreaded processor capable of allocating interrupts is described. In one embodiment, the multithreaded processor includes an interrupt module and threads for executing tasks. The interrupt module can identify a priority for each thread based on a task priority for tasks being executed by the threads and assign an interrupt to a thread based at least on its priority.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: February 18, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Erich James Plondke, Lucian Codrescu
  • Publication number: 20140013090
    Abstract: A method for flattening conditional statements, the method comprises: obtaining a program code, the program code comprising a conditional control flow program construct, which conditional control flow program construct when read by a target processor, causes the target processor to select a control flow path for execution between at least a first and a second control flow paths, wherein said selection is based on an evaluation of a condition of the conditional control flow program construct; replacing the conditional control flow program construct with a transaction-based control flow program construct, which when read by the target processor is operative to cause the target processor to commence a transaction, the transaction configured to execute the first control flow path; and wherein the transaction-based control flow program construct is operative to cause the target processor to execute the conditional control flow program construct in case the transaction is rolled back.
    Type: Application
    Filed: July 8, 2012
    Publication date: January 9, 2014
    Applicant: International Business Machines Corporation
    Inventor: Marcel Zalmanovici
  • Publication number: 20140013091
    Abstract: Some implementations provide techniques and arrangements for causing an interrupt in a processor in response to an occurrence of a number of events. A first event counter counts the occurrences of a type of event within the processor and outputs a signal to activate a second event counter in response to reaching a first predefined count. The second event counter counts the occurrences of the type of event within the processor and causes an interrupt of the processor in response to reaching a second predefined count.
    Type: Application
    Filed: December 29, 2011
    Publication date: January 9, 2014
    Inventors: Ahmad Yasin, Peggy J. Irelan, Ofer Levy, Emile Ziedan, Grant Zhou
  • Publication number: 20130346732
    Abstract: A processor core interrupt control circuit issues a request signal for requesting cancellation of a coprocessor instruction being executed at a coprocessor. A program control circuit issues interrupt processing after issuance of the cancellation request. A coprocessor computation control circuit retains the execution state of the coprocessor instruction. Upon receiving the processing cancellation request signal, a coprocessor interrupt control circuit performs cancellation or holding of the coprocessor instruction on the basis of execution state information retained by the coprocessor computation control circuit. The coprocessor interrupt control circuit evicts the execution state of the coprocessor instruction in the case of holding, and restores the execution state of the coprocessor instruction that had been evicted after completion of the interrupt processing.
    Type: Application
    Filed: October 26, 2011
    Publication date: December 26, 2013
    Applicant: NEC CORPORATION
    Inventor: Hiroyuki Igura
  • Patent number: 8615226
    Abstract: There are provided: a data communication system, a relay apparatus, and a portable terminal apparatus in which when a mobile portable terminal apparatus such as a mobile telephone displays a screen based on display screen definition data received from a central apparatus, the exception handling of the data communication can be dynamically changed according to the communication environment of the portable terminal apparatus. The central apparatus adds, to the display screen definition data, communication control data where an exception handling procedure for communication between the portable terminal apparatus and the central apparatus is set. The portable terminal apparatus displays an image based on the display screen definition data received from the central apparatus, and performs data communication with the central apparatus according to the communication control data extracted from the display screen definition data.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: December 24, 2013
    Assignee: Fujitsu Limited
    Inventors: Kazuki Matsui, Hideto Kihara, Soichi Nishiyama, Yasuhiko Awamoto, Hiroshi Kokubo, Chizu Tuge, Yoshiyuki Ito, Norie Tachibana
  • Publication number: 20130339701
    Abstract: Embodiments relate to cross-pipe serialization for a multi-pipeline computer processor. An aspect includes receiving, by a processor, the processor comprising a first pipeline, the first pipeline comprising a serialization pipeline, and a second pipeline, the second pipeline comprising a non-serialization pipeline, a request comprising a first subrequest for the first pipeline and a second subrequest for the second pipeline. Another aspect includes completing the first subrequest by the first pipeline. Another aspect includes, based on completing the first subrequest by the first pipeline, sending cross-pipe unlock signal from the first pipeline to the second pipeline. Yet another aspect includes, based on receiving the cross-pipe unlock signal by the second pipeline, completing the second subrequest by the second pipeline.
    Type: Application
    Filed: June 13, 2012
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Deanna Postles Dunn Berger, Michael F. Fee, Edward J. Kaminski,, JR., Diane L. Orf
  • Publication number: 20130339709
    Abstract: A TRANSACTION ABORT instruction is used to abort a transaction that is executing in a computing environment. The TRANSACTION ABORT instruction includes at least one field used to specify a user-defined abort code that indicates the specific reason for aborting the transaction. Based on executing the TRANSACTION ABORT instruction, a condition code is provided that indicates whether re-execution of the transaction is recommended.
    Type: Application
    Filed: March 8, 2013
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: INTERNATIONAL BUSINESS MACHINES CORPORATION
  • Publication number: 20130339706
    Abstract: An operation is provided to signal a processor that action is to be taken to facilitate execution of a transaction that has aborted one or more times. The operation is specified within an instruction or is itself an instruction. The instruction is executed based on detecting an abort of the transactions, and includes a field indicating how many times the transaction has aborted. The processor uses this information to determine what action is to be taken.
    Type: Application
    Filed: March 7, 2013
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Randall W. Philley, Peter J. Relson, Timothy J. Slegel
  • Publication number: 20130339702
    Abstract: Program exception conditions cause a transaction to abort and typically result in an interruption in which the operating system obtains control. A program interruption filtering control is provided to selectively present the interrupt. That is, the interrupt from the program exception condition may or may not be presented depending at least on the program interruption filtering control and a transaction class associated with the program exception condition. The program interruption filtering control is provided by a TRANSACTION BEGIN instruction.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Marcel Mitran, Timothy J. Slegel
  • Publication number: 20130339703
    Abstract: Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.
    Type: Application
    Filed: March 3, 2013
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: INTERNATIONAL BUSINESS MACHINES CORPORATION
  • Publication number: 20130339704
    Abstract: A TRANSACTION BEGIN instruction begins execution of a transaction and includes a general register save mask having bits, that when set, indicate registers to be saved in the event the transaction is aborted. At the beginning of the transaction, contents of the registers are saved in memory not accessible to the program, and if the transaction is aborted, the saved contents are copied to the registers.
    Type: Application
    Filed: March 3, 2013
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: INTERNATIONAL BUSINESS MACHINES CORPORATION
  • Publication number: 20130339708
    Abstract: Program exception conditions cause a transaction to abort and typically result in an interruption in which the operating system obtains control. A program interruption filtering control is provided to selectively present the interrupt. That is, the interrupt from the program exception condition may or may not be presented depending at least on the program interruption filtering control and a transaction class associated with the program exception condition. The program interruption filtering control is provided by a TRANSACTION BEGIN instruction.
    Type: Application
    Filed: March 8, 2013
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: INTERNATIONAL BUSINESS MACHINES CORPORATION
  • Publication number: 20130339705
    Abstract: Task specific diagnostic controls are provided to facilitate the debugging of certain types of abort conditions. The diagnostic controls may be set to cause transactions to be selectively aborted, allowing a transaction to drive its abort handler routine for testing purposes. The controls include, for instance, a transaction diagnostic scope and a transaction diagnostic control. The transaction diagnostic scope indicates when the transaction diagnostic control is to be applied, and the transaction diagnostic control indicates whether transactions are to selectively aborted.
    Type: Application
    Filed: March 3, 2013
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: INTERNATIONAL BUSINESS MACHINES CORPORATION
  • Publication number: 20130339707
    Abstract: Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether certain types of instructions are permitted to execute within the transaction. The controls include one or more of an allow access register modification control and an allow floating point operation control.
    Type: Application
    Filed: March 7, 2013
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Robert R. Rogers, Timothy J. Slegel
  • Publication number: 20130339710
    Abstract: Improving the performance of multitasking processors are provided. For example, a subset of M processors within a Symmetric Multi-Processing System (SMP) with N processors is dedicated for a specific task. The M (M>0) of the N processors are dedicate to a task, thus, leaving (N-M) processors for running normal operating system (OS). The processors dedicated to the task may have their interrupt mechanism disabled to avoid interrupt handler switching overhead. Therefore, these processors run in an independent context and can communicate with the normal OS and cooperation with the normal OS to achieve higher network performance.
    Type: Application
    Filed: August 16, 2013
    Publication date: December 19, 2013
    Applicant: Fortinet, Inc.
    Inventor: Jianzu Ding
  • Publication number: 20130332717
    Abstract: A multi-thread processor includes a plurality of hardware threads each of which generates an independent instruction flow, a first thread scheduler that continuously outputs a thread selection signal uniformly in a first period of a cycle of the first schedule pattern in accordance with a first schedule pattern or continuously outputs the thread selection signal uniformly in a second period of a cycle of the second schedule pattern in accordance with a second schedule pattern, the thread selection signal designating a hardware thread to be executed in a next execution cycle from among the plurality of hardware threads, a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread from among the plurality of hardware threads, and an execution pipeline that executes an instruction output from the first selector.
    Type: Application
    Filed: August 12, 2013
    Publication date: December 12, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Koji Adachi, Toshiyuki Matsunaga
  • Patent number: 8607035
    Abstract: This invention relates to multi-core, multi-processing, factory multi-core and DSP multi-core. The nature of the invention is related to more optimal uses of a multi-core system to maximize utilization of the processor cores and minimize power use. The novel and inventive steps are focused on use of interrupts and prioritized interrupts, along with optional in-built methods, to allow systems to run more efficiently and with less effort on the part of the programmer.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: December 10, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Paul Kimelman
  • Patent number: 8601177
    Abstract: A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using the ranges of addresses. Different ranges of addresses in the memory may be redistributed among a second set of functions in a second pipeline without waiting for the first set of functions to be flushed of data.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: December 3, 2013
    Assignee: Intel Corporation
    Inventor: Thomas A. Piazza
  • Patent number: 8601443
    Abstract: A computer program product comprises a computer useable medium. The computer useable medium has a computer readable program such that when the computer readable medium is executed on a computer, the computer is caused to configure a calling interceptor at a service invocation point corresponding to a first component service of a software application to monitor a service invocation made by the first component service of a second component service of the software application, record a first set of correlation data represented by a first correlation indicator into a trace file, record a unique identifier into the trace file, and send the unique identifier to the second component service thought the service invocation.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: December 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kevin Spencer Barker, Christopher Shane Claussen, Stefan Georg Derdak, Xiaochun Mei
  • Publication number: 20130318333
    Abstract: A client processor can save an execution state of a process that runs on two or more secondary processors in a single file. The single file can be transferred from the client processor over a network to a host processor. The single file is configured to permit the host processor to resume processing of the suspended process. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Application
    Filed: November 16, 2012
    Publication date: November 28, 2013
    Inventor: Tatsuya Iwamoto
  • Publication number: 20130318334
    Abstract: Methods, apparatus, and systems for facilitating effective power management through dynamic reconfiguration of interrupts. Interrupt vectors are mapped to various processor cores in a multi-core processor, and interrupt workloads on the processor cores are monitored. When an interrupt workload for a given processor core is detected to fall below a threshold, the interrupt vectors are dynamically reconfigured by remapping interrupt vectors that are currently mapped to the processor core to at least one other processor core, such that there are no interrupt vectors mapped to the processor core after reconfiguration. The core is then enabled to be put in a deeper idle state. Similar operations can be applied to additional processor cores, effecting a collapsing of interrupt vectors onto fewer processor cores.
    Type: Application
    Filed: April 24, 2012
    Publication date: November 28, 2013
    Inventor: Peter P. Waskiewicz, JR.
  • Publication number: 20130305024
    Abstract: A method and system uses exceptions for code specialization in a system that supports transactions. The method and system includes inserting one or more branchless instructions into a sequence of computer instructions. The branchless instructions include one or more instructions that are executable if a commonly occurring condition is satisfied and include one or more instructions that are configured to raise an exception if the commonly occurring condition is not satisfied.
    Type: Application
    Filed: December 16, 2011
    Publication date: November 14, 2013
    Inventors: Arvind Krishnaswamy, Daniel M Lavery
  • Publication number: 20130290689
    Abstract: The output of a non-deterministic instruction is handled during record and replay in a virtual machine. An output of a non-deterministic instruction is stored to a buffer during record mode and retrieved from a buffer during replay mode without exiting to the hypervisor. At least part of the contents of the buffer can be stored to a log when the buffer is full during record mode, and the buffer can be replenished from a log when the buffer is empty during replay mode.
    Type: Application
    Filed: June 25, 2013
    Publication date: October 31, 2013
    Inventors: Vyacheslav V. MALYUGIN, Min XU, Boris WEISSMAN, Ganesh VENKITACHALAM, Alexander KLAIBER