Abstract: Apparatus and a method for causing scheduler software to produce code which executes more rapidly by ignoring some of the normal constraints placed on its scheduling operations and simply scheduling certain instructions to run as fast as possible, raising an exception if the scheduling violates a scheduling constraint, and determining steps to be taken for correctly executing each set of instructions about which an exception is raised.

Abstract: Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a first instruction execution thread and (ii) a second instruction thread for execution by an execution block of the multi-thread processing environment; providing a first interrupt signal via a first interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the first instruction execution thread; and providing a second interrupt signal via a second interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the second instruction execution thread. The first interrupt signal line and the second interrupt signal line are physically separate and distinct signal lines that are directly electrically coupled to one another.

Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.

Abstract: User script code that has been developed for execution in a host application can be remapped to debuggable script code, based on explicit debugging gestures, allowing for appropriate debugging coverage for the code while mitigating execution (in)efficiency issues. Capabilities of an application virtual machine used for the host application can be determined, and the user script code can be instrumented with guards for detecting explicit debugging gestures based on a virtual machine's (VM') capabilities. The instrumented user script code can be executed in a runtime environment, for example, by a just-in-time compilation service. If an explicit debugging gesture is detected, a function where the gesture was detected can be transformed into debuggable script code, in one embodiment, based on the debuggable gesture detected.

Abstract: A method for a computer including a processor that is capable of counting invalidation of translation lookaside buffers and generating an interrupt at the occurrence of the invalidation, the invalidation being performed by an operating system upon switching between application programs, includes acquiring identification information of application programs from the operating system and storing the identification information as a first list; detecting an interrupt generated from the processor at the occurrence of switching from a first application program to a second application program; and when the interrupt is detected, acquiring the identification information of the first and second application programs from the operating system or the mechanism and comparing the acquired identification information with the first list to determine whether either of the first and second application programs is a program that has been created or disappeared.

Abstract: Various technologies and techniques are disclosed for providing concurrent exception handling. When one or more exceptions are received from concurrent workers, one or more exception handler functions are supplied. For each respective exception in the exception results, determine if the respective exception is one of a kind of exceptions handled by the one or more exception handler functions. If the respective exception is one of a kind handled by the exception handler functions, then run a particular handler of the exception handler functions and mark the respective exception as handled. Any unhandled exceptions are then processed appropriately. In one implementation, a collection of input data is processed to produce a collection of output results, with the exceptions being interleaved with other output results. In another implementation, a particular exception is selected that represents the multiple exceptions. The selected one particular exception is then thrown.

Abstract: A signature module calculates a signature during the execution of a program by a central processing unit based on program instructions to the central processing unit, and stores the signature in a signature register of the signature module. The signature module includes: a calculation unit configured to generate a signature value based on program instructions executed on the central processing unit; and an instruction information interface configured to receive at least one item of instruction information from the central processing unit which indicates whether an instruction currently being executed by the central processing unit was jumped to indirectly or directly.

Abstract: A first section of executable computer code of a computer program is dynamically patched by performing the following. A breakpoint is inserted at the first section of executable computer code. During execution of the computer program, an instruction counter is incremented on an instruction-by-instruction basis through the computer program. The instruction counter indicates a current instruction of the computer program being executed. The breakpoint where the instruction counter points to the first section of executable computer code is encountered, which results in a breakpoint handler being called. The breakpoint handler changes the instruction pointer to instead point to a second section of executable computer code. The second section of executable computer code is a patched version of the first section of executable computer code. Upon the breakpoint handler returning, the second section of executable computer code is executed in lieu of the first section of executable computer code.

Abstract: An information handling system includes a processor that may perform general purpose register recovery operations after an instruction flush operation that an exception, such as a branch misprediction causes. The processor receives an instruction stream that may include multiple instructions that operate on a particular target register that stores instruction result information. The general purpose register may temporarily store instruction opcode and register bits information for use during dispatch, execution and other operations. The processor includes a recovery buffer unit for use during flush recovery operations. The processor may use recovery valid and recovery pending bits that correspond with each instruction during the register recovery from flush operation.

Abstract: A microprocessor architecture for executing byte compiled Java programs directly in hardware. The microprocessor targets the lower end of the embedded systems domain and features two orthogonal programming models, a Java model and a RISC model. The entities share a common data path and operate independently, although not in parallel. The microprocessor includes a combined register file in which the Java module sees the elements in the register file as a circular operand stack and the RISC module sees the elements as a conventional register file. The integrated microprocessor architecture facilitates access to hardware-near instructions and provides powerful interrupt and instruction trapping capabilities.

Abstract: General-purpose distributed data-parallel computing using high-level computing languages is described. Data parallel portions of a sequential program written in a high-level language are automatically translated into a distributed execution plan. Map and reduction computations are automatically added to the plan. Patterns in the sequential program can be automatically identified to trigger map and reduction processing. Direct invocation of map and reduction processing is also provided. One or more portions of the reduce computation are pushed to the map stage and dynamic aggregation is inserted when possible. The system automatically identifies opportunities for partial reductions and aggregation, but also provides a set of extensions in a high-level computing language for the generation and optimization of the distributed execution plan. The extensions include annotations to declare functions suitable for these optimizations.

Abstract: A method for event positioning includes categorizing events into event groups based on a priority level, buffering the events in each event group into a group event queue, and determining an optimized position for events within each queue based, at least in part, on a processing time and an expected response time for each event in the group event queue.

Abstract: Embodiments of apparatuses, methods, and systems detecting spin loops in a virtual machine environment are disclosed. In one embodiment, an apparatus includes detection logic and virtualization logic. The detection logic is to detect whether a guest is executing a spin loop. The virtualization logic is to transfer control of the apparatus from the guest to a host in response to the detection logic detecting that the guest is executing the spin loop.

Abstract: A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using the ranges of addresses. Different ranges of addresses in the memory may be redistributed among a second set of functions in a second pipeline without waiting for the first set of functions to be flushed of data.

Abstract: A method for regulating execution of an application program includes a process for preparing the application and a process for executing the application. The preparation process divides the application program into related segments and encrypts instructions of at least one segment, positions encrypted instructions in at least two discontiguous regions within an executable file, and associates header information with at least one discontiguous region. The execution process initiates execution of the protected application when at least a portion of the application instructions are available to the computer only in encrypted form. Also provided are systems and methods to allow debugging of code extensions to protected applications without sacrificing protection of the application. A Secure Debugger allows extension developers to examine memory and set breakpoints in their own extensions, without permitting them to view information in the rest of the protected application.

Abstract: Methods and systems for handling exceptions, including being provided with a catch list, the catch list being a flattened inheritance tree for exception types in ascending inheritance order, receiving an exception from a thread, searching the catch list in ascending inheritance order to find a matching exception type to received exception.

Abstract: Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is to required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.

Abstract: There are provided a method and a processor for processing a thread. The thread includes a plurality of sequential instructions. The plurality of sequential instructions include some short-latency instructions and some long-latency instructions and at least one hazard instruction. The hazard instruction requires one or more preceding instructions to be processed before the hazard instruction is processed. The method includes the steps of: a) before processing each long-latency instruction, incrementing by one, a counter associated with the thread; b) after each long-latency instruction has been processed, decrementing by one, the counter associated with the thread; c) before processing each hazard instruction, checking the value of the counter associated with the thread, and i) if the counter value is zero, processing the hazard instruction, or ii) if the counter value is non-zero, pausing processing of the hazard instruction until a later time.

Abstract: A performance monitoring device has an interrupt detection unit that detects generation of an interrupt process to be executed by a processor in accordance with TLB entry invalidation executed in an operating system. A counter value acquisition unit acquires a counter value of a predetermined event counted by the processor when the interrupt process is detected by the interrupt detection unit. A process information acquisition unit acquires identification information for identifying a process executed on the processor from the operating system immediately before the interrupt process is detected by the interrupt detection unit. An associating unit associates the counter value acquired by the counter value acquisition unit during the interrupt process with the identification information acquired by the process information acquisition unit immediately before the interrupt process.

Abstract: A method for programmably controlling an exception includes performing, by a processor, a step of executing a control specification instruction for exception control specification that indicates whether an exception is enabled or not and setting a control specification value for the exception in a register and a step of executing a control execution instruction for exception control execution that indicates whether the exception is to be raised or not, determining whether the control specification value set in the register is a value for enabling the exception, and, when the control specification value is the value for enabling the exception, raising the exception. The method further includes performing a step of not raising the exception when the control specification value set in the register is not the value for enabling the exception.

Abstract: Handling business process exceptions. A method includes a computing system using a template, causing one or more operations to be performed to determine a problem that caused a business process exception. The computing system uses a template to cause one or more operations to be performed to perform one or more repair operations to address the business process exception. The computing system uses a template, to cause one or more operations to be performed to take action on the business process exception.

Abstract: A computer program product comprises a computer useable medium. The computer useable medium has a computer readable program such that when the computer readable medium is executed on a computer, the computer is caused to configure an interceptor at a service invocation point corresponding to a component service of a software application. Further, the computer is caused to record, at the interceptor, data in a trace file. The data is associated with a service invocation at the service invocation point. Finally, the computer is caused to provide the trace file to a service level debugger that navigates through the trace file.

Abstract: A method of enabling multiple different operating systems to run concurrently on the same computer, comprising selecting a first operating system to have a relatively high priority (the realtime operating system. such as C5); selecting at least one secondary operating system to have a relatively lower priority (the general purpose operating system, such as Linux); providing a common program (a hardware resource dispatcher similar to a nanokernel) arranged to switch between said operating systems under predetermined conditions; and providing modifications to said first and second operating systems to allow them to be controlled by said common program.

Abstract: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.

Abstract: Advanced programmable interrupt control for a multithreaded multicore processor that supports software compatible with x86 processors. Embodiments provide interrupt control for increased threads with minimal additional hardware by including in each processor core, a core advanced interrupt controller (core APIC) configured to determine a lowest priority thread of its corresponding processor core. Each core APIC reports its lowest priority thread level as a core priority to an input/output APIC. The I/O APIC routes interrupt requests to the core APIC with the lowest core priority. The selected core APIC then routes the interrupt request to the corresponding lowest priority thread. Each core APIC detects changes in priority levels of its corresponding processor core threads, and notifies the I/O APIC of any change to the corresponding core priority. Each core APIC may notify the I/O APIC as the core priority changes, or when the I/O APIC requests status from each core APIC.

Abstract: An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates to the microprocessor that the instructions are to execute in privileged (kernel) state only, and that the instructions are to communicate with privileged control registers, a field for designating which of a plurality of privileged architecture registers is to be modified, a field for designating which bit fields within the designated privileged architecture register is to be modified, and a field to designate whether the whether the designated bit fields are to be set or cleared. The instruction encoding allows a single instruction to atomically set or clear bit fields within privileged architecture registers, without reading the privileged architecture registers into a general purpose register.

Abstract: Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a first instruction execution thread and (ii) a second instruction thread for execution by an execution block of the multi-thread processing environment; providing a first interrupt signal via a first interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the first instruction execution thread; and providing a second interrupt signal via a second interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the second instruction execution thread. The first interrupt signal line and the second interrupt signal line are physically separate and distinct signal lines that are directly electrically coupled to one another.

Abstract: A soaker tool for an information handling system (IHS) exercises the IHS to provide a predetermined amount of utilization that a user may specify. The soaker tool schedules wait times following respective utilization times in alternating fashion to achieve a desired utilization value for a predetermined time period. The soaker tool monitors for a dispatch interrupt during the utilization times. Should a dispatch interrupt occur during a utilization time, the soaker tool accounts for the dispatch interrupt by determining a remainder utilization time to maintain utilization accuracy. The soaker tool may employ a parameter table that specifies utilization times, wait times, loop counts and adjustment cycles indexed to the respective utilization values that a user may select. The soaker tool may employ adjustment cycles to compensate for cumulative timing errors that may occur when running the tool for extended time periods.

Abstract: A method and apparatus within a processing system is provided for associating shadow register sets with interrupt routines. The invention includes a vector generator that receives interrupts, and generates exception vectors to call interrupt routines that correspond to the interrupts. The exception vector considers the type of interrupt and the priority level of the interrupt when selecting the exception vector. Shadow set mapping logic is coupled to the vector generator. The mapping logic contains a number of fields that correspond to the different exception vectors that may be generated. The fields are programmable by kernel mode instructions, and contain data mapping each field to one of a number of shadow register sets. When an interrupt occurs, the vector generator generates a corresponding exception vector. In addition, the shadow set mapping logic looks at the field corresponding to the exception vector, and retrieves the data stored therein.

Abstract: Millicode store access checking instructions are provided via an operand access control register (OACR) including a test modifier indicator, which is communicatively coupled to an instruction unit subsystem, the instruction unit subsystem for fetching and decoding instructions. The instructions include a millicode instruction with an operand defining an address to check for a store access exception. In addition, an execution unit for executing the millicode instruction performs a method. The method includes receiving the millicode instruction from the instruction unit subsystem, testing for the store access exception at the address as if the test modifier is set absent an update to the OACR, and outputting a result of the testing for the store access exception.

Abstract: Provided is information processing apparatus, information processing method and a record medium, which can prevent occurrence of manipulation, in a case of accessing a memory, without consuming the access band of the memory. A main-processing unit, a sub-processing unit and a memory for loading a program are provided and process limit information stored in the memory is stored in storing means. The sub-processing unit judges whether a program to be executed is manipulated or not, and loads a program to be executed in the memory in case that the program is not manipulated. The sub-processing unit refers to the process limit information before execution of a program, and not permits execution of the program of the main-processing unit in case that a process by the main-processing unit for information stored in the memory accords with a process included in the process limit information.

Abstract: Methods and apparatus to perform asynchronous control transfer are described. In one embodiment, upon occurrence of an event (e.g., an architectural event), a service routine data block (SRDB) is accessed via a service routine base pointer (SRDS) and a service routine offset value (SRDBP) to obtain the address of a yield service routine via a service routine instruction pointer (SRIP) and a service routine code segment (SRCS). Other embodiments are also described.

Abstract: A data processing apparatus is provided with a plurality of processing units (4 to 18; 32 to 38) executing respective streams of program instructions corresponding to respective processing threads. Exception control circuitry 20, 42 controls exception processing for a group of the processing unit in response to an exception triggering event. Each of the processing units moves only once and in sequence between normal, in-exception and done-exception states in response to a given exception event. A group of processing units moves in sequence between states normal, triggering and completing in response to the exception event. A counter value is used to track the number of processing units which have entered exception processing and then to track the number of processing units which have completed their exception processing.

Abstract: A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The system includes a state machine that determines an optimum length of a pipeline architecture based on a processing function to be performed. A pipeline sequence controller, responsive to the state machine, varies the depth of the pipeline based on the optimum length. A plurality of clock splitter elements, each associated with a corresponding plurality of latch stages in the pipeline architecture, are coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith.

Abstract: A signal processing apparatus for processing a periodic signal outputted from a signal source has a central processing unit and a task switch timer. The central processing unit performs multiple tasks including a signal processing task in parallel. In the signal processing task, the central processing unit starts to process the periodic signal after performing a synchronization processing to synchronize with the periodic signal, setting the task switch timer to a predetermined time upon completion of the synchronization processing, and enabling an interrupt to the central processing unit upon completion of the synchronization processing. The task switch timer disables the interrupt to the central processing unit immediately before expiring. The task switch timer outputs a task switch signal to the central processing unit when expiring, so that the central processing unit switches to the signal processing task.

Abstract: Methods and systems thereof for exception handling are described. An event to be handled is identified during execution of a code sequence. A bit is set to indicate that handling of the event is to be deferred. An exception corresponding to the event is generated if the bit is set.

Abstract: A computer implemented method of computer implemented method for installing a code object in a user process virtual memory space, while the user process is running is provided. The user process is run in a virtual memory space. A controller process is run in a different virtual memory space than the user process. The control process requests to a kernel module to install the code object into the virtual memory space of the user process. The kernel module installs the code object into the virtual memory space of the user process, while the user process is running.

Abstract: A processor receives interrupts of a same type from hardware. The processor determines a rate at which the interrupts are being received. The processor compares the rate at which the interrupts are being received to a threshold rate. In response to determining that the rate at which the interrupts are being received is greater than the threshold rate, the processor sends just the first received interrupt to firmware for processing. All other of the interrupts are not sent from the processor to the firmware but instead are suppressed by the processor. By comparison, in response to determining that the rate at which the interrupts are being received is less than the threshold rate, the processor can send all the interrupts from the processor to firmware for processing.

Abstract: Various technologies and techniques are disclosed for providing concurrent exception handling. Exceptions that occur in concurrent workers are caught. The caught exceptions are then forwarded from the concurrent workers to a coordination worker. The caught exceptions are finally aggregated into an aggregation structure, such as an aggregate exception object. This aggregation structure is rethrown and the individual caught exceptions may then be handled at a proper time.

Abstract: A system, method and computer program product for providing a programmable quiesce filtering register. The method includes receiving a quiesce interruption request at the processor. The processor is executing in a mode. A filtering zone associated with the mode is identified. It is determined if the quiesce interruption request can be filtered by the processor. The determining is responsive to the filtering zone and to contents of a programmable filtering register for indicating exceptions to filtering performed by the receiving processor. The quiesce interruption request is filtered in response to determining that the request can be filtered.

Abstract: A patching mechanism in a multi-core environment that includes sending an inter-core non-maskable interrupt to each target Virtual Central Processing Unit (CPU) (VCPU) in a target VCPU group, which share a code segment, so that said each target VCPU enters a patch synchronization state in response to the inter-core non-maskable interrupt. Thereafter, the patch synchronization state of said each target VCPU is monitored, and after all the target VCPUs have entered the patch synchronization state, embodiments modify a first instruction of an original function to be patched of said each target VCPU into an abnormal instruction, and outputting a patch synchronization state end notification to all the target VCPUs, so that the original function to be patched is enabled to jump to a new patch function in an exception handling process.

Abstract: An information handling system includes a memory, a processor, and an instruction tracking unit. The processor executes program code and, while the program code executes, the instruction tracking unit decodes a multi-purpose no-op instruction within the program code. In turn, the instruction tracking unit sends an interrupt to the processor, which invokes a profiling module to collect and store profiling data in a profiling buffer.

Abstract: A method of managing the software architecture of a radio communication circuit is provided. The software architecture includes a radio communication software stack and at least one client application. The radio communication software stack includes a radio communication interrupt manager and at least one radio communication task. The client application includes at least one client task. The method includes interleaving, within the radio communication software stack, at least one client interrupt manager, included in the client application, and belonging to the group comprising: a first client interrupt manager of execution priority level that is higher than the at least one radio communication task and lower than the radio communication interrupt manager; and a second client interrupt manager of execution priority level that is higher than the at least one radio communication task and higher than the radio communication interrupt manager.

Abstract: Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context. Without modifying a pre-existing operating system of the computer, an entry exception is establishing to be raised on each entry to the operating system at a specified entry point or on a specified condition. The entry exception has an associated entry handler programmed to save a context of an interrupted thread and modify the thread context before delivering the modified context to the operating system. A resumption exception is established to be raised on each resumption from the operating system complementary to one of the specified entries. The resumption exception has an associated exit handler programmed to restore the context saved by a corresponding execution of the entry handler.

Abstract: A method for executing by a processing unit a program stored in a memory, includes: detecting a piece of information during the execution of the program by the processing unit, and if the information is detected, triggering the execution of a hidden subprogram by the processing unit. The method may be applied to the securization of an integrated circuit.

Abstract: A method includes: decoding an instruction a first time to obtain a first decoded instruction; decoding the instruction a second time to obtain a second decoded instruction; comparing at least a portion of the first decoded instruction to at least a portion of the second decoded instruction; and when the at least a portion of the first decoded instruction matches the at least a portion of the second decoded instruction, executing the instruction.

Abstract: In wireless communications such as in the Bluetooth communication system, an execution unit sequentially receives software instructions for execution. Prior to completing each instruction, the execution unit issues an interrupt indicating the upcoming completion of the instruction execution and awaits receipt of the next instruction. A Link Manager issues limited instructions, and a Link Controller includes a hardware execution unit for executing the limited instructions. A processing unit in the Link Manager performs remaining functions under control of a software program.

Abstract: Instruction execution includes fetching an instruction that comprises a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value. It further includes executing the instruction to determine whether to perform a trap, wherein executing the instruction includes selecting from a plurality of tests at least one test for determining whether to perform a trap and carrying out the at least one test.

Abstract: Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one embodiment a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.

Abstract: A method and system of presenting an interrupt request to processors executing in lock step. At least some of the illustrative embodiments are computer systems comprising a first processor configured to execute a program, a second processor configured to execute a duplicate copy of the program in lock step with the first processor, and a logic device coupled to the processors. The logic device is configured to present an interrupt request to the processors when the processors are at substantially the same computational point in the program.