Abstract: A system for collecting events relating to multiple distributed physical systems includes multiple event collection cards (100), each receiving events from one of the distributed physical systems. Each event collection card includes a time stamp clock (120) configured to provide a time stamp when each event is received, an event memory (110) configured to store the received events, a sync interface unit (130) configured to receive a sync signal, a sync control unit (125) configured to synchronize the time stamp clock (120) to the sync signal received by the sync interface (130), and a collection control unit (115) configured to time stamp the collected events according to the time stamp clock (120) synchronized to the sync signal, and to store the time stamped events in the event memory (110).

Abstract: A new computing architecture that mimics the behavior of biological cells, called a Whole Cell Computer (WCC) is disclosed. The WCC is a computational architecture based on the biochemical processing of cells. It represents both a specialization and an extension of membrane computing. It is derived from the properties of biological cells and has extensive statistical redundancy built in. It can be programmed using genetic programming techniques.

Abstract: A multiprogrammed multiprocessor system comprises a plurality of processors and some communications resources such as networks through which the processors communicate with each other. A plurality of tasks may be executed on the system, and the allocation of the communications resources among the tasks is globally controlled. The allocation of resources among the tasks running on the system can be dependent on the signature of the tasks, where one component of a task signature is a measure of the communication resources needed by the task. The scheduling of a task running on the system may also be dependent on the signature of the task. The allocation of communications resources can be globally controlled using a variety of techniques including: packet injection into the communications resources using periodic strobing or using global flow control; using global implicit acknowledgments; by destination scheduling; by pacing; or by prioritized communication scheduling.

Abstract: An instruction memory system is shared by a plurality of processors and the system utilizes an increased bandwidth to support the combined number of processors. The total instruction address space is divided into code segments according to the disjoint tasks to be performed. The instruction codes of each processor are consolidated into one copy for control instructions and duplicate copies for other disjoint tasks such as inbound requests and outbound requests that have greater processor contention. Interleaving of the memory arrays for certain disjoint tasks serves to provide a larger number of instructions for these tasks. The system utilizes arbiters to receive all disjoint tasks and to control multiplexors that send addresses to memory arrays.

Abstract: A processor comprising a new architectural feature called a Register Domain, where a Register Domain has a register file, at least one execution unit, and coupling circuitry between the two. A processor will typically have a plurality of Register Domains, and Register Domains may have different types of execution units within them. Individual Register Domains will be visible to a user.

Abstract: The invention relates to a bus for a highly scalable multiprocessor system, to a redundant bus system that utilizes this bus, and to a method for transmitting information in this bus system. To guarantee an optimally high throughput of individual accesses onto a shared memory, the bus 3 consists of an address bus 4 and a data bus 5, which are operated logically independent of one another and which are functionally connected only via a common identifier. In this way, the dynamic holding of the address bus 4 and of the data bus 5 as well as the latencies are minimized.

Abstract: The invention comprises a modem apparatus adapted to provide full messaging and communications interface between a control device and a communications medium such as a telephone line. The modern can comprise an interface adapted to communicate directly with a control system device, such as a programmable logic controller (PLC), using a communications protocol compatible with the normal network communications used in a distributed control system. The apparatus advantageously interfaces directly with unmodified control system devices, providing the ability to send and receive messages from remote devices or personnel via a communications medium. The invention also comprises a control system including a modem device providing full communications between a control device and remote personnel and/or devices.

Abstract: A system having a plurality of processors, each one of the processors being adapted to issue a control signal and a processor ID code. Each one of the processors has: a unique, pre-assigned processor ID code, and a common software program. The software program operates to: receive the control signal and the processor ID code from the issuing one of the processors along with an indication of the one of the processors which issued the particular control signal and processor ID code; and test whether the received processor ID code is the same as the processor issuing the command and if so, generate one of the broadcast mode or uni-cast modes; otherwise, generate the other one of the broadcast or uni-cast modes.

Abstract: A messaging scheme that conserves system memory bandwidth during a memory read operation in a multiprocessing computer system is described. A source processing node sends a memory read command to a target processing node to read data from a designated memory location in a system memory associated with the target processing node. The target node transmits a read response to the source node containing the requested data and also concurrently transmits a probe command to one or more of the remaining nodes in the multiprocessing computer system. In response to the probe command each remaining processing node checks whether the processing node has a cached copy of the requested data. If a processing node, other than the source and the target nodes, finds a modified cached copy of the designated memory location, that processing node responds with a memory cancel response sent to the target node and a read response sent to the source node.

Abstract: The present invention provides a system and method for improving the performance of general purpose processors by expanding at least one source operand to a width greater than the width of either the general purpose register or the data path width. In addition, the present invention provides several classes of instructions which cannot be performed efficiently if the operands are limited to the width and accessible number of general purpose registers. The present invention provides operands which are substantially larger than the data path width of the processor by using a general purpose register to specify a memory address from which at least more than one, but typically several data path widths of data can be read. The present invention also provides for the efficient usage of a multiplier array that is fully used for high precision arithmetic, but is only partly used for other, lower precision operations.

Abstract: A network interface architecture includes a processor having an associated program memory, and a programmable logic device coupled to the processor. A connection port of the logic device is adapted to be coupled to a medium of a selected network having a defined network protocol, and the logic device has an associated configuration memory. A data communication path is coupled to the processor and the logic device, and is arranged to connect with a host device for transferring data between the host device and a network to which the logic device is coupled. The processor responds to information identifying a selected network by loading corresponding network protocol data from the configuration memory and the program memory into the logic device and the processor. The host device may include, without limitation, a personal, lap top, desk top or hand-held computer, a network appliance, file server, printer, vending machine, cell phone or the like.

Abstract: A method for prototyping an integrated circuit may include selecting at least one daughter card for connection to a motherboard. The daughter card is selected having an ability to provide functionality corresponding to a specific integrated circuit device. The at least one daughter card is connected to the motherboard so that the daughter card is communicatively connected to common memory provided on the motherboard. The motherboard is connected to an information handling system utilizing a prototyping interface device, the information handling system providing a virtual software modeling environment for an integrated circuit. The at least one daughter card, information handling system, prototyping interface device and motherboard emulate an integrated circuit design. At least one of software and system integration of the integrated circuit emulated by the motherboard, information handling system, prototyping interface device and the at least one daughter card is tested.

Abstract: A method for prototyping an integrated circuit may include selecting at least one daughter card for connection to a motherboard. The daughter card is selected having an ability to provide functionality corresponding to a specific integrated circuit device. The at least one daughter card is connected to the motherboard so that the daughter card is communicatively connected to common memory provided on the motherboard. The at least one daughter card and motherboard emulate an integrated circuit design. At least one of software and system integration of the integrated circuit emulated by the motherboard and the at least one daughter card is tested.

Abstract: An inter-chip communication (ICC) mechanism enables any processor in a pipelined arrayed processing engine to communicate directly with any other processor of the engine over a low-latency communication path. The ICC mechanism includes a unidirectional control plane path that is separate from a data plane path of the engine and that accommodates control information flow among the processors. The mechanism thus enables inter-processor communication without sending messages over the data plane communication path extending through processors of each pipeline.

Abstract: A multi-processor system (10) includes a plurality of processors (12). Each processor (12) has an integrated memory (16) operable to provide, receive, and store data. Each processor (12) also includes an integrated memory controller (30) in order to control read and write access to the integrated memory (16). Additionally, each processor (12) includes an integrated memory directory (18) operable to maintain a plurality of memory references to data within the integrated memory (16). The multi-processor system (10) also includes an external switch (14) coupled to each of the plurality of processors (12). The external switch (14) passes data to and from any of the plurality of processors (12). The external switch (14) has an external directory (22). The external directory (22) provides a memory reference for each of the plurality of processors (12) to remote data that is not provided within its own integrated memory directory (18).

Abstract: A programmable processor that comprises a general purpose processor architecture, capable of operation independent of another host processor, having a virtual memory addressing unit, an instruction path and a data path; an external interface; a cache operable to retain data communicated between the external interface and the data path; at least one register file configurable to receive and store data from the data path and to communicate the stored data to the data path; and a multi-precision execution unit coupled to the data path. The multi-precision execution unit is configurable to dynamically partition data received from the data path to account for an elemental width of the data and is capable of performing group floating-point operations on multiple operands in partitioned fields of operand registers and returning catenated results. In other embodiments the multi-precision execution unit is additionally configurable to execute group integer and/or group data handling operations.

Abstract: When converting a sequential execution source program into a parallel program to be executed by respective processors (nodes) of a distributed shared memory parallel computer, a compiler computer transforms the source program to increase a processing speed of the parallel program. First, a kernel loop having a longest sequential execution time is detected in the source program. Next, a data access pattern equal to that of the kernel loop is reproduced to generate a control code to control first touch data distribution. The first touch control code generated is inserted in the parallel program.

Abstract: An object oriented processor array includes a library of functional objects which are instantiated by commands through a system object and which communicate via a high level language. According to the invention, instantiated objects communicate directly with a script server which is programmed to react to data events generated by instantiated objects. One script server may serve several object oriented processor arrays, or an object oriented processor array may have a local script server. The object oriented processor array may be embodied in hardware, software, or a combination of hardware and software. Each functional object may include a discrete hardware processor or may be embodied as a virtual processor within the operations of a single processor. According to one embodiment, the object oriented processor array is formed on a single chip or on a single processor chip and an associated memory chip.

Abstract: A massively parallel data processing system consisting of an array of closely spaced cells where each cell has direct output means as well as means for processing, memory and input. The data processing system according to the present invention overcomes the von Neumann bottleneck of uniprocessor architectures, the I/O and memory bottlenecks that plague parallel processors, and the input bandwidth bottleneck of high-resolution displays.

Abstract: A data processing system includes an interconnect, a plurality of nodes coupled to the interconnect that each include at least one agent, response logic within each node, and a queue. In response to snooping a transaction on the interconnect, each agent outputs a snoop response. In addition, the queue, which has an associated agent, allocates an entry to service the transaction. The response logic within each node accumulates a partial combined response of its node and any preceding node until a complete combined response for all of the plurality of nodes is obtained. However, prior to the associated agent receiving the complete combined response, the queue speculatively deallocates the entry if the partial combined response indicates that an agent other than the associated agent will service the transaction.

Abstract: A node controller (12) in a computer system (10) includes a processor interface unit (24), a memory directory interface unit (22), and a local block unit (28). In response to a memory location in a memory (17) associated with the memory directory interface unit (22) being altered, the processor interface unit (24) generates an invalidation request for transfer to the memory directory interface unit (22). The memory directory interface unit (22) provides the invalidation request and identities of processors (16) affected by the invalidation request to the local block unit (28). The local block unit (28) determines which ones of the identified processors (16) are present in the computer system (10) and generates an invalidation message for each present processor (16) for transfer thereto. Each of the present processors (16) process their invalidation message and generate an acknowledgment message for transfer to the processor interface unit (24) that generated the invalidation request.

Abstract: A processor architecture containing multiple closely coupled processors in a form of symmetric multiprocessing system is provided. The special coupling mechanism allows it to speculatively execute multiple threads in parallel very efficiently. Generally, the operating system is responsible for scheduling various threads of execution among the available processors in a multiprocessor system. One problem with parallel multithreading is that the overhead involved in scheduling the threads for execution by the operating system is such that shorter segments of code cannot efficiently take advantage of parallel multithreading. Consequently, potential performance gains from parallel multithreading are not attainable. Additional circuitry is included in a form of symmetrical multiprocessing system which enables the scheduling and speculative execution of multiple threads on multiple processors without the involvement and inherent overhead of the operating system.

Abstract: The present invention provides a processor device and technique having the capability of providing a two-processor solution with only one processor. In accordance with the principles of the present invention, a host processor is programmed in its native source and machine code language, and an emulated second processor is programmed in a different native source or machine code language particular to that emulated processor, to allow programming specialists in the different processors to develop common code for use on the same host processor. A multitasking operating system is included to allow time sharing operation between instructions from program code relating to the host processor (e.g., a DSP in the disclosed embodiment), and different program code relating to the emulated processor. The program code relating to the host processor (e.g., DSP) is written in program code which is native to the DSP, while the program code relating to the emulated processor (e.g.

Abstract: A file loader including a processor configuration management unit for managing status information of processors, a function database management unit for managing storage information of running files corresponding to functions installed in the processors, and a file load control unit for (i) recognizing other processors in the system having functions identical to a function which has to be installed in the concerned processor based on the storage information, (ii) searching for one processor among the other processors to send the files, while referring to the status of the other processors by the status information, and (iii) performing control for making the above sender processor load the running files required for the related function.

Abstract: A computer system is presented implementing a system and method for properly ordering write operations. The system and method for properly ordering write operations aids in maintaining memory coherency within the computer system. The computer system includes multiple interconnected processing nodes. One or more of the processing nodes includes a central processing unit (CPU) and/or a cache memory, and one or more of the processing nodes includes a memory controller coupled to a memory. The CPU or cache generates a write command to store data within the memory. The memory controller receives the write command and responds to the write command by issuing a target done response to the CPU or cache after the memory controller: (i) properly orders the write command within the memory controller with respect to other commands pending within the memory controller, and (ii) determines that a coherency state with respect to the write command has been established within the computer system.

Abstract: A computer system is described having a plurality of resources which includes a plurality of processors, a distributed point-to-point transmission infrastructure for interconnecting the plurality of processors, and a partitioning processor for configuring the plurality of resources into at least one partition. Each partition comprises a subset of the plurality of resources. The partitioning processor is operable to configure the resources by enabling at least one link between at least one of the plurality of processors and at least one other one of the plurality of processors according to a previously specified partitioning schema. The link(s) so enabled corresponds to a portion of the point-to-point transmission infrastructure.

Abstract: A method, for executing a load locked and a store conditional instruction in a processor, achieves an atomic read-write operation to a memory block. First the load locked instruction is executed to read a memory block, and the processor in response to executing the load locked instruction issues a read modify system command to read the block and to take ownership of the block by the processor, and also sets a lock flag for the address of the memory block, and writes a value of the memory block into a cache of the processor as a cache copy of the memory block. The lock flag, upon receipt of an invalidate message by the processor for the cache copy of the memory block, is reset if any invalidate messages for the memory block are received by the processor. The processor waits for a selected time interval before the processor surrenders ownership of the memory block upon receipt of an ownership request message, if any is received by the processor after execution of the load locked instruction.

Abstract: A method, apparatus, article of manufacture, and a memory structure for selecting a coordinator node to configure a parallel processing system having a plurality of interconnected nodes. The method comprises the steps of: multicasting a best available node list and a best desired node list from each node to each node; receiving the best available node list and the best desired node list from each node in each node; and selecting the coordinator node as the node originating a best available node list that includes every node in the desired node list. If no node is identified as originating a best available node list that includes every node in the desired list, the node originating a best available node list that includes the greatest number of nodes in the desired node list is selected as the coordinator node.

Abstract: A data processing system includes at least first and second nodes and a segmented interconnect having coupled first and second segments. The first node includes the first segment and first and second agents coupled to the first segment, and the second node includes the second segment and a third agent coupled to the second segment. The first node further includes cancellation logic that, in response to the first agent issuing a request on the segmented interconnect that propagates from the first segment to the second segment and the second agent indicating ability to service the request, sends a cancellation message to the third agent instructing the third agent to ignore the request.

Abstract: A multiplexed bus data transmission control system, suitable for a multiplexed bus data flow control, according to the invention. The system includes a bus flow monitor, a critical value controller and a transmission control unit. The bus flow monitor is used to calculate the data flow of the multiplexed bus and to output a calculated result according to a time constant. The critical value controller receives the calculate result and outputs a corresponding critical value according to a ratio of the calculated result and the time constant. The transmission control unit is used to control a data transmission device using the multiplexed bus according to the critical value outputted from the critical value controller.

Abstract: A system, such as an AMBA based system, wherein an interrupt controller is coupled directly to a processor, thereby providing that the processor can access the interrupt controller without having to access a system bus. Specifically, the interrupt controller may be coupled to a port of the processor, such as a tightly coupled memory (TCM) port or a coprocessor port of the processor. The interrupt controller may be coupled to the TCM port along with SRAM.

Abstract: A plurality of CPU units are used for multiple CPU control. Each CPU unit includes a device memory for processing device data, a shared memory for reading data from and writing data into the CPU unit and other CPU units, and OS describing the procedure for transferring data, and a microprocessor for transferring data between its own CPU unit and other CPU units according to the procedure described in the OS. Each microprocessor fetches the device data stored in the shared memory of other CPU units into the device memory of its own CPU unit.

Abstract: A method of, apparatus for and computer-readable medium for obtaining a program for a distributed memory-type parallel computer by dividing data for a program written for a serial processing computer. The method comprises changing a declaration of an array to be subjected to indirect or irregular division which is designated by the mapping array in the program into a declaration of an allocation array; inserting statements to declare the allocation array for converting subscripts and to calculate the size of the divided array during processing, and inserting a statement to preserve or to release an area for divided arrays corresponding to the calculated length of arrays to be divided and subscript conversion arrays during processing.

Abstract: A single integrated circuit chip interfaces device control circuitry of a device to a client machine via a computer network. The chip comprises an internal data bus; a central processing unit connected to the internal data bus; an internal memory connected to the internal data bus; a device interface connected to the internal data bus, wherein the device interface comprises circuit blocks for communicating digital information between the integrated circuit and the device control circuitry; and a network interface connected to the internal data bus, wherein the network interface comprises circuit blocks for communicating digital information between the integrated circuit and the computer network.

Abstract: A data processing system comprises a plurality of nodes and a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a memory which is partitioned into a plurality of sections, including a first section for directly sharable memory located on the printed circuit board, and a second section for block sharable memory. A local bus connects the processor, block sharable memory and printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board.

Abstract: An apparatus is described that comprises a data processing unit and at least one coprocessor. The data processing unit comprises a register file having registers, a memory, a plurality of execution units, a coprocessor interface for coupling the at least one coprocessor with the data processing unit, and a pipeline configuration for processing instructions having a fetch stage for fetching an instruction from the memory, a decode stage for decoding an operational code from the instruction, an execution stage for activating one of the execution units, and a write-back stage for God writing back from the execution unit. The data processing unit comprises read-and write-lines coupling the register file with the coprocessor for exchanging operands, at least one control line indicating that the coprocessor is busy, and a plurality of control lines from the decode stage for controlling the coprocessor which are operated upon detection of a coprocessor instruction.

Abstract: A data processing system includes a plurality of processing nodes that each contain at least one processor and data storage. The plurality of processing nodes are coupled together by a system interconnect. The data processing system further includes a configuration utility residing in data storage within at least one of the plurality of processing nodes. The configuration utility selectively configures the plurality of processing nodes into either a single non-uniform memory access (NUMA) system or into multiple independent data processing systems through communication via the system interconnect.

Abstract: A new method of distributed computing, sideband computing, that is global, scalable and can utilize many idle CPU resources worldwide. Sideband is defined as when a user connects to some (normal) network services, a separate communication channel is opened, through which a server distributes its tasks to all the clients and collects the results later. By this method, any network server which has a lot of clients can compute very large parallel computing problems by dividing it into small individual parts and have them calculated by its clients. With little cost, the network server can act as a supercomputer.

Abstract: A method and computer system for efficiently accessing resources in a multiprocessor computer system. Multiple resources are grouped into nodes and system resource descriptors are maintained as data structures. The method incorporates traversing a data structure to efficiently allocate resources within a grouping of nodes. Each node in the system is assigned a node identifying number. This number identifies a node location within a multiprocessor and is used to determine latency between nodes, either through an average latency table or a system interconnect connection table. The data structure comprises secondary data structures therein for storing processor, bus, memory and shared cache information. The data structure includes pointers to each of the secondary data structures. In addition, each node or grouping of nodes may include subnodes. As such, the system provides for a method of recursively accessing additional data structure levels for each level of nodes and/or subnodes in the system.

Abstract: A computer system splits a data space to partition data between processors or processes. The data space may be split into sub-regions which need not be orthogonal to the axes defined the data space's parameters, using a decision tree. The decision tree can have neural networks in each of its non-terminal nodes that are trained on, and are used to partition, training data. Each terminal, or leaf, node can have a hidden layer neural network trained on the training data that reaches the terminal node. The training of the non-terminal nodes' neural networks can be performed on one processor and the training of the leaf nodes' neural networks can be run on separate processors. Different target values can be used for the training of the networks of different non-terminal nodes. The non-terminal node networks may be hidden layer neural networks.

Abstract: A method, apparatus, article of manufacture, and a memory structure for selecting nodes while configuring a parallel processing system is disclosed. The method comprises the steps of multicasting a request from a coordinator node to the non-coordinator node to transmit a list of nodes reachable by the non-coordinator node; receiving the list of nodes reachable by the non-coordinator node in the coordinator node; generating a global view of the nodes reachable by the non-coordinator node; generating a node list having member nodes belonging to the configured parallel processing system according to a first criteria; and transmitting the parallel processing node list to the member nodes. The apparatus comprises a means for performing the steps described above, and the article of manufacture comprises a program storage device tangibly embodying computer instructions for performing the above method steps.

Abstract: A system for processing a batch which is distributed into a plurality of independent segments. A preferred embodiment of this invention calls for implementation on a symmetrical multiprocessing platform, however, the invention is also applicable to massively parallel architectures as well as uniprocessor environments. Each segment comprises a plurality of discrete events, each discrete event comprising a plurality of sub-events to be processed. The system operates to process each discrete event within each segment sequentially and each sub-event within each discrete event sequentially. The plurality of segments may be processed on an uniprocessor, an SMP system or an MPP system. By balancing the number of discrete events in each segment using a “course grain” approach, a flexible but efficient use of processor availability is obtained.

Abstract: A messaging scheme that conserves system memory bandwidth and maintains cache coherency during a victim block write operation in a multiprocessing computer system is described. A source node having a dirty victim cache block—a modified cache block that is being written back to a corresponding system memory—sends a victim block command along with the dirty cache block data to the target processing node having associated therewith the corresponding system memory. The target node responds with a target done message sent to the source node and also initiates a memory write cycle to transfer the received cache block to the corresponding memory location. If the source node encounters an invalidating probe between the time it sent the victim block command and the time it received the target done response, the source node sends a memory cancel response to the target node.

Abstract: A buffer cache management structure, or metadata, for a computer system such as a NUMA (non-uniform memory access) machine, wherein physical main memory is distributed and shared among separate memories. The memories reside on separate nodes that are connected by a system interconnect. The buffer cache metadata is partitioned into portions that each include a set of one or more management data structures such as hash queues that keep track of disk blocks cached in the buffer cache. Each set of management data structures is stored entirely within one memory. A first process performs operations on the buffer cache metadata by determining, from an attribute of a data block requested by the process, in which memory a portion of the metadata associated with the data block is stored. The process then determines if the memory containing the metadata portion is local to the process. If so, the first process performs the operation.

Abstract: A distributed digital rule processor to create a single system image (SSI) on a cluster of von Neumann processors. The rule processing engine has a group of digital rule nets each having their own local bindery and local controllers which are interconnected by a global bindery. Slave translators are interfaced to the global bindery to receive rule calls from the rule nets and return statuses. A compiler maps the typical source code instructions into groups of rules which are stored in the rule nets' storage area. The rules contain groups of input variables and output variables. The output variables of a calling rule become the input and data for the called rule. Slave application processes on the von Neumann processors perform slave activities for the slave translators, as the rule nets are unable to manipulate data. Rules received from the rule nets by slave translators are processed and processed data or return statuses are sent back to the nets for further instructions.

Abstract: A parallel processor capable of exhibiting a high processing performance, which when receiving as input access requests generating page faults to sub-banks from a plurality of processor elements connected to a common bus and another access request is input while data is being transferred between sub banks and an external memory via an external access bus in response to the input access requests, a shared memory stores the other access request in a request queue and makes a control circuit execute the stored access request when the stored access request does not generate a page fault.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention provide a development tool that enables computer programmers to design and develop a data flow program for execution in a multiprocessor computer system. The tool displays an interface that enables the programmer to define a region divided into multiple blocks, wherein each block is formed of a set of values associated with a function, and to define sets of the blocks, each block in a set having a state reflected by a designated portion of the program that when executed transforms the values forming the block based on the function. The interface also records any dependencies among the blocks, each dependency indicating a relationship between two blocks and requiring the portion of the program associated with a first block of the relationship to be executed before the portion of the program associated with a second block of the relationship.

Abstract: The present invention provides a cross-bar circuit that implements a switch of a broadband processor. In an exemplary embodiment, the present invention provides a cross-bar circuit that, in response to partially-decoded instruction information and in response to datapath information, (1) allows any bit from a 2n-bit (e.g. 256-bit) input source word to be switched into any bit position of a 2m-bit (e.g. 128-bit) output destination word and (2) provides the ability to set-to-zero any bit in said 2m-bit output destination word. The cross-bar circuit includes: (1) a switch circuit which includes 2m 2n:1 multiplexor circuits, where each of the 2n:1 multiplexor circuits (a) has a unique n-bit (e.g.

Abstract: A messaging scheme that conserves system memory bandwidth during a memory read operation in a multiprocessing computer system is described. A source processing node sends a memory read command to a target processing node to read data from a designated memory location in a system memory associated with the target processing node. The target node transmits a read response to the source node containing the requested data and also concurrently transmits a probe command to one or more of the remaining nodes in the multiprocessing computer system. In response to the probe command each remaining processing node checks whether the processing node has a cached copy of the requested data. If a processing node, other than the source and the target nodes, finds a modified cached copy of the designated memory location, that processing node responds with a memory cancel response sent to the target node and a read response sent to the source node.

Abstract: Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subdivided by software into multiple partitions, each with the ability to run a distinct copy, or instance, of an operating system. At different times, different operating system instances may be loaded on a given partition. Resources, such as CPUs and memory, can be dynamically assigned to different partitions and used by instances of operating systems running within the machine by modifying the configuration. The partitions themselves can also be changed without rebooting the system by modifying the configuration tree. Each instance keeps track of the CPUs in the system and their respective operational statuses relative to the instance, such as compatibility with the instance, control by the instance, and availability to the instance for SMP processing.