Abstract: Memory consistency is provided in an emulated processing environment. A processor architected with a weak memory consistency emulates an architecture having a firm memory consistency. This memory consistency is provided without requiring serialization instructions or special hardware.

Abstract: A communication device includes a voice data and RF integrated circuit (IC) that includes a memory module that stores a least one application as a plurality of operational instructions, the at least one application having a plurality of power modes that each correspond to one of a plurality of use characteristics. A processing module executes the plurality of operational instructions and determines a selected one of the plurality of power modes based on current use characteristics of the at least one application, and the generates a power mode signal based on the selected one of the plurality of power modes. An off-chip power management circuit receives the power mode signal and that generates a plurality of power supply signals to the voice data and RF IC based on the power mode signal.

Abstract: A partition that is executed by multiple processing nodes. Each node includes multiple cores and each of the cores has a frequency that can be set. A first frequency range is provided to the cores. Each core, when executing the identified partition, sets its frequency within the first frequency range. Frequency metrics are gathered from the cores running the partition by the nodes. The gathered frequency metrics are received and analyzed by a hypervisor that determines a second frequency range to use for the partition, with the second frequency range being different from the first frequency range. The second frequency range is provided to the cores at the nodes executing the identified partition. When the cores execute the identified partition, they use a frequencies within the second frequency range.

Abstract: A network of switches may be adapted to route image data to one or more processor cores based on tags associated with data samples, where each tag includes at least one reference-space coordinate value. When image data is received by the network, the image data may be spatially transformed to a reference space, e.g., the physical space that is represented by the image data, to generate the data samples and each data sample may be tagged with a corresponding reference space coordinate value and routed through the network to one or more of the processors according to the tag.

Abstract: Applying firmware updates to servers in a data center, the servers including one or more active servers and a standby server, each server mapped to separate remote computer boot storage, including applying the firmware updates to the standby server; selecting an active server for firmware updating; powering off the selected active server by the system management server; remapping the standby server to the remote computer boot storage for the selected active server; rebooting the standby server from the remote computer boot storage for the selected active server, designating the standby server as an active server; remapping the selected active server to the remote computer boot storage formerly mapped to the standby server; and rebooting the selected active server from the remote boot storage formerly mapped to the standby server, designating the selected active server as a standby server.

Abstract: A microprocessor for processing instructions comprises multiple clusters for receiving the instructions, each of the clusters having a plurality of functional units for executing the instructions, multiple register sub-files each having multiple registers for storing data for executing the instructions, wherein each of the clusters is associated with corresponding one of the register sub-files so that an instruction dispatched to a cluster is executed by accessing registers in a register sub-file associated with the cluster to which the instruction is dispatched, a register-renaming unit for renaming target registers in an instruction with registers in a register sub-file associated with a cluster to which the instruction is dispatched, and issue-queue units each of which is associated with a corresponding one of the clusters, wherein an issue-queue unit holds instruction renamed by the register-renaming unit until the renamed instruction is issued to be executed in a cluster associated with the issue-queue u

Abstract: A radio control board passes a plurality of digital samples between a memory of a computing device and a radio frequency (RF) transceiver coupled to a system bus of the computing device. Processing of the digital samples is carried out one or more cores of a multi-core processor to implement a software-defined radio.

Abstract: A first storing unit stores therein a chain indivisibility instruction. A detecting unit detects a change of first data that is distributed in a node computer. A first designating unit designates, when the detecting unit detects the change in the first data, an indivisibility instruction corresponding to the first data from which the change is detected, by referring to the first storing unit. A first executing unit executes the indivisibility instruction designated by the first designating unit.

Abstract: A method and a device are provided for performing switching and data comparison in a computer system having at least two processing units which each process data at a specified clock pulse, in which a switchover arrangement is provided and switching takes place between at least two operating modes, and a comparison unit is provided. A first operating mode corresponding to a compare mode is provided, and a second operating mode corresponding to a performance mode is provided. A synchronization arrangement is provided which assigns to the specifiable data a clock pulse information as a function of a processing unit, and at least the comparison unit takes into consideration this clock pulse information in the corresponding data.

Abstract: A unit and method for clock changeover in a system having at least two processing units, in which switchover device(s) are provided by which a switchover between at least two operating modes of the system is able to be implemented in which a clock pulse changeover is carried out in at least one processing unit in a switching of the operating mode.

Abstract: In parallel computers, sorting and calculation of large-scale data are realized while large-scale data is held in the respective processors without sharing the large-scale data between the processors so as to reduce communication between the processors. An information processing method gives global dimension value numbers common to all the processing modules to the dimension values for calculation, calculates measures for each of the dimension value numbers within the processing module, and lastly calculates measures commonly between all processing modules. The value list and pointer arrangement to the value list are locally held in each processing module and the order of the dimension values as a reference is globally held between processing modules. As a result, it is possible to eliminate mutual access by processing modules for acquiring data required for calculation and only data required for deciding the order of the dimension values is communicated between the processing modules.

Abstract: The present invention discloses a modified computer architecture which enables an applications program to be run simultaneously on a plurality of computers. Shared memory at each computer is updated with amendments and/or overwrites so that all memory read requests are satisfied locally. During initial program loading, or similar, instructions which result in memory being re-written or manipulated are identified. Additional instructions are inserted to cause the equivalent memory locations at all computers to be updated.

Abstract: A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory connected to the processing elements. The processing elements transfer data to and from the memory at the memory address. The memory interface can connect to a host configured to access data in a conventional SDRAM memory device so that the host can access data in the memory.

Abstract: In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).

Abstract: To provide a signal processing section of a software radio device or the like which can dynamically change connection itself of an internal function structure at the time of execution. A switching module ISM1(2) or the like selects and uses one of the plurality of the routing tables (60) or the like prepared according to the signal processing and executes routing control to respective processing modules a11 or the like based on the input data packet. The processing module a11 or the like executes each processing by using a parameter table or the like indicating the processing to be performed in accordance with the data packet.

Abstract: A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

Abstract: This invention discloses a method for executing vertex shader in a computer system, the method comprising running software vertex shader for a predetermined vertex shader command in a CPU thread when a GPU is overloaded by vertex shader execution, buffering the output of the software vertex shader, running hardware vertex shader for z-values of the vertex shader command, and replacing z-values from the software vertex shader with the z-values from the hardware vertex shader, wherein the vertex shader overloading can be lessoned yet the vertex shader z-values are consistently transformed by the hardware vertex shader.

Abstract: A computer configured for a connection to a network of computers including the Internet, comprising: a microchip including a microprocessor including a master control unit configured using hardware and firmware, and two processing units; an internal hardware firewall that is located between a protected portion and an unprotected portion of the microchip; said protected portion including said master control unit and one of the processing units, said unprotected portion including one or more of the processing units that are separate from and located outside of the internal hardware firewall; said hardware firewall denying access to said protected portion by the network; and said hardware firewall permitting access by another computer in the network to one or more of the processing units included in the unprotected portion for an operation with said another computer in the network; and an active configuration of a circuit integrated into the microchip.

Abstract: Methods, systems, and products are disclosed for chaining DMA data transfer operations for compute nodes in a parallel computer that include: receiving, by an origin DMA engine on an origin node in an origin injection FIFO buffer for the origin DMA engine, a RGET data descriptor specifying a DMA transfer operation data descriptor on the origin node and a second RGET data descriptor on the origin node, the second RGET data descriptor specifying a target RGET data descriptor on the target node, the target RGET data descriptor specifying an additional DMA transfer operation data descriptor on the origin node; creating, by the origin DMA engine, an RGET packet in dependence upon the RGET data descriptor, the RGET packet containing the DMA transfer operation data descriptor and the second RGET data descriptor; and transferring, by the origin DMA engine to a target DMA engine on the target node, the RGET packet.

Abstract: A method is described that involves determining that software state information of program code is to be made visible to a monitoring system. The method also involves initiating the writing of the software state information into a register. The method also involves waiting for the software state information to be placed onto a link within a link based computing system.

Abstract: According to an aspect of an embodiment, an apparatus has a pair of first system boards, each of the first system boards including a processor and being adapted for sending duplicate requests, in parallel, respectively, a second system board including a processor and being adapted for sending requests, a first transfer device for transferring requests, having a first arbiter for selecting and outputting one of the duplicate requests sent from each of the first system boards, and a second arbiter for selecting and outputting one of the requests sent from the second system board and a second transfer device for transferring requests, having a third arbiter for selecting one of the duplicate requests sent from each of the first system boards and outputting the selected request in synchronization with the selected request outputted by the first arbiter, the second transfer device having a forth arbiter.

Abstract: A high performance sequencer/synchronizer controls multiple concurrent data processors and dedicated coprocessors and their interaction with multiple shared memories. This sequencer/synchronizer controls multi-threading access to shared memory.

Abstract: A processing apparatus comprises a plurality of processors (12), each arranged to perform an instruction, and a bus (20) arranged to carry data and control tokens between the processors. Each processor (12) is arranged, if it receives a control token via the bus, to carry out the instruction, and on carrying out the instruction, to perform an operation on the data, to identify any of the processors (12) which are to be data target processors, and to transmit output data to any identified data target processors, to identify any of the processors which are to be control target processors, and to transmit a control token to any identified control target processors.

Abstract: In some embodiments, the invention involves efficiently boot and resume a machine from a low power state. In at least one embodiment, the present invention saves the processor state(s) in a buffer that allows fast access upon a resume from sleep mode. When a sleep (S3 mode) is initiated in a platform, processor state context is saved in a system reserved buffer that does not allow access to the operating system. The firmware (EFI) has access to the buffer and upon a resume, the processor context(s) are restored from a fast buffer. Other embodiments are described and claimed.

Abstract: Power management methods and systems. First, a running cycle of a processing unit processing a data unit is recorded. A gating signal is generated according to the running cycle and a performance requirement, and a working clock is adjusted according to the gating signal. Thereafter, the adjusted working signal is provided to the processing unit.

Abstract: A method of reducing power consumption of a computing system by a predetermined amount comprises: selecting at least one memory component of the computer system for reduced power consumption based on the predetermined amount of power consumption reduction; and evacuating the selected at least one memory component to reduce the power consumption of the computing system by at least the predetermined amount.

Abstract: Systems and methods of managing workloads provide for detecting a workload for a system having a first processor core with a first performance indicator and a second processor core with a second performance indicator. The workload is scheduled based on the first and second performance indicator settings. In one embodiment, a performance feasibility index is calculated for each core based on the core's frequency setting and utilization and the workload is assigned to the core associated with the highest index.

Abstract: A method for inserting an object into a concurrent set including obtaining a key associated with the object, traversing the concurrent set using a first thread containing the key, identifying a first insertion point while traversing the concurrent set, where the first insertion point is before a current node and after a predecessor node, obtaining a first lock for the predecessor node after identifying the first insertion point, validating the predecessor node and the current node after obtaining the lock, inserting a new node into the concurrent set after validating, where the new node is associated with the object, and releasing the first lock after inserting the new node.

Abstract: A system, apparatus, and method for a core rationing logic to enable cores of a multi-core processor to adhere to various power and thermal constraints.

Abstract: A computer system includes multiple caches and a cache line state directory structure, having at least a portion dedicated to a particular device cache within a particular device, and contains a fixed number of entries having a one-to-one correspondence to the cache lines of the cache to which it corresponds. The cache line state directory is used to determine whether it is necessary to send an invalidation message to the device cache. In the preferred embodiment, a dedicated portion of the cache line state directory structure corresponds to an I/O bridge device cache. Preferably, the cache line state directory also maintains state for one or more processor caches in a different format. The computer system preferably uses a NUMA architecture, the directories being maintained by node servers in each node.

Abstract: Distant parallelization of sequential programs is obtained by making parallelization decisions at the boundaries between program methods (e.g., functions and sub-routines). Experimentation suggests that such a partitioning allows for large-scale parallelization without data flow conflicts.

Abstract: Resources may be dynamically allocated in a distributed processing portable electronic communication device. The dynamic allocation may include receiving an instruction to process an audio processing task related to audio data; determining whether resources for processing the processing task are available at a first processing unit; performing the audio processing task by the first processing unit when the resources are determined to be available, the audio processing task obtaining processed audio data; and providing the processed audio data synchronously with a global synchronization pulse so that the phase of the audio data is controlled.

Abstract: A mechanism for performing dynamic request routing based on broadcast source request information is provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide source request information to each of the other processor chips in the system. The source request information identifies the number of active source requests sent by the processor chip that originated the heartbeat signal. The source request information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data.

Abstract: A signal intelligence system comprising a plurality of software components that are programmable to provide a signal intelligence function. The signal intelligence system includes a processor system having a plurality of interconnected processor devices and a plurality of processor managers that are connected to the processor devices and are configured to control software components associated with the processor devices. Further, the signal intelligence system has a framework manager that is configured to interact with the plurality of processor managers to control the processor devices and effectuate the signal intelligence function.

Abstract: A method, computer program product, and system for segmenting a software application program into a set of separately executable images. The method including segmenting program binary images of the application program into sub-execution units to be distributed to run in each device of a team as part of a single event-driven runtime process with a single main program linear contiguous code address space and a single main program linear contiguous data address space. The program sub-execution units containing executable code, and data; and each sub-execution unit containing one linear contiguous address space subset segment of the main program code, and one linear contiguous address space subset segment of the main program data; and running a unification engine on each said device of said team of devices to synchronize and serialize events as needed across the formed team of devices that drive said single event-driven runtime process.

Abstract: A multiple computer environment is disclosed in which an application program executes simultaneously on a plurality of computers (M1, M2, . . . Mn) interconnected by a communications network (53) and in which the local memory of each computer is maintained substantially the same by updating in due course. A lock mechanism is provided to permit exclusive access to an asset, object, or structure (ie memory location) by acquisition and release of the lock. In particular, before a new lock can be acquired by any other computer on a memory location previously locked by one computer, any re-written content(s) for the previously locked memory location are transmitted to all the other computers and their corresponding memory locations (before the in due course updating). Thus when the new lock is acquired all the corresponding memory locations of all computers have been updated.

Abstract: In one embodiment of the present invention, a method includes verifying an initiating logical processor of a system; validating a trusted agent with the initiating logical processor if the initiating logical processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.

Abstract: A computing device is booted in a manner that enables a software application to begin execution with minimal delay. When the device is powered up, a first processor begins booting under control of a first operating system, and a second processor begins booting under control of a second operating system. The first operating system is of a type that generally takes longer to complete booting than the second operating system. As soon as the second processor has booted up, it begins controlling execution of a software application. Then, when the first processor has booted up, control over the software application is transferred from the second processor to the first processor.

Abstract: This invention relates to multi-core, multi-processing, factory multi-core and DSP multi-core. The nature of the invention is related to more optimal uses of a multi-core system to maximize utilization of the processor cores and minimize power use. The novel and inventive steps are focused on use of interrupts and prioritized interrupts, along with optional in-built methods, to allow systems to run more efficiently and with less effort on the part of the programmer.

Abstract: A compiler for a heterogeneous system that includes both one or more primary processors and one or more parallel co-processors is presented. For at least one embodiment, the primary processors(s) include a CPU and the parallel co-processor(s) include a GPU. Source code for the heterogeneous system may include code to be performed on the CPU but also code segments, referred to as “foreign macro-instructions”, that are to be performed on the GPU. An optimizing compiler for the heterogeneous system comprehends the architecture of both processors, and generates an optimized fat binary that includes machine code instructions for both the primary processor(s) and the co-processor(s). The optimizing compiler compiles the foreign macro-instructions as if they were predefined functions of the CPU, rather than as remote procedure calls.

Abstract: A storage system is comprised of an interface unit 10 which has an interface with a server 3 or hard drives 2, a memory unit 21 which has a cache memory module 126 for storing data to be read from/written to the server 3 or the hard drives 2 and a control information memory module 127 for storing control information of the system, a processor unit 81 which has a microprocessor for controlling the read/write of data between the server 3 and the hard drives 2, and an interconnection 31, wherein the interface unit 10, memory unit 21 and processor unit 81 are interconnected with the interconnection 31.

Abstract: A method of providing physics data within a game program or simulation using a hardware-based physics processing unit having unique architecture designed to efficiently calculate physics related data.

Abstract: In a data processing system, a plurality of agents communicate operations therebetween. Each operation includes a request and a combined response representing a system-wide response to the request. Within data storage in the data processing system, a data structure indicates a duration of a protection window extension for each of the plurality of agents. Each protection window extension is a period following receipt of a combined response during which an associated one of the plurality of agents protects transfer of coherency ownership of a data granule between agents. Each of the plurality of agents is configured with a duration of a protection window extension by reference to the data structure, and at least two of the agents have protection window extensions of differing durations. The plurality of agents thereafter employ the configured protection window extensions.

Abstract: An apparatus and program product for transferring entitlement to standby resources between respective computers. Standby resources are made available at a destination computer by rendering unavailable corresponding resources at a source computer. As such, the aggregate number of available standby resources may remain unchanged, but the distribution of the availability may be reapportioned according to operational requirements. Where desired, this transfer of entitlement may be accomplished automatically, dynamically and/or in a secure manner.

Abstract: In a multi-core stream processing system and scheduling method of the same, a scheduler is coupled to a number (N) of stream processing units and a number (N+1) of stream fetching units, where N?2. When the scheduler receives a stream element from a Pth stream fetching unit, the scheduler assigns a Pth stream processing unit as a target stream processing unit when the Pth stream processing unit does not encounter a bottleneck condition, assigns a Qth stream processing unit, which does not encounter the bottleneck condition, as the target stream processing unit when the Pth stream processing unit encounters the bottleneck condition, where 1?P?N, 1?Q?N, and P?Q, and dispatches the received stream element to the target stream processing unit such that the target stream processing unit processes the stream element dispatched from the scheduler.

Abstract: There is provided, in a parallel pipelined structure on a multi-core device, a method for parallel pipelined multi-core indexing. The method includes generating one or more single document indexes respectively corresponding to one or more single documents of a given data stream. The method further includes generating one or more multi-document interval-based hash tables from the one or more single document indexes. The method also includes generating a global hash table formed from merging one or more of the multi-document interval-based hash tables, the global hash table representing a collective index for all of the single documents for which the one or more single document indexes were generated.

Abstract: In at least some embodiments, a system, comprises a first computing unit having a first type of processors. The system further comprises a second computing unit having a second type of processors, the second computing unit being coupled to the first computing unit. The first and second computing units are configured to provide parallel processing of an application based on an algorithm that distributes work evenly to a plurality of threads. The number of the threads assigned to each of the first and second computing units is based on a number of processors associated with each of the first and second computing units and a per-processor performance of the first and second computing units.

Abstract: An information processor controls accesses to a cache memory from application software programs differing in range of addresses, accesses to which are authorized. The cache memory blocks an access to an unauthorized address. In the information processor, an ID is assigned to each application software program, and the tag field of the cache memory is extended. Further, in performing “Cache Fill” (i.e. reading main memory data into the cache memory), the ID is recorded. At the time of making a cache hit judgment, the access control is performed by comparing the extended tag field with ID of an application software program group of an access requester.

Abstract: A computing device is booted in a manner that enables a software application to begin execution with minimal delay. When the device is powered up, a first processor system begins booting under control of a first operating system, and a second processor system begins booting under control of a second operating system. The first operating system is of a type that generally takes longer to complete booting than the second operating system. As soon as the second processor system has booted up, it begins controlling execution of a software application. Then, when the first processor system has booted up, control over the software application is transferred from the second processor system to the first processor system.

Abstract: One embodiment of the invention provides a processor. The processor generally includes a first and second processor core, each having a plurality of pipelined execution units for executing an issue group of multiple instructions and scheduling logic configured to issue a first issue group of instructions to the first processor core for execution and a second issue group of instructions to the second processor core for execution when the processor is in a first mode of operation and configured to issue one or more vector instructions for concurrent execution on the first and second processor cores when the processor is in a second mode of operation.