Abstract: Sequences of items may be maintained using ordered locks. These items may correspond to anything, but using ordered locks to maintain sequences of packets, especially for maintaining requisite packet orderings when distributing packets to be processed to different packet processing engines, may be particularly useful. For example, in response to a particular packet processing engine completing processing of a particular packet, a gather instruction is attached to the particular identifier of a particular ordered lock associated with the particular packet. If no longer needed for further processing, the packet processing engine is immediately released to be able to process another packet or perform another function. The gather instruction is performed in response to the particular ordered lock being acquired by the particular identifier, with the gather instruction causing the processed particular packet to be sent.

Abstract: The invention relates to an audio processing system 1. In order to improve the audio processing, the system comprises at least one audio processing component 11, 12, 13 with a group of real-time functions 14 for processing audio data and a group of control functions 15 for processing control signals. The system further comprises at least one processor 16 providing a first process 20 for executing real-time functions 14 of the at least one audio processing component 11, 12, 13 using a basically constant processing power and at least one further process 30 for executing control functions 15 of the at least one audio processing component 11, 12, 13 when needed without affecting the processing power employed for the first process 20. The invention relates equally to a corresponding method and to a corresponding software program product.

Abstract: A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

Abstract: Methods, signals, devices and systems are provided for matching tasks with processing units. A region within a multi-faceted task space is allocated to a processing unit. A point in the multi-faceted task space is assigned to a task. The task is then associated with the processing unit if the region allocated to the processing unit is close to the point assigned to the task. The region allocated to a processing unit may be changed. If no assigned point for a task is sufficiently close to any allocated processing unit region, the task is suspended. Overlapping regions may be assigned to different processing units. In some implementations, the union of the allocated regions covers the task space, while in others it does not. Regions may also be allocated to wait conditions and one or more dimensions of a region may be allocated to conventional processor allocators.

Abstract: An improved method and system for complex and integrated application performance management which tracks end-to-end computer resource consumption of a first business application workflow in an enterprise system. The first business application workflow may include a plurality of components. The plurality of components may further include one or more component types. A second or subsequent business application workflow may be embedded or linked as a component of the first business application workflow. Resource usage information of the plurality of components (including resource usage information of underlying units of work of the plurality of components) may be correlated to determine cumulative resource usage information for the first business application workflow. The resource usage information may be displayed in a graphical user interface.

Abstract: The present invention is an integral parallel machine for performing intensive computations. By combining data parallelism, time parallelism and speculative parallelism where data parallelism and time parallelism are segregated, efficient computations can be performed. Specifically, for sequential functions, the time parallel system in conjunction with an implementation for speculative parallelism is able to handle the sequential computations in a parallel manner. Each processing element in the time parallel system is able to perform a function and receives data from a prior processing element in the pipeline. Thus, after a latency period for filling the pipeline, a result is produced after clock cycle or other desired time period.

Abstract: There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address,(ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.

Abstract: The data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one application, a data processing system includes first and second processing books, each including at least first and second processing units. Each of the first and second processing units has a respective first output data bus. The first output data bus of the first processing unit is coupled to the second processing unit, and the first output data bus of the second processing unit is coupled to the first processing unit. At least the first processing unit of the first processing book and the second processing unit of the second processing book each have a respective second output data bus.

Abstract: A method for communicating in a multi-processor environment is provided that includes generating a bit at an originating processor associated with a message to be communicated to a destination processor. The bit is positioned in a send register associated with the originating processor and transposed from the send register of the originating processor to a receive register of the destination processor. An interrupt signal is then generated in response to the bit being transposed.

Abstract: A method for prototyping an integrated circuit may include selecting at least one daughter card for connection to a motherboard. The daughter card is selected having an ability to provide functionality corresponding to a specific integrated circuit device. The at least one daughter card is connected to the motherboard so that the daughter card is communicatively connected to common memory provided on the motherboard. The at least one daughter card and motherboard emulate an integrated circuit design. At least one of software and system integration of the integrated circuit emulated by the motherboard and the at least one daughter card is tested.

Abstract: A computer system includes a plurality of nodes coupled together wherein each node may comprise a processor and memory. The system may also include a plurality of software objects usable by any of the nodes. Each object may be provided to, and stored in, the memory of the node that most frequently uses the object.

Abstract: Herein disclosed is a digital signal processing apparatus comprising: input means for inputting a plurality of acoustic signals from an external outputting device; a plurality of digital signal processing units electrically connected with one another in series to form a closed loop, for receiving and processing said acoustic signals as shared data elements in a sequential order; and output means for outputting a plurality of acoustic data elements processed and generated by said digital signal processing units to an external inputting device, whereby each of said digital signal processing units comprises: receiving means for receiving said shared data elements from a preceding digital signal processing unit; copied data storing means for copying said shared data elements to a shared memory section; acoustic signal processing means for inputting said shared data elements stored in said shared memory section as an input signal, processing said shared data elements thus inputted, and writing an output signal int

Abstract: A method and system are disclosed for managing saved process states in a memory of a data processing system that has multiple partitions executing independent operating systems. A hypervisor manager affords access to any processor in the data processing system for the purpose of storing process states for that processor to the memory, independent of the operating system running on the processor.

Abstract: A coprocessor instruction interface is described which provides a flexible degree of coupling with a host control processor. Specific methods are defined for architectures to make use of multiple coprocessing instruction interfaces with a single coprocessor for supporting client-server coprocessors (CSCOPs). A dynamic debug interface is used in each coprocessor instruction interface to support tightly coupled, loosely coupled and firmly coupled operation of the single conprocessor for a corresponding coupled control processor.

Abstract: A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plurality of processing units includes interconnect logic, coupled to each point-to-point communication link of that processing unit, that broadcasts requests received from one of the multiple others of the plurality of processing units to one or more of the plurality of processing units. The interconnect logic includes a partial response data structure including a plurality of entries each associating a partial response field with a plurality of flags respectively associated with each processing unit containing a snooper from which that processing unit will receive a partial response.

Abstract: Apparatus, methods, data structures, and systems are provided for subdividing input data associated with a first software program into job quanta, wherein each job quantum is operable to be executed by a separate software program residing on a different processing element from the first software program. The first software program and the separate software program execute substantially in parallel and output data associated with the executions of the programs are assembled into a single coherent presentation or results data. Moreover, the software programs may be threaded or non-threaded.

Abstract: A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure includes routers in service or compute processor boards distributed in an array of cabinets connected in series on each board and to respective routers in neighboring row cabinet boards with the routers in series connection coupled to routers in series connection in respective neighboring column cabinet boards. The array can include disconnect cabinets or respective routers in all boards in each cabinet connected in a toroid. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.

Abstract: A method and apparatus are provided for implementing frame header alterations on multiple concurrent frames. Each of a plurality of frame data alteration engines includes a pair of a command decoder and an associated data aligner. A command buffer arbiter sequentially receives frame alteration commands and sequentially selects one of the frame data alteration engines for the sequentially received frame alteration commands. Each command decoder receives and decodes frame alteration commands and provides frame alignment commands and alteration instructions and each associated data aligner receives frame data and selectively latches data bytes of the received frame data responsive to the frame alignment commands and sequentially provides an aligned frame data output of a predefined number of bytes.

Abstract: A method of setting a parameter of a peripheral device, for controlling an operation of the peripheral device includes collecting and storing a command issued for the peripheral device by an external device, analyzing a command issue pattern for the peripheral device based on the stored command, and determining a most proper value of the parameter based on the command issue pattern. The most proper value of the parameter determined is set as a parameter for controlling the operation of the peripheral device.

Abstract: A multi-processor unit includes a first domain for processing data according to first configuration information and having multiple first domain processors each connected to communication apparatus and each performing a different function of the first processing. The first domain processors include a first domain control processor for controlling the first processing of the first domain. The multi-processor unit also includes a second domain for second processing of the first processed data depending on a second domain configuration and having multiple second domain processors each connected to the communication apparatus and each performing a different function of the second processing. The second domain processors include a second domain control processor for controlling the second processing of the second domain.

Abstract: A multiprocessor data processing system includes a plurality of processors coupled to an interconnect and to a global promotion facility containing at least one promotion bit field. A first processor executes a high speed instruction sequence including a load-type instruction to acquire a promotion bit field within the global promotion facility exclusive of at least a second processor. The request may be made visible to all processors coupled to the interconnect. In response to execution of the load-type instruction, a register of the first processor receives a register bit field indicating whether or not the promotion bit field was acquired by execution of the load-type instruction. While the first processor holds the promotion bit field exclusive of the second processor, the second processor is permitted to initiate a request on the interconnect.

Abstract: A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory connected to the processing elements. The processing elements transfer data to and from the memory at the memory address. The memory interface can connect to a host configured to access data in a conventional SDRAM memory device so that the host can access data in the memory.

Abstract: A system for automating an operating parameter list process includes a web-based interface for accessing OPL data. Databases are provided for storing updated OPL parameter values for use in resolving the OPL process with respect to a particular operation cycle. The OPL data is provided in a format that is accessed and modified by various parties, with updates and notifications provided accordingly. Access to past OPL cycles is also provided.

Abstract: Comprising a data reader 31 for reading digital camera image data, a means 32 for setting, for example, the number of prints, a plurality of printers 33, a printer selector 34 for selecting which of the plurality of printers to use, and a controller 35 for sending a specific control signal to the printer selector 34 and image data to a specific printer 33 based on the information set by the setting means 32, each printer 33 is provided with an image processing circuit 36 for processing the read image data.

Abstract: A computer system includes a system memory, a processor and a peripheral. The peripheral includes a peripheral memory, a circuit, a first interface to receive a packet and a second interface that is adapted to communicate with the system memory. The peripheral memory is adapted to store a table that includes entries that identify different packet flows. The circuit is adapted to use the table to associate the packet with one of the packet flows and based on the association, interact with the second interface to selectively transfer a portion of the packet to the system memory for processing by the processor.

Abstract: A method for enabling access to a resource shared by at least two processors over a bus that supports an atomic instruction, wherein a first processor does not support the atomic instruction, the method comprising the steps of providing an atomic instruction emulator coupled to the bus, the atomic instruction emulator including at least two register sets for implementing an atomic instruction; receiving by the emulator over the bus an emulation request from the first processor to perform the atomic instruction on the shared resource, the request including an address location; and performing by the emulator the atomic instruction for the processor using the data and the address location from the request.

Abstract: A method, apparatus, and computer instructions for broadcasting information. A change in data used by a number of processors in the data processing system is identified. A message is sent to the number of processors in the data processing system in which the message is sent with a priority level equal to a set of routines that use the data in response to identifying the change. This message is responded to only when the recipient is at an interrupt priority less favored than the priority of the message. A flag is set for each of the number of processors to form a plurality of set flags for the message in which the plurality of set flags are located in memory locations used by the number of processors in which the plurality of set flags remains set until a response is made to the message.

Abstract: Methods and systems are provided for reconciling any changes that have occurred in two file trees since they were last synchronized. A reconciler takes as input two logs of the changes made in the respective file trees. The first log resides on a client computing device, and the second log resides on a server computing device. The reconciler outputs two sets of changes that need to be applied to the respective file trees in order to synchronize them. The reconciler detects and outputs a list of changes that conflict with each other.

Abstract: Systems and methods for balancing a load among multiple graphics processors that render different portions of a frame. A display area is partitioned into portions for each of two (or more) graphics processors. The graphics processors render their respective portions of a frame and return feedback data indicating completion of the rendering. Based on the feedback data, an imbalance can be detected between respective loads of two of the graphics processors. In the event that an imbalance exists, the display area is re-partitioned to increase a size of the portion assigned to the less heavily loaded processor and to decrease a size of the portion assigned to the more heavily loaded processor.

Abstract: A method and system transfers data between intra-node firmware and inter-nodes firmware in a multi-node computer system using reduced hardware resources. A set of control codes and data transfer functions are provided to enable data communications between computer nodes and inter-nodes controller through a one-byte control module and a one-byte data module.

Abstract: A static schedule is selected from a set of static schedules for an application dependent on the state of the application. A scheduling system stores a set of pre-defined static schedules for each state of the application. A scheduling system learns the costs of predefined schedules for each state of the application on-line as the application executes. Upon the detection of a state change in the application during run-time, the scheduling system selects a new static schedule for the application. The new static schedule is determined based on schedule costs and exploration criteria.

Abstract: A protection CMTS is available to immediately service a cable modem should that modem's service from a working CMTS fail for any reason. To speed the service transfer (cutover) from the working CMTS to the protection CMTS, the cable modem may preregister with the protection CMTS well before the cutover becomes necessary. The cable modem's registration with both the working CMTS and the protection CMTS preferably employs a single IP address, so that the cable modem need not obtain a new IP address during cutover. While the cable modem may register with both the working CMTS and the protection CMTS, the devices are designed or configured so that only the working CMTS injects a host route for the cable modem into the appropriate routing protocol. Only after cutover to the protection CMTS does the protection CMTS inject its host route.

Abstract: The invention comprises a modem apparatus adapted to provide full messaging and communications interface between a control device and a communications medium such as a telephone line. The modem can comprise an interface adapted to communicate directly with a control system device, such as a programmable logic controller (PLC), using a communications protocol compatible with the normal network communications used in a distributed control system. The apparatus advantageously interfaces directly with unmodified control system devices, providing the ability to send and receive messages from remote devices or personnel via a communications medium. The invention also comprises a control system including a modem device providing full communications between a control device and remote personnel and/or devices.

Abstract: A distributed system is provided for apportioning an instruction stream into multiple segments for processing in multiple parallel processing units, and for merging the processed segments into a single processed instruction stream having the same sequential relative order as the original instruction stream. Tags may be attached to each segment after apportioning to indicate the order in which the various segments are to be merged. In one embodiment, the end of each segment includes a tag indicating the unit to which the next instruction in the original instruction sequence is directed.

Abstract: A dedicated processor for efficient processing of documents encoded in a markup language, such as XML. The dedicated processor is capable of performing traditional parsing, transformation and manipulation processes on the document. The special purpose processor frees a general purpose processor to perform other tasks, resulting in an increase in system performance. In one embodiment, the dedicated processor includes a general purpose processor and suitable software which is provided in addition to the general purpose processor which has been traditionally used for processing. In such an embodiment, the dedicated processor may be implemented in a multi-processor system. In another embodiment, the dedicated processor is implemented in special purpose hardware, e.g. as an integrated circuit embodied in silicon in one or more chips. In either embodiment, the dedicated processor may be provided to offload processing locally or remotely.

Abstract: A method and an apparatus are provided for prefetching data from a system memory to a cache for a direct memory access (DMA) mechanism in a computer system. A DMA mechanism is set up for a processor. A load access pattern of the DMA mechanism is detected. At least one potential load of data is predicted based on the load access pattern. In response to the prediction, the data is prefetched from a system memory to a cache before a DMA command requests the data.

Abstract: A data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one implementation, a data processing system includes at least first through third processing units, data storage coupled to the plurality of processing units, and an interconnect fabric. The interconnect fabric includes at least a first data bus coupling the first processing unit to the second processing unit and a second data bus coupling the third processing unit to the second processing unit so that the first and third processing units can transmit data traffic to the second processing unit. The data processing system further includes a control channel coupling the first and third processing units.

Abstract: A smart camera system provides focused images to an operator at a host computer by processing digital images at the imaging location prior to sending them to the host computer. The smart camera has a resident digital signal processor for preprocessing digital images prior to transmitting the images to the host. The preprocessing includes image feature extraction and filtering, convolution and deconvolution methods, correction of parallax and perspective image error and image compression. Compression of the digital images in the smart camera at the imaging location permits the transmission of very high resolution color or high resolution grayscale images at real-time frame rates such as 30 frames per second over a high speed serial bus to a host computer or to any other node on the network, including any remote address on the Internet.

Abstract: A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a descriptor-based packet processing mechanism for use in efficiently assigning and processing packets to a plurality of processors. A plurality of descriptors associated with each packet transfer are written back to memory in order, divided into subset groups and assigned to processors, where each processor searches the assigned subset for EOP and associated SOP descriptors to process.

Abstract: A programmable graphics system and method for processing high precision graphics data represented in one or more data formats in one or more passes. Graphics program instructions executed by the system control the processing and format conversion of the data. The program instructions and the data are stored in a memory accessible by the system. Within the memory, contiguous memory entries can contain program instructions or data represented in different formats. The format used to represent a particular data element within the data, is specified in the state information maintained in the system and is used to configure format conversion units within the system. High precision data, such as floating color, is processed by the programmable graphics system and output via a digital to analog converter (DAC) for display.

Abstract: A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.

Abstract: In a display apparatus, a display instruction generating unit outputs a display instruction. A plurality of display processing units are arranged in parallel, and each of the plurality of display processing units generates display data in response to the display instruction from the display instruction generating unit. A display switching unit selects one of the plurality of display processing units and outputs the display data from the selected display processing unit to the display unit. Thus, a display unit displays the display data.

Abstract: A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing data including programming engines that support multiple contexts arranged to provide a functional pipeline by a functional pipeline control unit that passes functional data among the programming engines.

Abstract: A reconfigurable processor architecture. A reconfigurable processor is an array of a multiplicity of various functional elements, between which the interconnections may be programmably configured. The inventive processor is implemented on a single substrate as a network of clusters of elements. Each cluster includes a crossbar switching node to which a plurality of elements is connected via ports. Additional ports on the crossbar switching node connect to the switching nodes of nearest neighbor clusters. The crossbar switching nodes allow pathways to be programmably set between any of the ports, and any pathway may be set to be either registered or unregistered. The use of clusters of processing elements allows complete freedom of local connectivity for effective configuration of many different processing functions. Wide area interconnection is more restricted, but, since it is less used, does not significantly restrict configurability.

Abstract: A database management and indexing technique provides coherent access to and update of dynamic configuration information stored in a database associated with a multiprocessing environment of an aggregation router. The multiprocessing environment comprises a forwarding engine configured as a computing matrix of processors that operate on packets in a parallel as well as a pipeline fashion. A unique handle, i.e., a virtual common coherency index (VCCI) value, is associated with an interface regardless of whether it is a virtual or a physical interface. When a packet enters the computing matrix, it is classified and assigned a VCCI value based upon the interface over which it is received at or transmitted from the router. The assigned VCCI value is then passed along with the packet to each feature that processes the packet.

Abstract: A system, method, and computer program product for creating a sequence of computer graphics frames, using a plurality of rendering pipelines. For each frame, each rendering pipeline receives a subset of the total amount of graphics data for the particular frame. At the completion of a frame, each rendering pipeline sends a performance report to a performance monitor. The performance monitor determines whether or not there was a significant disparity in the time required by the respective rendering pipelines to render their tiles. If a disparity is detected, and if the disparity is determined to be greater than some threshold, an allocation module resizes the tiles for the next frame. This serves to balance the load across rendering pipelines for each frame.

Abstract: The present invention is directed to a method and a system for maintaining cache coherence in a distributed shared memory (DSM) multiprocessor system. The method begins with a receiving of a shared access request by a receiving node, where the receiving node is an arbitrary node having at least one main memory unit containing information desired to be accessed. Then, the method determines whether the shared access request originates from a local node or from a remote node. When the shared access request originates from a local node, the shared access request is processed as a shared access request. If the shared access request is granted, a sharing vector is generated or updated to reflect the sharing local node(s). When the shared access request originates from a remote node, the shared access request is converted to an exclusive access request and the sharing vector is replaced with a pointer to the requesting remote node. This limits the potential size of the sharing vector according to the local nodes.

Abstract: An order placement and acceptance system includes a first data processing device for sending a design data for processing and manufacture of a predetermined item, a second data processing device for obtaining the design data sent from the first data processing device and for sending at least a part of the design data, and a third data processing device for obtaining at least the part of the design data sent from the second data processing device.

Abstract: A protection CMTS is available to immediately service a cable modem should that modem's service from a working CMTS fail for any reason. To speed the service transfer (cutover) from the working CMTS to the protection CMTS, the cable modem may preregister with the protection CMTS well before the cutover becomes necessary. The cable modem's registration with both the working CMTS and the protection CMTS preferably employs a single IP address, so that the cable modem need not obtain a new IP address during cutover. While the cable modem may register with both the working CMTS and the protection CMTS, the devices are designed or configured so that only the working CMTS injects a host route for the cable modem into the appropriate routing protocol. Only after cutover to the protection CMTS does the protection CMTS inject its host route.

Abstract: The present invention defines a transaction management contract between an application server and a resource adapter and its underlying resource manager that allows an application server to utilize local transactions on a resource manager and avoid the overhead of an external transaction manager. The transaction management contract incorporates two aspects that apply to different types of transactions. The first aspect provides an application level transaction contract between a transaction manager and a resource manager based on javax.transaction.xa.XAResource of the J2EE specification. The second aspect is local transaction management contract. These contracts enable application server to provide the infrastructure and runtime environment for transaction management. An application component relies on this transaction infrastructure to support its component level transaction model.