Abstract: For one disclosed embodiment, a processor comprises a first processor core, a second processor core, and a cache memory. The first processor core is to save a state of the first processor core and to enter a mode in which the first processor core is powered off. The second processor core is to save a state of the second processor core and to enter a mode in which the second processor core is powered off. The cache memory is to be powered when the first processor core is powered off. The first processor core is to restore the saved state of the first processor core in response to the first processor core transitioning to a mode in which the first processor core is powered. The second processor core is to restore the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered. Other embodiments are also disclosed.

Abstract: In one embodiment, receipt of a print job at a printer is recognized. If the printer has a set of capabilities needed to meet requirements of the job, local processing is performed, and printing of the job at the printer is caused. If the printer does not have the set, and the printer and a print service available to the printer via a network together have the set, the job is sent to the service for remote processing. After the remote processing, the job is received at the printer from the service. Printing of the job, at the printer and in accordance with the requirements, is caused.

Abstract: A processor has a plurality of PEs (processing elements) that operate in parallel based on operation commands and an information collection unit that collects the data of the plurality of PEs, wherein each of the plurality of PEs holds data and a condition flag, supplies the data and the condition flag to the information collection unit upon receiving an operation command, and upon receiving an update request for updating the condition flag, updates the condition flag in accordance with the update request that was received; and the information collection unit, upon receiving the data and the condition flags, selects one PE based on a predetermined order of priority from among the PEs for which the received condition flags are active and both supplies the data of the selected PE as collection result data and supplies an update request for updating the condition flag of the PE that was selected.

Abstract: Described embodiments provide a method of coordinating debugging operations in a network processor. The network processor has one or more processing modules. A system cache of the network processor requests a data transfer between the system cache and at least one external memory. A memory interface of the network processor selects an encrypted data pipeline or a non-encrypted data pipeline based on whether the processed data transfer request includes an encrypted operation. If the data transfer request includes an encrypted operation, the memory interface provides the data transfer to the encrypted data pipeline and checks whether a debug indicator is set for the data transfer request. If the debug indicator is set, the memory interface disables encryption/decryption of the encrypted data pipeline. The data transfer request is performed by the encrypted data pipeline to the at least one external memory.

Abstract: Techniques described herein generally relate to optimizing energy consumption in a computer system. In some examples an energy usage benchmark can be determined for a system component of the computer system by measuring performance levels and energy usages of the system component under a range of energy settings and utilization rates of the system component. A utilization rate of the system component can be determined based on prediction factors including the execution of a first set of instructions on the computer system. The system component can be configured to execute a second set of instructions after the first set of instructions by selecting an energy setting from the range of energy settings for operating the system component. The energy setting can be selected based on the energy usage benchmark and the determined utilization rate.

Abstract: A micro grid bridge structure and an associated method of formation. The micro grid bridge structure includes micro grid apparatuses and at least one bridge module including two bridge units connected by a bridge hinge. Each micro grid apparatus includes a central area and radial arms defining docking bays. Each bridge unit in each bridge module is latched into a docking bay of a respective micro grid apparatus of two micro grid apparatuses to bridge the two grid apparatuses together such that each micro grid apparatus is bridged to at least one other micro grid apparatus. Each micro grid apparatus is either a power hub apparatus whose central area includes rechargeable batteries or a processor apparatus whose central area includes processors that includes a unique processor having a unique operating system differing from an operating system in each other processor.

Abstract: A processor of a data processing system executes a controlling thread of a program and detects occurrence of a particular asynchronous event during execution of the controlling thread of the program. In response to occurrence of the particular asynchronous event during execution of the controlling thread of the program, the processor initiates execution of an assist thread of the program such that the processor simultaneously executes the assist thread and controlling thread of the program.

Abstract: A distributed processing system is described that employs “application-based” specialization. In particular, the distributed processing system is constructed as a collection of computing nodes in which each computing node performs a particular processing role within the operation of the overall distributed processing system. Each of the computing nodes includes an operating system, such as the Linux operating system, and includes a plug-in software module to provide a distributed memory operating system that employs the role-based computing techniques. An administration node maintains a database that defines a plurality of application roles. Each role is associated with a software application, and specifies a set of software components necessary for execution of the software application. The administration node deploys the software components to the application nodes in accordance with the application roles associates with each of the application nodes.

Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

Abstract: A mechanism is provided for automatically tuning power proxy architectures. Based on the set of conditions related to an application being executed on a microprocessor core, a weight factor to use for each activity in a set of activities being monitored for the microprocessor core is identified, thereby forming a set of weight factors. A power usage estimate value is generated using the set of activities and the set of weight factors. A determination is made as to whether the power usage estimate value is greater than a power proxy threshold value identifying a maximum power usage for the microprocessor core. Responsive to the power usage estimate value being greater than the power proxy threshold value, a set of signals is sent to one or more on-chip actuators in the power proxy unit associated with the microprocessor core and a set of operational parameters associated with the component are adjusted.

Abstract: A multi-processor computer system is described in which transaction processing is distributed among multiple protocol engines. The system includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.

Abstract: A data processing device including a reception unit, an instruction unit and a storage unit. The reception unit receives instructions for processing at a processing execution device. The instruction unit instructs the processing execution device to cancel a power saving state of the processing execution device and execute the processing corresponding to an instruction received by the reception unit. The storage unit stores data relating to received instructions. If the processing corresponding to the received instruction is a pre-specified process, data relating to the instruction is stored by the storage unit. If the processing corresponding to the received instruction is not a pre-specified process, the instruction unit instructs the processing execution device to execute both the processing corresponding to this instruction and processing based on data relating to instructions stored in the storage unit.

Abstract: A hierarchical and distributed system architecture for a container monitoring and security system is provided. The architecture may be a hierarchical chain of separate, related processing elements. The partitioning of functions and distribution of processing among these or other similar hierarchical elements in the network is provided. The elements may further be described in successive layers, each have a greater level of network intelligence than the former.

Abstract: A method, apparatus and product useful for verifying Distributed Symmetric Multi-Processing systems (DSMPs). The method comprising: determining one or more sub-systems of a DSMP, wherein each sub-system is a Symmetric Multi-Processing System (SMP) which comprises a shared memory and a set of processing entities that have the same access permissions to the shared memory; and verifying the DSMP using a verification tool designed to verify an SMP, wherein said verifying is performed by verifying each sub-system.

Abstract: A large-scale data processing system and method for processing data in a distributed and parallel processing environment. The system includes an application-independent framework for processing data having a plurality of application-independent map modules and reduce modules. These application-independent modules use application-independent operators to automatically handle parallelization of computations across the distributed and parallel processing environment when performing user-specified data processing operations. The system also includes a plurality of user-specified, application-specific operators, for use with the application-independent framework to perform a user-specified data processing operation on a user-specified set of input files. The application-specific operators include: a map operator and a reduce operator. The map operator is applied by the application-independent map modules to input data in the user-specified set of input files to produce intermediate data values.

Abstract: Methods, apparatuses, and computer readable media are disclosed for control flow on a heterogeneous computer system. The method may include a first processor of a first type, for example a CPU, requesting a first kernel be executed on a second processor of a second type, for example a GPU, to process first work items. The method may include the GPU executing the first kernel to process the first work items. The first kernel may generate second work items. The GPU may execute a second kernel to process the generated second work items. The GPU may dispatch producer kernels when space is available in a work buffer. The GPU may dispatch consumer kernels to process work items in the work buffer when the work buffer has available work items. The GPU may be configured to determine a number of processing elements to execute the first kernel and the second kernel.

Abstract: Aspects of the present invention reduce a lock wait time in a distributed processing environment. A plurality of wait-for dependencies between a first plurality of transactions and a second plurality of transactions in a distributed processing environment is identified. The first plurality of transactions waits for the second plurality of transactions to release a plurality of locks on a plurality of shared resources. An amount of time the first plurality of transactions will wait for the second plurality of transactions in the distributed processing environment is determined based on the plurality of wait-for dependencies between the first plurality of transactions and the second plurality of transactions. Historical transaction data related to the plurality of wait-for dependencies between the first plurality of transactions and the second plurality of transactions is analyzed.

Abstract: A system includes plural processors; memory that stores a program currently under execution by the processors; and a pre-loader that pre-loads into a fragment area of the memory, a target program that is to be executed and is a program other than the program currently under execution by the processors.

Abstract: A multithreaded rendering software pipeline architecture dynamically reallocates regions of an image space to raster threads based upon performance data collected by the raster threads. The reallocation of the regions typically includes resizing the regions assigned to particular raster threads and/or reassigning regions to different raster threads to better balance the relative workloads of the raster threads.

Abstract: Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerate SBR and other audio processing. In addition to the instruction extensions, execution units (e.g., multiplication and accumulation units (MACs)) may operate in parallel to reduce the number of audio processing cycles. Performance may be further enhanced through the use of source and destination units which are configured to work with the execution units and quickly fetch and store source and destination operands.

Abstract: Direct injection of a data to be transferred in a hybrid computing environment that includes a host computer and a plurality of accelerators, the host computer and the accelerators adapted to one another for data communications by a system level message passing module. Each accelerator includes a Power Processing Element (‘PPE’) and a plurality of Synergistic Processing Elements (‘SPEs’). Direct injection includes reserving, by each SPE, a slot in a shared memory region accessible by the host computer; loading, by each SPE into local memory of the SPE, a portion of data to be transferred to the host computer; executing, by each SPE in parallel, a data processing operation on the portion of the data loaded in local memory of each SPE; and writing, by each SPE, the processed data to the SPE's reserved slot in the shared memory region accessible by the host computer.

Abstract: This invention is involving the creation of a sub-sequence net (hereafter briefly as Sub SN). The Sub SN is a kind of sequence net encapsulation that includes sub-routine structure of N+1 single machines. Based on the fact that the sequence net call instruction of sequence net call function in the environment of sequence net computers of this invention is a single machine instruction which can call the operation of a Sub SN comprising N+1 branch programs. In N+1 branch programs, the sequence net call instruction calls Sub SN devices and realizes the call of sequence net. In this invention, grade call and sequence call of sequence net are created to meet requirements of random events and ordered events of models.

Abstract: Direct injection of a data to be transferred in a hybrid computing environment that includes a host computer and a plurality of accelerators, the host computer and the accelerators adapted to one another for data communications by a system level message passing module. Each accelerator includes a Power Processing Element (‘PPE’) and a plurality of Synergistic Processing Elements (‘SPEs’). Direct injection includes reserving, by each SPE, a slot in a shared memory region accessible by the host computer; loading, by each SPE into local memory of the SPE, a portion of data to be transferred to the host computer; executing, by each SPE in parallel, a data processing operation on the portion of the data loaded in local memory of each SPE; and writing, by each SPE, the processed data to the SPE's reserved slot in the shared memory region accessible by the host computer.

Abstract: A synchronization device includes a receiver that receives data from at least two synchronization devices establishing synchronization, and extracts synchronization information and register selection information from the received data, a transmitter that transmits data to each of the at least two synchronization devices establishing synchronization among a plurality of synchronization devices, a first and a second receiving state register that each stores the extracted synchronization information, a second receiving state register that stores the extracted synchronization information, and a controller that stores the extracted synchronization information into the first receiving state register and the second receiving state register alternately based on the register selection information, and controls the transmitter to transmit data including the register selection information to each of the at least two synchronization devices when the extracted synchronization information is completed in one of the first a

Abstract: In a storage system that includes two or more file servers each including an arbitrary number of operating virtual file servers, a management server: holds a load information table regarding a load on each virtual file server for each time period and redundancy information table for the storage system; judges, with reference to the load information table and redundancy information table, whether or not the loads on the virtual file servers can be handled by a smaller number of file servers than the number of currently-operating file servers; selects, if the judgment result is positive, a power-off target file server and makes another file server fail over a virtual file server in the power-off target file server; and turns off the power-off target file server.

Abstract: In a system having a plurality of processing nodes, a control node divides a task into a plurality of sub-tasks, and assigns the sub-tasks to one or more additional processing nodes which execute the assigned sub-tasks and return the results to the control node, thereby enabling a plurality of processing nodes to efficiently and quickly perform memory initialization and test of all assigned sub-tasks.

Abstract: Various embodiments of the present invention provide systems and methods for a multi-tier data processing system. For example, a data processing system is disclosed that includes an input operable to receive data to be processed, a first data processor operable to process at least some of the data, a second data processor operable to process a portion of the data not processed by the first data processor, wherein the first data processor has a higher throughput than the second data processor, and an output operable to yield processed data from the first data processor and the second data processor.

Abstract: Embodiments of the invention intelligently associate processes with core processors in a multi-core processor. The core processors are asymmetrical in that the core processors support different features or provide different resources. The features or resources are published by the core processors or otherwise identified (e.g., via a query). Responsive to a request to execute an instruction associated with a thread, one of the core processors is selected based on the resource or feature supporting execution of the instruction. The thread is assigned to the selected core processor such that the selected core processor executes the instruction and subsequent instructions from the assigned thread. In some embodiments, the resource or feature is emulated until an activity limit is reached upon which the thread assignment occurs.

Abstract: A computer or microchip including one or more microprocessors or processing units, at least one network communication component, and an internal hardware firewall. located on a microchip and configured to separate a protected side of the computer or microchip from an unprotected side of the computer or microchip, the unprotected side being configured to connect to a network. The hardware protected side of the computer or microchip includes at least one microprocessor or processing unit. The unprotected network side of the computer or microchip is located between the internal hardware firewall and the network and includes the at least one unprotected microprocessors or processing units and network communications components. The unprotected microprocessors or processing units and network communications components are separate components and both are separate from the internal hardware firewall. The computer or microchip can be actively configured, including using microchips with field programmable gate arrays.

Abstract: A Decentralized System Services (DSS) architecture defines a framework for building fault-tolerant distributed applications across decentralized and heterogeneous systems. DSS enables “complexity through composition” by defining distributed designs as compositions of limited function and observable services which may be quickly and dynamically assembled to perform higher level functions. DSS defines a standardized interaction between distributed services using sessionless, asynchronous communications with explicit failure semantics. Accounting for latency, failure and state management all become a natural part of the design process. DSS includes a runtime implementation for managing concurrent services—the Common Concurrency Runtime (CCR), a protocol for service interactions—the Web Services Application Protocol (WSAP), and a set of required service behaviors which provide for composibility, location independence, and fault tolerance—Distributed Protocol Oriented Programming (DPOP).

Abstract: A clocking system, comprises a plurality of clocked data processing devices and a clock control circuit controlling a generation of a plurality of clock signals and an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices. A method for clocking a plurality of clocked data processing devices comprises controlling a generation of a plurality of clock signals and controlling an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices.

Abstract: Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodiment, the method comprises taking inputs from a set of receivers of the nodes, dividing the inputs from the receivers into a plurality of classes, combining the inputs of each of the classes to obtain a result, and sending said result to a set of senders of the nodes. Embodiments of the invention provide a method, system and computer program product for embedding a collective network in a parallel computer system organized as a torus network. In one embodiment, the method comprises adding to a torus network a central collective logic to route messages among at least a group of nodes in a tree structure.

Abstract: A method and system are provided in which one or more processors may be operable to generate an intermediate representation of a shader source code, wherein the intermediate representation comprises one or more whole-program data flow graph representations of the shader source code. The one or more processors may be operable to generate machine code based on the generated intermediate representation of the shader source code. The one or more whole-program data flow graph representations of the shader source code may be generated utilizing a compiler front end. The machine code may be generated utilizing a compiler back end. The generated machine code may be executable by a graphics processor. The generated machine code may be executable by a processor comprising a single-instruction multiple-data (SIMD) architecture. The generated machine code may be executable to perform coordinate and/or vertex shading of image primitives.

Abstract: A method and an apparatus are provided for combining multiple independent tile-based graphic cores. An incoming geometry stream is split into a plurality of streams and sent to respective tile based graphics processing cores. Each one generates a separate tiled geometry list as described. These may be combined into a master tiling unit or, alternatively, markers may be inserted into the tiled geometry lists which are used in the rasterization phase to switch between tiling lists from different geometry processing cores.

Abstract: Administering connection identifiers for collective operations in a parallel computer, including prior to calling a collective operation, determining, by a first compute node of a communicator to receive an instruction to execute the collective operation, whether a value stored in a global connection identifier utilization buffer exceeds a predetermined threshold; if the value stored in the global ConnID utilization buffer does not exceed the predetermined threshold: calling the collective operation with a next available ConnID including retrieving, from an element of a ConnID buffer, the next available ConnID and locking the element of the ConnID buffer from access by other compute nodes; and if the value stored in the global ConnID utilization buffer exceeds the predetermined threshold: repeatedly determining whether the value stored in the global ConnID utilization buffer exceeds the predetermined threshold until the value stored in the global ConnID utilization buffer does not exceed the predetermined thr

Abstract: Administering connection identifiers for collective operations in a parallel computer, including prior to calling a collective operation, determining, by a first compute node of a communicator to receive an instruction to execute the collective operation, whether a value stored in a global connection identifier utilization buffer exceeds a predetermined threshold; if the value stored in the global ConnID utilization buffer does not exceed the predetermined threshold: calling the collective operation with a next available ConnID including retrieving, from an element of a ConnID buffer, the next available ConnID and locking the element of the ConnID buffer from access by other compute nodes; and if the value stored in the global ConnID utilization buffer exceeds the predetermined threshold: repeatedly determining whether the value stored in the global ConnID utilization buffer exceeds the predetermined threshold until the value stored in the global ConnID utilization buffer does not exceed the predetermined thr

Abstract: A semiconductor device has reduced power consumption and processing time associated with the release of a low power consumption state set by a central processing unit thereof. The semiconductor device controls a relationship between a forcible release and reset of the low power consumption state previously set by the central processing unit. In one embodiment, a forcible release control circuit forcibly releases the supply and stop of power and clocks previously set to one or more controlled circuits, only during a period required by a signal outputted from a requesting circuit, which requesting circuit may be either internal to the device or external to the device. Once the request signal from the requesting circuit has ended, the controlled circuits and, if appropriate, the central processing unit as well, are restored to the original low power consumption state.

Abstract: In a method for the management of tasks in a decentralized data network with a plurality of nodes for carrying out the tasks, resources are distributed based on a mapping rule, in particular a hash function. A task that is to be suspended is distributed by dividing the process image of the task into segments and by distributing the segments over the nodes using the mapping rule. Thus, a distributed swap space is created so that tasks can also be carried out on nodes whose swap space is not sufficient on its own. The method can be used in embedded systems with a limited storage capacity and/or in a voltage distribution system, wherein the nodes are, for example, switching units in the voltage distribution system. The method can also be used in any other technical systems such as, for example, a power generation system, an automation system and the like.

Abstract: A processing apparatus comprises a plurality of processors (12), each arranged to perform an instruction, and a bus (20) arranged to carry data and control tokens between the processors. Each processor (12) is arranged, if it receives a control token via the bus, to carry out the instruction, and on carrying out the instruction, to perform an operation on the data, to identify any of the processors (12) which are to be data target processors, and to transmit output data to any identified data target processors, to identify any of the processors which are to be control target processors, and to transmit a control token to any identified control target processors.

Abstract: Performing a deterministic reduction operation in a parallel computer that includes compute nodes, each of which includes computer processors and a CAU (Collectives Acceleration Unit) that couples computer processors to one another for data communications, including organizing processors and a CAU into a branched tree topology in which the CAU is a root and the processors are children; receiving, from each of the processors in any order, dummy contribution data, where each processor is restricted from sending any other data to the root CAU prior to receiving an acknowledgement of receipt from the root CAU; sending, by the root CAU to the processors in the branched tree topology, in a predefined order, acknowledgements of receipt of the dummy contribution data; receiving, by the root CAU from the processors in the predefined order, the processors' contribution data to the reduction operation; and reducing, by the root CAU, the processors' contribution data.

Abstract: According to an aspect of the embodiment, a user apparatus transmits a parameter on generation of drawing data to each of drawing data generation apparatuses through a network, to assign generation processing of the drawing data to each of drawing data generation apparatuses. The user apparatus receives the drawing data generated based on the parameter by each of the plurality of drawing data generation apparatuses through the network, and displays the received drawing data. The user apparatus changes the parameter corresponding to the displayed drawing data, and displays a new drawing data corresponding to the changed parameter.

Abstract: Techniques are provided for dynamically re-ordering operation requests that have previously been submitted to a queue management unit. After the queue management unit has placed multiple requests in a queue to be executed in an order that is based on priorities that were assigned to the operations, the entity that requested the operations (the “requester”) sends one or more priority-change messages. The one or more priority-change messages include requests to perform operations that have already been queued. For at least one of the operations, the priority assigned to the operation in the subsequent request is different from the priority that was assigned to the same operation when that operation was initially queued for execution. Based on the change in priority, the operation whose priority has change is placed at a different location in the queue, relative to the other operations in the queue that were requested by the same requester.

Abstract: A tracing apparatus for tracing operational information that is output from a plurality of processing units in relation to data processing operations, the tracing apparatus comprising for each of the processing units: a counting unit configured to obtain and output a counter value for the corresponding processing unit, the counter value obtained by counting clock signals that are input to the processing unit at an operating frequency thereof; a counter value conversion unit configured to obtain and output a converted counter value for the corresponding processing unit, the converted counter value obtained by converting the counter value based on the assumption that the processing unit has a given reference operating frequency; and an adding unit configured to acquire an operational information set from the corresponding processing unit, and to add the converted counter value to the operational information set.

Abstract: A device includes a peer-to-peer group owner processor. The device also includes a memory coupled to the peer-to-peer group owner processor. At least one client associated with the device is a legacy client, and the peer-to-peer group owner processor enters a listening state after a dozing state. The device consumes less power in the listening state than in an awake state.

Abstract: A scheduler receives at least one flexible reservation request for scheduling in a computing environment comprising consumable resources. The flexible reservation request specifies a duration and at least one required resource. The consumable resources comprise at least one machine resource and at least one floating resource. The scheduler creates a flexible job for the at least one flexible reservation request and places the flexible job in a prioritized job queue for scheduling, wherein the flexible job is prioritizes relative to at least one regular job in the prioritized job queue. The scheduler adds a reservation set to a waiting state for the at least one flexible reservation request.

Abstract: An information processing device which has a plurality of process units for performing various kinds of processes includes a detecting unit that detects a processing loads of the process units; a determining unit that determines whether a total amount of the processing loads detected by the detecting unit is equal to or larger than a specific value; a designating unit that designates a process unit having a process state to be controlled, based on the processing loads of the process units detected by the detecting unit, when the determining unit determines that the total amount is equal to or larger than the specific value; a process identifying unit that identifies a process having an execution state to be controlled among processes being performed by the process unit designated by the designating unit; and a control unit that controls the execution state of the process identified by the process identifying unit.

Abstract: An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a fast-path that avoids protocol processing for most messages, greatly accelerating data transfer and offloading time-intensive processing tasks from the host CPU. The host retains a fallback processing capability for messages that do not fit fast-path criteria, with the device providing assistance such as validation even for slow-path messages, and messages being selected for either fast-path or slow-path processing. A context for a connection is defined that allows the device to move data, free of headers, directly to or from a destination or source in the host. The context can be passed back to the host for message processing by the host. The device contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU.

Abstract: A parallel processing data processing system builds at least one data structure indicating a communication schedule for a plurality of processes each having a respective one of a plurality of equal length vectors formed of multiple equal size chunks. The data processing system, based upon the at least one data structure, communicates chunks of the plurality of vectors among the plurality of processes and performs partial reduction operations on chunks in accordance with the communication schedule. The data processing system then stores a result vector representing reduction of the plurality of vectors.

Abstract: A protection CMTS is available to immediately service a cable modem should that modem's service from a working CMTS fail for any reason. To speed the service transfer (cutover) from the working CMTS to the protection CMTS, the cable modem may preregister with the protection CMTS well before the cutover becomes necessary. The cable modem's registration with both the working CMTS and the protection CMTS preferably employs a single IP address, so that the cable modem need not obtain a new IP address during cutover. While the cable modem may register with both the working CMTS and the protection CMTS, the devices are designed or configured so that only the working CMTS injects a host route for the cable modem into the appropriate routing protocol. Only after cutover to the protection CMTS does the protection CMTS inject its host route.

Abstract: A distributed computer system, as for transmitting and receiving executable multimedia applications, includes a source of a continuous data stream repetitively transfering data representing a distributed computing application and a client computer, receiving the data stream, for extracting the distributed computing application representative data from the data stream, and executing the extracted distributed computing application.