Abstract: A microprocessor integrated circuit includes first and second processors, an internal memory accessible by the first and second processors, and a bus interface unit configured to interface to a bus external to the microprocessor for providing access to a memory external to the microprocessor. The bus interface unit, external bus, and external memory are accessible by the second processor but are inaccessible by the first processor. The first processor writes debug information to the internal memory. The first processor detects an event and provides a notification of the event to the second processor. The second processor, coupled to the bus interface unit, executes microcode in response to the event notification received from the first processor. The microcode reads the debug information from the internal memory and writes the debug information to the external memory via the bus interface unit and external bus for use in debugging the second processor.

Abstract: A micro grid apparatus and associated method of formation. Multiple tiers are formed. The tiers are distributed and sequenced in a vertical direction such that each tier is at a different vertical level in the vertical direction. Each tier includes a multiplicity of complex shapes interconnected by bridge modules. Each complex shape is a physical structure having an exterior boundary. Each complex shape includes multiple docking bays such that each docking bay is configured to have a module latched therein. Each complex shape is either a power hub including rechargeable batteries or a processor hub including processors. A sensor module is latched in a sensor docking bay and an actuator module is latched in an actuator docking bay of each complex shape in one or more tiers of the multiple tiers.

Abstract: A multiprocessor computer system has a plurality of first processors having a first addressable memory space, and a plurality of second processors having a second addressable memory space. The second addressable memory space is of a different size than the first addressable memory space, and the first addressable memory space and second addressable memory space comprise a part of the same common address space.

Abstract: Dynamically managing a thread pool associated with a plurality of sub-applications. A request for at least one of the sub-applications is received. A quantity of threads currently assigned to the at least one of the sub-applications is determined. The determined quantity of threads is compared to a predefined maximum thread threshold. A thread in the thread pool is assigned to handle the received request if the determined quantity of threads is not greater than the predefined maximum thread threshold. Embodiments enable control of the quantity of threads within the thread pool assigned to each of the sub-applications. Further embodiments manage the threads for the sub-applications based on latency of the sub-applications.

Abstract: A concurrent grouping operation for execution on a multiple core processor is provided. The grouping operation is provided with a sequence or set of elements. In one phase, each worker receives a partition of a sequence of elements to be grouped. The elements of each partition are arranged into a data structure, which includes one or more keys where each key corresponds to a value list of one or more of the received elements associated with that key. In another phase, the data structures created by each worker are merged so that the keys and corresponding elements for the entire sequence of elements exist in one data structure. Recursive merging can be completed in a constant time, which is not proportional to the length of the sequence.

Abstract: An electric device is capable of operating in a normal operation mode and a power save operation mode. The electric device includes a first processor for processing information input externally in the normal operation mode, and a second processor for processing an internal operation of the electric device in the normal operation mode. The second processor consumes power smaller than that of the first processor. In the electric device, power of the first processor is restricted through a restriction process in the power save operation mode. Further, in the power save operation mode, the second processor restricts the internal operation and processes the information input externally. When the second processor detects the information input externally, power of the first processor is released through a restriction releasing process.

Abstract: Embodiments off the invention provide a mechanism for process migration on a massively parallel computer system. In particular, embodiments of the invention may be used to update process state data for a migrated compute node, such as MPI (or other communication library) state data, across a full collection of compute nodes present in a given parallel system executing a parallel task. Migrating a process form one compute node to another may be useful to address a variety of sub-optimal operating conditions. For example, one or more processes may be migrated to cure network congestion resulting from a poorly mapped task or when a compute node is predicted to experience a hardware failure.

Abstract: A cooperative data stream processing system is provided that utilizes a plurality of independent, autonomous and possibly heterogeneous sites in a cooperative arrangement to process user-defined job requests over dynamic, continuous streams of data. The sites negotiate peering relationships to share data and processing resources to handle the submitted job requests. These peering relationships can be cooperative or federated and can be expressed using common interest policies. Each site within the system runs an instance of a system architecture for processing job requests and is therefore a self-contained, fully functional instance of the cooperative data stream processing system.

Abstract: Minimizing code duplication in an unbounded transactional memory system. A computing apparatus including one or more processors in which it is possible to use a set of common mode-agnostic TM barrier sequences that runs on legacy ISA and extended ISA processors, and that employs hardware filter indicators (when available) to filter redundant applications of TM barriers, and that enables a compiled binary representation of the subject code to run correctly in any of the currently implemented set of transactional memory execution modes, including running the code outside of a transaction, and that enables the same compiled binary to continue to work with future TM implementations which may introduce as yet unknown future TM execution modes.

Abstract: A Method to redirect SRB routines from otherwise non-zIIP eligible processes on an IBM z/OS series mainframe to a zIIP eligible enclave is disclosed. This redirection is achieved by intercepting otherwise blocked operations and allowing them to complete processing without errors imposed by the zIIP processor configuration. After appropriately intercepting and redirecting these blocked operations more processing may be performed on the more financially cost effective zIIP processor by users of mainframe computing environments.

Abstract: In a computer system in which a server has, in addition to a disk used for booting, an operation transfer destination disk that has the same content as the boot disk, a method for changing the disk used by the server or another server in the computer system for booting to the operation transfer destination disk is realized by changing the content of the operation transfer destination disk to enable the OS and applications installed in the operation transfer destination disk to be booted from the destination disk and by changing the setting of a boot program of the server to enable booting from the operation transfer destination disk.

Abstract: A processor blade determines whether a selected processing task is to be off-loaded to a storage blade for processing. The selected processing task is off-loaded to the storage blade via a planar bus communication path, in response to determining that the selected processing task is to be off-loaded to the storage blade. The off-loaded selected processing task is processed in the storage blade. The storage blade communicates the results of the processing of the off-loaded selected processing task to the processor blade.

Abstract: A communication device includes a memory module that stores a plurality of applications corresponding to a plurality of uses of the communication device. A processing module executes a selected one of the plurality of applications and selects one of a plurality of power modes based on a current one of the plurality of uses of the communication device corresponding to the selected one of the plurality of applications. The processing module generates a power mode signal based on the selected one of the plurality of power modes. A power management circuit receives the power mode signal and that generates a plurality of power supply signals based on the power mode signal.

Abstract: A method and an apparatus are provided for combining multiple independent tile based graphic cores. An incoming geometry stream is split into a plurality of streams and sent to respective tile based graphics processing cores. Each one generates a separate tiled geometry lists. These may be combined into a master tiling unit or, alternatively, markers may be inserted into the tiled geometry lists which are used in the rasterization phase to switch between tiling lists from different geometry processing cores.

Abstract: In a system having a plurality of processing nodes, a control node divides a task into a plurality of sub-tasks, and assigns the sub-tasks to one or more additional processing nodes which execute the assigned sub-tasks and return the results to the control node, thereby enabling a plurality of processing nodes to efficiently and quickly perform memory initialization and test of all assigned sub-tasks.

Abstract: A packet processing system includes multiple processors and a set of code partitions that implement a feature set for packet processing. Each of the processors is capable of loading and executing one or more of the code partitions. A context manager enables packet processing operations to migrate between code partitions executing on one or more of the processors.

Abstract: A method of task assignment in a distributed processing system including a plurality of processors is proposed. The method of task assignment includes calculating utilities of tasks to be processed in execution units included in each processor and arranging the calculated results in descending order; calculating utility difference values between the execution units included in each processor and outputting a highest difference value; comparing a utility of the task with the output highest difference value; designating the task to be assigned to the execution unit having the lowest utility in a processor in which the highest difference value is generated when the utility of the task is less than or equal to the output highest difference value; repeating the calculating, comparing, and designating in the order of the arranged tasks; and assigning the tasks to the designated targets.

Abstract: A computer implemented method of monitoring the operational state of a computer, comprises running on the monitored computer a monitoring program configured to monitor a set of parameters. The set of monitored parameters comprises for example the name(s) of any process(es) running on the computer, together with i) the values of a plurality of metrics indicating the level of activity of the computer, and/or ii) time. The monitored parameters are provided by the monitoring program to another, monitoring, computer; which runs a comparison program which compares the set of monitored parameters with a predetermined model which determines whether or not the monitored computer is in a predetermined operational state defined by the model, and produces an indication of whether or not the monitored computer complies with the model.

Abstract: The distributed data handling and processing resources system of the present invention includes a) a number of data handling and processing resource nodes that collectively perform a desired data handling and processing function, each data handling and processing resource node for providing a data handling/processing subfunction; and, b) a low latency, shared bandwidth databus for interconnecting the data handling and processing resource nodes. In the least, among the data handling and processing resource nodes, is a processing unit (PU) node for providing a control and data handling/processing subfunction; and, an input/output (I/O) node for providing a data handling/processing subfunction for data collection/distribution to an external environment. The present invention preferably uses the IEEE-1394b databus due to its unique and specialized low latency, shared bandwidth characteristics.

Abstract: The invention achieves efficient execution of programs belonging to an object oriented platform independent language technology like Java, .NET in a multitasking environment by utilizing a processor, a co-processor (executing machine independent instructions) and memory that is accessed by both said processor and said co-processor. The co-processor is agnostic of format of the executables of the object oriented platform independent programs and operates on a composite data structure to execute a program. The composite data structure is a logical representation of an objected oriented platform independent computer program and includes instructions, object pointers, metadata, etc. Said composite data structure is independent of any object oriented platform independent technology like Java, .NET, etc. The co-processor relies on a native program to reduce executable file(s) of an objected oriented platform independent program to the said composite data structure.

Abstract: Methods of detecting and recovering from communication failures within an operating network switching device that is switching packets in a communication network, and associated structures. The communication failures addressed involve communications between the packet processors and a host CPU over a shared communications bus, e.g., PCI bus. The affected packet processor(s)—which may be all or a subset of the packet processors of the network switch—may be recovered without affecting hardware packet forwarding through the affected packet processors. This maximizes the up time of the network switching device. Other packet processor(s), if any, of the network switching device, which are not affected by the communication failure, may continue their normal packet forwarding, i.e., hardware forwarding that does not involve communications with the host CPU as well as forwarding or other operations that do involve communications with the host CPU.

Abstract: A distributed processing system delegates the allocation and control of computing work units to agent applications running on computing resources including multi-processor and multi-core systems. The distributed processing system includes at least one agent associated with at least one computing resource. The distributed processing system creates work units corresponding with execution phases of applications. Work units can be associated with concurrency data that specifies how applications are executed on multiple processors and/or processor cores. The agent collects information about its associated computing resources and requests work units from the server using this information and the concurrency data. An agent can monitor the performance of executing work units to better select subsequent work units. The distributed processing system may also be implemented within a single computing resource to improve processor core utilization of applications.

Abstract: A business rules application parallel processing system is provided. The system comprises at least one computer system, stored data, and an application that, when executed on the at least one computer system, extracts data from the initially stored data for processing in accordance with at least one business rule. The system also stores the data in a sequential file format as a first data set and partitions the data in the first data set in accordance with the at least one business rule to create a second data set and prepare the data in the second data set for processing. The system also partitions the data in the second data set into partition units appropriate for scaled application processing across multiple processors in the at least one computer system to create a third data set. The system also processes the data in the third data set in a parallel execution across the multiple processors and recombines the data after processing in accordance with the at least one business rule in a fourth data set.

Abstract: According to an aspect of the embodiment, a grid processing control apparatus includes a grid OS being an OS dedicated to grid computing, a general-purpose OS being an OS other than the grid OS, and an OS boot up unit selectively allowing the grid OS or the general-purpose OS to operate. The OS boot up unit allows only the grid OS to operate during grid use term when the grid OS is operated, and allows only the general-purpose OS to operate during general-purpose OS use term when the general-purpose OS is operated.

Abstract: An image display device that controls an external device and a method therefore are provided. The image display device includes an interface unit which is connected to an external device, a determining unit which determines whether another external device that has a control ownership of the external device exists, and a control unit which registers the control ownership of the external device if it is determined that the other external device does not exist. The external device is controlled by registering the control ownership.

Abstract: An image processing apparatus which applies processes to input image data is disclosed. The image processing apparatus includes a first processing section which applies processes to the image data by a specific calculating device, and a second processing section which applies processes to the image data by a general-purpose calculating program. The input image data are multilevel image data. The first processing section includes an image data binarizing unit for forming binary image data from the multilevel image data, and a multilevel image data processing section for applying a calculation process to the multilevel image data. The second processing section includes a binary image data processing section for applying a calculation process to the binary image data formed by the image data binarizing unit.

Abstract: A method and a device for controlling a computer system having at least two execution units, switchover operations being carried out between at least two operating modes, and a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode. At least one set of runtime objects is defined; at least one identifier is assigned to each runtime object of the defined set; and the identifier assigns at least the two operating modes to the runtime object.

Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

Abstract: A method accelerates access of a multi-core system to its critical resources, which includes preparing to delete a critical node in a critical resource, separating the critical node from the critical resource, and deleting the critical node if the conditions for deleting the critical node are satisfied. An apparatus includes a confirmation module for the node to be deleted and a deletion module to accelerate access of a multi-core system to its critical resources.

Abstract: A hardwired core is embedded in an integrated circuit having programmable circuitry. The hardwired core has a microprocessor; a crossbar interconnect coupled to processor local buses of the microprocessor; and a memory controller interface coupled to the crossbar interconnect. The crossbar interconnect provides pipelines for coupling the hardwired core to the programmable circuitry. The microprocessor, the crossbar interconnect, and the memory controller interface are all capable of operating at a first frequency of operation, and the memory controller interface is further capable of being set to operate at a second frequency of operation having an integer ratio with respect to the first frequency of operation. The crossbar interconnect is configured to direct transactions initiated by the microprocessor to the memory controller interface for accessing one or more memory devices coupled to the memory controller interface via a memory controller.

Abstract: A micro grid apparatus and associated method of formation. At least one tier in a printed circuit board is formed. Each tier includes complex shapes interconnected by bridge modules. Each complex shape includes a central area and at least three radial arms external to and integral with the central area. Each radial arm extends radially outward from the central area. Each pair of adjacent radial arms defines a docking bay. Each complex shape is either a power hub whose central area includes rechargeable batteries or a processor hub whose central area includes processors. A bridge unit of a bridge module is latched in at least one docking bay of each complex shape. Each docking bay not latching a bridge unit of any bridge module latches an irregular shaped module. An irregular shaped module is latched in at least one docking bay in at least two complex shapes.

Abstract: A processor comprising groups of plural processor elements and corresponding data registers. When a first operating mode is selected, distinct data to be calculated is written to the data registers of the groups. The same data is written to the data registers of at least two groups when a second mode is selected. Calculation results from the groups are selectively outputted, and comparison between two groups outputs is made. Selection and comparison of calculation results are carried out when the first and second modes are set, respectively. Calculation results are outputted when they agree with each other; otherwise an error is produced.

Abstract: A portable data storage device compatible with both standard and high definition digital video cameras is provided. The device includes at least one SDI I/O, and preferably at least one audio I/O and preferably at least one medium speed I/O interface. A device controller takes the high speed serial data, packetizes it, and then sends it out to a plurality of memory modules. Preferably each memory module includes four NAND clusters, each NAND cluster consisting of a flash memory controller and two NAND flash memories. Interposed between the device controller and the memory modules are a plurality of memory controllers, each memory controller controlling a group of memory modules. A user interface is coupled to the device controller, the interface including a display capable of at least two user-selectable orientations, record/playback controls and a four-way directional control pad.

Abstract: A dynamic reconfigurable circuit includes multiple clusters each including a group of reconfigurable processing elements. The dynamic reconfigurable circuit is capable of dynamically changing a configuration of the clusters according to a context including a description of processing of the processing elements and of connection between the processing elements. A first cluster among the clusters includes a signal generating circuit that when an instruction to change the context is received, generates a report signal indicative of the instruction to change the context; a signal adding circuit that adds the report signal generated by the signal generating circuit to output data that is to be transmitted from the first cluster to a second cluster; and a data clearing circuit that, when output data to which a report signal generated by the second cluster is added is received, performs a clearing process of clearing the output data received.

Abstract: In an embodiment, the present invention discloses a flexible and reconfigurable architecture with efficient memory data management, together with efficient data transfer and relieving data transfer congestion in an integrated circuit. In an embodiment, the output of a first functional component is stored to an input memory of a next functional component. Thus when the first functional component completes its processing, its output is ready to be accessed as input to the next functional component. In an embodiment, the memory device further comprises a partition mechanism for simultaneously accepting output writing from the first functional component and accepting input reading from the second functional component. In another embodiment, the present integrated circuit comprises at least two functional components and at least two memory devices, together with a controller for switching the connections between the functional components and the memory devices.

Abstract: In a method and system for collecting event information, XML documents specifying event parsing logic for respective groups of related events are loaded. Representations for the parsing logic contained in the plurality of XML documents are stored in one or more parsing trees. Events are received, including events in a plurality of groups of events. The received events are processed in accordance with the event parsing logic in the one or more parsing trees. The received events are also processed in accordance with stored program instructions that are independent of the parsing logic for the plurality of groups of events. Event information for the received events is stored. The stored event information includes information determined in accordance with the event parsing logic in at least one or more parsing trees.

Abstract: A distributed processing system is described that employs “application-based” specialization. In particular, the distributed processing system is constructed as a collection of computing nodes in which each computing node performs a particular processing role within the operation of the overall distributed processing system. Each of the computing nodes includes an operating system, such as the Linux operating system, and includes a plug-in software module to provide a distributed memory operating system that employs the role-based computing techniques. An administration node maintains a database that defines a plurality of application roles. Each role is associated with a software application, and specifies a set of software components necessary for execution of the software application. The administration node deploys the software components to the application nodes in accordance with the application roles associates with each of the application nodes.

Abstract: The present invention provides for systems and methods of dynamically controlling a cluster or grid environment. The method comprises attaching a trigger to an object and firing the trigger based on a trigger attribute. The cluster environment is modified by actions initiated when the trigger is fired. Each trigger has trigger attributes that govern when it is fired and actions it will take. The use of triggers enables a cluster environment to dynamically be modified with arbitrary actions to accommodate needs of arbitrary objects. Example objects include a compute node, compute resources, a cluster, groups of users, user credentials, jobs, resources managers, peer services and the like.

Abstract: The present invention extends to methods, systems, and computer program products for performing computations in a distributed infrastructure. Embodiments of the invention include a general purpose distributed computation infrastructure that can be used to perform efficient (in-memory), scalable, failure-resilient, atomic, flow-controlled, long-running state-less and state-full distributed computations. Guarantees provided by a distributed computation infrastructure can build upon existent guarantees of an underlying distributed fabric in order to hide the complexities of fault-tolerance, enable large scale highly available processing, allow for efficient resource utilization, and facilitate generic development of stateful and stateless computations. A distributed computation infrastructure can also provide a substrate on which existent distributed computation models can be enhanced to become failure-resilient.

Abstract: A data allocation control program manages data allocation when data is distributively stored in a plurality of disk nodes that are shifted to a power saving mode unless access is performed for a certain time. The program produces a plurality of allocation pattern candidates each indicating the disk nodes in which the respective data are to be stored. The program calculates a no-access period expectation that represents an expected value of occurrence of a no-access period during which access is not performed to some of the disk nodes. The program selects as an allocation pattern for data reallocation, one of the plurality of produced allocation pattern candidates with the largest calculated no-access period expectation. The program instructs the disk nodes to reallocate the respective data in accordance with the selected allocation pattern.

Abstract: A system and method of parallelizing programs assigns write tokens and read tokens to data objects accessed by computational operations. During run time, the write sets and read sets for computational operations are resolved and the computational operations executed only after they have obtained the necessary tokens for data objects corresponding to the resolved write and read sets. A data object may have unlimited read tokens but only a single write token and the write token may be released only if no read tokens are outstanding. Data objects provide a wait list which serves as an ordered queue for computational operations waiting for tokens.

Abstract: Provided is a semiconductor apparatus including a power management integrated circuit. The semiconductor apparatus includes an application processor and a voltage management integrated circuit. The application processor outputs clock information on an operation clock signal, and includes a core circuit. The voltage management integrated circuit receives the clock information from the application processor, and generates and outputs a core voltage having a voltage level corresponding to the clock information in response to the clock information. The operation clock signal is a clock signal, which has a variable frequency and is input to the core circuit of the application processor.

Abstract: A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region of the system memory. Each of the plurality of processing units includes a processor core and a cache memory including a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory and a cache controller. The cache controller, responsive to a store request from the processor core to update a particular VBSR line, performs a non-blocking update of the cache array in each other of the plurality of processing units contemporaneously holding a copy of the particular VBSR line by transmitting a VBSR update command on the interconnect fabric.

Abstract: A processing module, interface, and information handling system are disclosed. According to an aspect, a processing module can include a plurality of components coupled to a circuit card operable to be coupled to a host processing system. The processing module can also include a processing module interface configured to be coupled to a host interface of the host processing system. According to an aspect, the processing module interface can include a plurality of contacts operable to couple a plurality of signals configured to be coupled between the host processing and the circuit card to enable or disable use of resources of the circuit card during a reduced operating state of the host processor.

Abstract: A method, apparatus, and program product optimize power consumption in a parallel computing system that includes a plurality of computing nodes by selectively throttling performance of selected nodes to effectively slow down the completion of quicker executing parts of a workload of the computing system when those parts are dependent upon or otherwise associated with the completion of other, slower executing parts of the same workload. Parts of the workload are executed on the computing nodes, including concurrently executing a first part on a first computing node and a second part on a second computing node. The first node is selectively throttled during execution of the first part to decrease power consumption of the first node and conform a completion time of for the first node in completing the first part of the workload with a completion time for the second node in completing the second part.

Abstract: A semiconductor memory device for use in a multiprocessor system includes a shared memory area and a reset signal generator. The shared memory area is accessible by the processors of the multiprocessor system through different ports, and is assigned to a portion of a memory cell array. The reset signal generator is configured to provide a reset enable signal to a processor, predetermined as a slave processor among the multiple processors, for a predetermined time after an initial booting of the multiprocessor system. The reset signal generator also provides a reset disable signal to the slave processor after the predetermined time lapses.

Abstract: A multiple computer environment is disclosed in which an application program executes simultaneously on a plurality of computers (M1, M2, . . . Mn) interconnected by a communications network (53) and in which the local memory of each computer is maintained substantially the same by updating in due course. A lock mechanism is provided to permit exclusive access to an asset, object, or structure (ie memory location) by acquisition and release of the lock. In particular, before a new lock can be acquired by any other computer on a memory location previously locked by one computer, any re-written content(s) for the previously locked memory location are transmitted to all the other computers and their corresponding memory locations (before the in due course updating). Thus when the new lock is acquired all the corresponding memory locations of all computers have been updated.

Abstract: Methods, systems, and products are disclosed for broadcasting collective operation contributions throughout a parallel computer. The parallel computer includes a plurality of compute nodes connected together through a data communications network. Each compute node has a plurality of processors for use in collective parallel operations on the parallel computer. Broadcasting collective operation contributions throughout a parallel computer according to embodiments of the present invention includes: transmitting, by each processor on each compute node, that processor's collective operation contribution to the other processors on that compute node using intra-node communications; and transmitting on a designated network link, by each processor on each compute node according to a serial processor transmission sequence, that processor's collective operation contribution to the other processors on the other compute nodes using inter-node communications.

Abstract: A Decentralized System Services (DSS) architecture defines a framework for building fault-tolerant distributed applications across decentralized and heterogeneous systems. DSS enables “complexity through composition” by defining distributed designs as compositions of limited function and observable services which may be quickly and dynamically assembled to perform higher level functions. DSS defines a standardized interaction between distributed services using sessionless, asynchronous communications with explicit failure semantics. Accounting for latency, failure and state management all become a natural part of the design process. DSS includes a runtime implementation for managing concurrent services—the Common Concurrency Runtime (CCR), a protocol for service interactions—the Web Services Application Protocol (WSAP), and a set of required service behaviors which provide for composibility, location independence, and fault tolerance—Distributed Protocol Oriented Programming (DPOP).

Abstract: A system and method forward data between processing elements. A first processing element includes an address register that stores a first memory address. A forwarding storage element is coupled to the first processing element. A second processing element, coupled to the forwarding storage element, transmits a second memory address to the forwarding storage element. The forwarding storage transmits the second memory address to the first processing element, and the first processing element compares the second memory address with the first memory address.