Digital Signal Processor Patents (Class 712/35)
  • Patent number: 10387155
    Abstract: A processing system includes a program processor for executing a program, and a dedicated processor for executing operations of a particular type (e.g. vector processing operations). The program processor uses an interfacing module and a group of two or more register banks to offload operations of the particular type to the dedicated processor for execution thereon. While the dedicated processor is accessing one register bank for executing a current operation, the interfacing module can concurrently load data for a subsequent operation into a different one of the register banks. The use of multiple register banks allows the dedicated processor to spend a greater proportion of its time executing operations.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: August 20, 2019
    Assignee: Imagination Technologies Limited
    Inventors: Paul Murrin, Gareth Davies, Adrian J. Anderson
  • Patent number: 10031888
    Abstract: The invention relates to a multi-core processor memory system, wherein it is provided that the system comprises memory channels between the multi-core processor and the system memory, and that the system comprises at least as many memory channels as processor cores, each memory channel being dedicated to a processor core, and that the memory system relates at run-time dynamically memory blocks dedicatedly to the accessing core, the accessing core having dedicated access to the memory bank via the memory channel.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: July 24, 2018
    Assignee: Hyperion Core, Inc.
    Inventor: Martin Vorbach
  • Patent number: 9766942
    Abstract: There is provided a control device including an allocation unit configured to allocate processing of tasks to any of respective processing devices on the basis of contents of the tasks and at least any of attributes and states of the processing devices.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: September 19, 2017
    Assignee: SONY CORPORATION
    Inventors: Ken Miyashita, Hironori Isobe
  • Patent number: 9710052
    Abstract: Embodiments include a method of managing operating states of a plurality of digital signal processors (DSPs). The method generally includes determining a first number of the plurality of DSPs to operate in a ready state, determining a second number of the plurality of DSPs to operate in a first energy-saving state, and determining a third number of the plurality of DSPs to operate in a second energy-saving state. In some embodiments, the first energy-saving state corresponds to a dormant mode of the DSPs, and the second energy-saving state corresponds to a reset mode of the DSPs.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: July 18, 2017
    Assignee: Cisco Technology, Inc.
    Inventors: Ming Chen, Prasad Miriyala, Ramakrishnan Kunnath, Jing Li
  • Patent number: 9710427
    Abstract: A method, apparatus and product useful for verifying Distributed Symmetric Multi-Processing systems (DSMPs). The method comprising: determining one or more sub-systems of a DSMP, wherein each sub-system is a Symmetric Multi-Processing System (SMP) which comprises a shared memory and a set of processing entities that have the same access permissions to the shared memory; and verifying the DSMP using a verification tool designed to verify an SMP, wherein said verifying is performed by verifying each sub-system.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: July 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Alex Goryachev, Ronny Morad, Tali Rabetti, Sergey Shusterman
  • Patent number: 9612844
    Abstract: A method and apparatus are provided for executing instructions of a multi-threaded processor having multiple hardware threads (32, 34) with differing hardware resources comprising the steps of receiving a plurality of streams of instructions (38, 44) and determining which hardware threads are able to receive instructions for execution (40, 46), determining whether a thread determined to be available for executing an instructions has the hardware resources available required by that instructions (36) and executing the instruction in dependence on the result of the determination (50).
    Type: Grant
    Filed: January 18, 2010
    Date of Patent: April 4, 2017
    Assignee: Imagination Technologies Limited
    Inventor: Andrew Webber
  • Patent number: 9501383
    Abstract: A method for securing a first program, the first program including a finite number of program points and evolution rules associated to program points and defining the passage of a program point to another, the method including defining a plurality of exit cases and, when a second program is used in the definition of the first program, for each exit case, definition of a branching toward a specific program point of the first program or a declaration of branching impossibility, defining a set of properties to be proven, each associated with one of the constitutive elements of the first program, said set of properties comprising the branching impossibility as a particular property and establishment of the formal proof of the set of properties.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: November 22, 2016
    Inventor: Dominique Bolignano
  • Patent number: 9431374
    Abstract: A semiconductor device includes a substrate having a first part and a second part, the first and second parts being continuous with each other and at different height levels, a first semiconductor chip overlapping the first and second parts of the substrate, an electrical interconnection structure connecting the first part of the substrate and the first semiconductor chip, a distance between the first part of the substrate and the first semiconductor chip being shorter than a distance between the second part of the substrate and the first semiconductor chip, and at least one electronic component in a space between the second part of the substrate and the first semiconductor chip.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: August 30, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Baik-Woo Lee, Seok-Hyun Lee
  • Patent number: 9369547
    Abstract: The present embodiments disclose techniques for transcoding media data using a virtualized network environment. This virtual environment may be hosted on one or more memory cards which each contain one or more memory chips. For example, the memory cards may include plurality of interconnected memory elements mounted on a PCB. The virtual environment may include virtual machines that execute applications that transcode the media data from one format to a different format. Because each virtual machine acts like an independent physical machine, a plurality of transcode operations may be performed in parallel on respective virtual machines. By virtualizing the transcode process, the hardware required for transcoding can be reduced relative to using a dedicated data center for transcoding the media data.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: June 14, 2016
    Assignee: Disney Enterprises, Inc.
    Inventor: Matthew Lemus
  • Patent number: 9277340
    Abstract: In a sound output system including: an information processing apparatus; a first output device; and a second output device, the information processing apparatus generates, based on predetermined information processing, a first sound signal to be outputted to the first output device, and a second sound signal that is a sound signal to be outputted to the second output device and has a content different from that of the first sound signal. When headphones are connected to the second output device, the second sound signal is generated such that at least a part of a first sound which is not outputted as a second sound when no headphones are connected, is contained in the second sound, and the second sound is outputted from the headphones.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: March 1, 2016
    Assignee: NINTENDO CO., LTC.
    Inventor: Masato Mizuta
  • Patent number: 9274801
    Abstract: Systems, methods, and other embodiments associated with a digital signal processor that includes a read-only memory are described. According to one embodiment, a processor includes a read-only memory (ROM) configured with a plurality of processing routines that when executed cause the processor to implement corresponding processor features. The processor includes a digital signal processor (DSP) engine. The DSP engine is configured to determine whether a processing routine of the plurality of processing routines is enabled based, at least in part, on a corresponding value in a control register. The DSP engine is configured to selectively execute the processing routine based, at least in part, on whether the value indicates that the processing routine is enabled.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: March 1, 2016
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventor: Kapil Jain
  • Patent number: 9256458
    Abstract: Methods, parallel computers, and computer program products for conditionally updating shared variable directory (SVD) information in a parallel computer are provided. Embodiments include a runtime optimizer receiving a broadcast reduction operation header. The broadcast reduction operation header includes an SVD key and a first SVD address. The first SVD address is associated with the SVD key in a first SVD associated with a first task. Embodiments also include the runtime optimizer retrieving from a remote address cache associated with the second task, a second SVD address indicating a location within a memory partition associated with the first SVD, in response to receiving the broadcast reduction operation header. Embodiments also include the runtime optimizer determining that the first SVD address does not match the second SVD address and updating the remote address cache with the first SVD address.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: February 9, 2016
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Archer, James E. Carey, Philip J. Sanders, Brian E. Smith
  • Patent number: 9052957
    Abstract: The system for conducting intensive multitask and multistream calculation in real time comprises a central processor core (SPP) for supporting the system software and comprising a control unit (ESCU) for assigning threads of an application, the non-critical threads being run by the central processor core (SPP), whereas the intensive or specialized threads are assigned to an auxiliary processing part (APP) comprising a set of N auxiliary calculation units (APU0, . . . , APUN-1) that are optimized for fast processing of certain operations, a memory space (SMS) shared by the auxiliary calculation units (APU0, . . . , APUN-1) via an internal network and a unit (ACU) for controlling and assigning the auxiliary resources. The various elements of the system are arranged in such a manner that communication between the various auxiliary calculation units (APU0, . . . , APUN-1) or between those auxiliary calculation units (APU0, . . .
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: June 9, 2015
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Raphaël David, David Vincent, Nicolas Ventroux, Thierry Collette
  • Patent number: 9009723
    Abstract: A method for managing distributed computer data stream acceleration devices is provided that utilizes distributed acceleration devices on nodes within the computing system to process inquiries by programs executing on the computing system. The available nodes and available acceleration devices in the computing system are identified. In addition, a plurality of virtual acceleration device definitions is created. Each virtual acceleration device definition includes attributes used to configure at least one of the plurality of identified acceleration devices. When an inquiry containing an identification of computing system resources to be used in processing the inquiry is received, at least one virtual acceleration device definition that is capable of configuring an acceleration device in accordance with the computing system resources identified by the inquiry is identified.
    Type: Grant
    Filed: March 19, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Louis Ralph Degenaro, James Ryan Giles, Gabriela Jacques Da Silva
  • Patent number: 9003166
    Abstract: System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: April 7, 2015
    Assignee: Synopsys, Inc.
    Inventors: Navendu Sinha, William Charles Jordan, Bryon Irwin Moyer, Stephen John Joseph Fricke, Roberto Attias, Akash Renukadas Deshpande, Vineet Gupta, Shobhit Sonakiya
  • Patent number: 8972699
    Abstract: A multicore interface with dynamic task management capability and a task loading and offloading method thereof are provided. The method disposes a communication interface between a micro processor unit (MPU) and a digital signal processor (DSP) and dynamically manages tasks assigned by the MPU to the DSP. First, an idle processing unit of the DSP is searched, and then one of a plurality of threads of the task is assigned to the processing unit. Finally, the processing unit is activated to execute the thread. Accordingly, the communication efficiency of the multicore processor can be effectively increased while the hardware cost can be saved.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: March 3, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Tai-Ji Lin, Tien-Wei Hsieh, Yuan-Hua Chu, Shih-Hao Ou, Xiang-Sheng Deng, Chih-Wei Liu
  • Patent number: 8935468
    Abstract: A microprocessor includes a memory interface to obtain data envelopes of a first length, and control logic to implement an instruction to load an initial data envelope of a stream of data values into a buffer, each data value having a second length shorter than the first length, the stream of data values being disposed across successive data envelopes at the memory interface. Another instruction merges current contents of the buffer and the memory interface such that each invocation loads one of the data values into a first register, and moves at least a remainder of the current contents of the memory interface into the buffer for use in a successive invocation. Another instruction loads a reversed representation of a set of data values obtained via the memory interface into a second register. Another instruction implements an FIR computation including a SIMD operation involving multiple data values of the stream and the reversed representation.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: January 13, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Dror E. Maydan, William A. Huffman, Sachin Ghanekar, Fei Sun
  • Patent number: 8761188
    Abstract: In the provided architecture, one or more multi-threaded processors may be combined with hardware blocks. The resulting combination allows for data packets to undergo a processing sequence having the flexibility of software programmability with the high-performance of dedicated hardware. For example, a multi-threaded processor can control the high-level tasks of a processing sequence, while the computationally intensive events (e.g., signal processing filters, matrix operations, etc.) are handled by dedicated hardware blocks.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: June 24, 2014
    Assignee: Altera Corporation
    Inventors: Anargyros Krikelis, Martin Roberts
  • Patent number: 8601176
    Abstract: Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: December 3, 2013
    Assignee: Altera Corporation
    Inventors: Edwin Franklin Barry, Nikos P. Pitsianis, Kevin Coopman
  • Patent number: 8555251
    Abstract: A signal processing apparatus for performing signal processing including a plurality of steps in data units by software signal processing includes signal processing modules performing the steps, a circuit configuration information storing and managing unit storing the signal processing modules and circuit configuration information, a signal processing order determining unit determining a signal processing order by performing path routing, a signal processing executing unit executing the signal processing in the determined order, and a circuit configuration changing unit changing circuit configuration information and causing the signal processing order determining unit to re-execute path routing to determine a signal processing order for the changed circuit configuration information during a period from the end of the software signal processing in the data unit to the beginning of the subsequent data unit.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: October 8, 2013
    Assignee: Sony Corporation
    Inventor: Kosei Yamashita
  • Patent number: 8533716
    Abstract: A method and apparatus for resource management in a multicore processor is disclosed. A system management controller (130) provides omnipresent scheduling, synchronization, load balancing, and power and memory management services to each processing resource (150) within in a multicore processor (10), via a plurality of system management clients (120) implemented in hardware or software. The controller (130) allocates the tasks executing in each processing resource (150) by means of interrupt control signals, which interact directly with the system management clients (120), enabling processing resources (150) to autonomously create, execute and distribute tasks around a parallel system architecture whilst monitoring and policing the use of shared system resources (140).
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: September 10, 2013
    Assignees: Synopsys, Inc., Fujitsu Semiconductor Limited
    Inventor: Mark David Lippett
  • Patent number: 8495602
    Abstract: The present disclosure includes a shader compiler system and method. In an embodiment, a shader compiler includes a decoder to translate an instruction having a vector representation to a unified instruction representation. The shader compiler also includes an encoder to translate an instruction having a unified instruction representation to a processor executable instruction.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: July 23, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Lin Chen, Guofang Jiao, Chihong Zhang, Junhong Sun
  • Patent number: 8464025
    Abstract: A signal processing apparatus able to raise a processing capability in processing accompanying access to a storing means is provided. Stream control units (SCU) 203—0 to 203—3 access data at an external memory system or local memories 204—0 to 204—3 according to a thread under control from a host processor. Processor units (PU) arrays 202—0 to 202—3 perform image processing by a different thread from the thread of the SCUs 203—0 to 203—3.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: June 11, 2013
    Assignee: Sony Corporation
    Inventors: Yuji Yamaguchi, Masatoshi Imai, Toshiharu Noda, Naosuke Asari, Tomoo Mitsunaga, Mitsuharu Ohki, Kazumasa Ito, Hidetoshi Nagano, Sumito Arakawa, Kei Ito
  • Patent number: 8429384
    Abstract: An architecture for a digital signal processor alleviates the difficulties and complexities normally associated with writing and optimizing programs to avoid stalls during which one instruction awaits the result of a prior instruction. The architecture coordinates the processing of data for multiple instructions through a multiple stage data pipeline. As a result, the architecture not only supports simultaneous execution of multiple programs, but also permits each program to execute without delays caused by inter-relationships between instructions within the program.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: April 23, 2013
    Assignee: Harman International Industries, Incorporated
    Inventors: James D. Pennock, Ronald Baker, Brian R. Parker, Christopher Belcher
  • Patent number: 8364941
    Abstract: Systems, methods, and computer software for operating a device can be used to operate the device in multiple modes. The device can be operated in a first operating mode adapted for processing data, in which a first processor executes a driver for a nonvolatile memory and a second processor performs processing of data stored in files on the nonvolatile memory. An instruction can be received to switch the device to a second operating mode adapted for reading and/or writing files from or to the nonvolatile memory. The driver for the nonvolatile memory can be switched from the first processor to the second processor in response to the instruction, and the driver for the nonvolatile memory can be executed on the second processor after performing the switch. A communications driver can be executed on the first processor in response to the instruction to switch the device to the second operating mode.
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: January 29, 2013
    Assignee: Apple Inc.
    Inventors: Michael J. Cornwell, Christopher P. Dudte
  • Patent number: 8363683
    Abstract: Digital signal processing based methods and systems for receiving data signals include parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate automatic gain control (AGC) loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate offset compensation loop for each ADC path. In an embodiment, the present invention is implemented as a multi-channel receiver that receives a plurality of data signals.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: January 29, 2013
    Assignee: Broadcom Corporation
    Inventors: Oscar Agazzi, Venugopal Gopinathan
  • Patent number: 8316378
    Abstract: A method includes receiving data in a first data processing module, and enabling a second data processing module when at least one signal time slot of the received data comprises data that complies with a first data transmission standard. The method also includes exchanging signals between the first data processing module and software executing in a processor, and determining that a software configuration of the second data processing module has been completed. The method also includes processing the data in the second data processing module for the at least one signal time slot, and enabling a third data processing module upon a completion of processing at least one data block in the second data processing module, and determining that a software configuration of the third data processing module has been completed, the at least one data block comprising multiple signal time slots.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: November 20, 2012
    Assignee: MediaTek Inc.
    Inventors: John Zijun Shen, Carsten Aagaard Pedersen, Deepak Mathew, Paul Donald Krivacek, Aiguo Yan, Timothy Perrin Fisher-Jeffes
  • Patent number: 8261085
    Abstract: According to some implementations methods, apparatus and systems are provided involving the use of processors having at least one core with a security component, the security component adapted to read and verify data within data blocks stored in a L1 instruction cache memory and to allow the execution of data block instructions in the core only upon the instructions being verified by the use of a cryptographic algorithm.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: September 4, 2012
    Assignee: Media Patents, S.L.
    Inventor: Álvaro Fernández Gutiérrez
  • Patent number: 8250342
    Abstract: Architecture of a digital signal processing engine and method for digital signal processing therewith are described. Instruction memory stores an instruction which has at least one opcode which is selected from a group consisting of a control opcode, a digital signal processing (DSP) opcode, and a memory opcode. A digital signal processing engine includes a controller for receiving the control opcode, a DSP core for receiving the DSP opcode, and a memory interface for receiving the memory opcode. The controller, the digital signal processing core, and the memory interface are separate pipelines at least two of which have different numbers of stages. The controller may include an arithmetic logic unit, a base address regfile, and a branch/decode circuit.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: August 21, 2012
    Assignee: Xilinx, Inc.
    Inventors: Igor Kostarnov, Richard Walke
  • Patent number: 8244931
    Abstract: Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: August 14, 2012
    Assignee: Altera Corporation
    Inventors: Edwin Franklin Barry, Nikos P. Pitsianis, Kevin Coopman
  • Patent number: 8176296
    Abstract: Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: May 8, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventor: Warren Snyder
  • Patent number: 8151098
    Abstract: A signal processing apparatus for processing a periodic signal outputted from a signal source has a central processing unit and a task switch timer. The central processing unit performs multiple tasks including a signal processing task in parallel. In the signal processing task, the central processing unit starts to process the periodic signal after performing a synchronization processing to synchronize with the periodic signal, setting the task switch timer to a predetermined time upon completion of the synchronization processing, and enabling an interrupt to the central processing unit upon completion of the synchronization processing. The task switch timer disables the interrupt to the central processing unit immediately before expiring. The task switch timer outputs a task switch signal to the central processing unit when expiring, so that the central processing unit switches to the signal processing task.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: April 3, 2012
    Assignee: DENSO CORPORATION
    Inventors: Akimasa Niwa, Masahiro Kamiya, Hideaki Ishihara, Yoshinori Teshima
  • Patent number: 8145822
    Abstract: One aspect relates to a computer system including a first data processing unit, a second data processing unit and a data transmission/memory device. The data transmission/memory can transmit sets of data from the first data processing unit to the second data processing unit. The data transmission/memory device includes a first memory region and a second memory region.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: March 27, 2012
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Hachmann, Christian Sauer
  • Patent number: 8145888
    Abstract: A data processing circuit has an execution circuit (18) with a plurality of functional units (20). An instruction decoder (17) is operable in a first and a second instruction mode. In the first instruction mode instructions have respective fields for controlling each of the functional units (20), and in the second instruction mode instructions control one functional unit. A mode control circuit (12) controls the selection of the instruction modes. In an embodiment, the instruction decoder uses time-stationary decoding of the selection of operations to be executed by the execution circuit (18) and the selection of destination registers from the set of registers (19). Mode switching is a more efficient way of reducing instruction time for time stationary processors than indicating functional units for which the instruction contains commands.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: March 27, 2012
    Assignee: Silicon Hive B.V.
    Inventors: Jeroen Anton Johan Leijten, Hendrik Tjeerd Joannes Zwartenkot
  • Patent number: 8095782
    Abstract: Graphics processing elements are capable of processing multiple contexts simultaneously, reducing the need to perform time consuming context switches compared with processing a single context at a time. Processing elements of a graphics processing pipeline may be configured to support all of the multiple contexts or only a portion of the multiple contexts. Each processing element may be allocated to process a particular context or a portion of the multiple contexts in order to simultaneously process more than one context. The allocation of processing elements to the multiple contexts may be determined dynamically in order to improve graphics processing throughput.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: January 10, 2012
    Assignee: NVIDIA Corporation
    Inventors: John M. Danskin, Lacky V. Shah
  • Patent number: 8090921
    Abstract: A processing device included on a single chip includes processors capable of executing tasks in parallel and a cache memory shared by the processors, wherein the cache memory includes single-port memories and read data selection units, each of the single-port memories have one data output port, and each of the read data selection units is in a one-to-one association with each of the processors and selects a single-port memory which stores data to be read to a associated processor, from among the single-port memories.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: January 3, 2012
    Assignee: Panasonic Corporation
    Inventors: Tetsu Hosoki, Masaitsu Nakajima
  • Patent number: 8082372
    Abstract: Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: December 20, 2011
    Assignee: Altera Corporation
    Inventors: Edwin Franklin Barry, Nikos P. Pitsianis, Kevin Coopman
  • Patent number: 8078834
    Abstract: A digital signal processor includes a control block configured to issue instructions based on a stored program, and a compute array including two or more compute engines configured such that each of the issued instructions executes in successive compute engines of at least a subset of the compute engines at successive times. The digital signal processor may be utilized with a control processor or as a stand-alone processor. The compute array may be configured such that each of the issued instructions flows through successive compute engines of at least a subset of the compute engines at successive times.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: December 13, 2011
    Assignee: Analog Devices, Inc.
    Inventor: Douglas Garde
  • Patent number: 8065506
    Abstract: This invention is an application specific integrated processor to implement the complete fixed-rate DRX signal processing paths (FDRX) for a reconfigurable processor-based multi-mode 3G wireless application. This architecture is based on the baseline 16-bit RISC architecture with addition functional blocks (ADU) tightly coupled with the based processor's data path. Each ADU accelerates a computation-intensive tasks in FDRX signal path, such as multi-tap FIRs, IIRs, complex domain and vectored data processing. The ADUs are controlled through custom instructions based on the load/store architecture. The whole FDRX data path can be easily implemented by the software employing these custom instructions.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: November 22, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Jinwen Xi, Roman Staszewski, Thang Minh Tran
  • Publication number: 20110246749
    Abstract: In an example embodiment, there is described herein an apparatus comprising an interface for communicating with a plurality of digital signal processors and logic operable to send and receive data via the interface. The logic is configured to determine a first set of digital signal processors to be maintained in a ready state, a second set of digital signal processors to be maintained in a first energy saving state, and a third set of digital signal processors to be maintained in a second energy saving state.
    Type: Application
    Filed: March 31, 2010
    Publication date: October 6, 2011
    Inventors: Ming Chen, Prasad Miriyala, Ramakrishnan Kunnath, Jing Li
  • Patent number: 7987465
    Abstract: A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using the available processing resources to produce resulting data, and the resulting data is passed to an input/output device.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: July 26, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Korbin Van Dyke, Paul W Campbell, Don A. Van Dyke, Ali Alasti, Stephen C. Purcell
  • Patent number: 7984448
    Abstract: A system and method for supporting collective communications on a plurality of processors that use different parallel programming paradigms, in one aspect, may comprise a schedule defining one or more tasks in a collective operation, an executor that executes the task, a multisend module to perform one or more data transfer functions associated with the tasks, and a connection manager that controls one or more connections and identifies an available connection. The multisend module uses the available connection in performing the one or more data transfer functions. A plurality of processors that use different parallel programming paradigms can use a common implementation of the schedule module, the executor module, the connection manager and the multisend module via a language adaptor specific to a parallel programming paradigm implemented on a processor.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: July 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gheorghe Almasi, Gabor Dozsa, Sameer Kumar
  • Patent number: 7975080
    Abstract: Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: July 5, 2011
    Inventors: Edwin Franklin Barry, Nikos P. Pitsianis, Kevin Coopman
  • Patent number: 7969187
    Abstract: A hardware interface in an integrated circuit is disclosed. The hardware interface comprises data storage coupled to store and provide data; a data shifter coupled to the data storage to at least bit shift the data obtained from the data storage; and a control circuit coupled to the data storage and the data shifter for controlling a transfer of the data from the data storage and the data shifter. The control circuit comprises a state machine for controlling operation of the data storage and the data shifter; and the state machine is programmable responsive to code executable by a processor coupled to an auxiliary processing unit to adapt to the auxiliary processing unit.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: June 28, 2011
    Assignee: Xilinx, Inc.
    Inventors: Stephen A. Neuendorffer, Paul M. Hartke, Paul R. Schumacher
  • Patent number: 7953958
    Abstract: A joint detection system is configured to perform joint detection of received signals and includes a joint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: May 31, 2011
    Assignee: MediaTek Inc.
    Inventors: John Zijun Shen, Paul D. Krivacek, Thomas J. Barber, Jr., Lidwine Martinot, Aiguo Yan, Marko Kocic
  • Patent number: 7949801
    Abstract: Coprocessor systems for using a main microprocessor DMA channel to write to a port to control a coprocessor system are provided. In certain examples, coprocessor systems are described using a main CPU counter to trigger a DMA channel to perform a single byte transfer to a port used to control coprocessor command timing.
    Type: Grant
    Filed: June 30, 2007
    Date of Patent: May 24, 2011
    Assignee: Pitney Bowes Inc.
    Inventors: George T. Monroe, Linda Dore, Michael LePore
  • Publication number: 20110099352
    Abstract: There is provided a method of performing single instruction multiple data (SIMD) operations. The method comprises storing a plurality of arrays in memory for performing SIMD operations thereon; determining a total number of SIMD operations to be performed on the plurality of arrays; loading a counter with the total number of SIMD operations to be performed on the plurality of arrays; enabling a plurality of arithmetic logic units (ALUs) to perform a first number of operations on first elements of the plurality of arrays; performing the first number of operations on first elements of the plurality of arrays using the plurality of ALUs; decrementing the counter by the first number of operations to provide a remaining number of operations; and enabling a number of the plurality of ALUs to perform the remaining number of operations on second elements of the plurality of arrays.
    Type: Application
    Filed: November 23, 2009
    Publication date: April 28, 2011
    Applicant: Mindspeed Technologies, Inc.
    Inventor: Patrick D. Ryan
  • Publication number: 20110099398
    Abstract: An integrated circuit includes a main processing unit, a peripheral connection port for connecting a peripheral device, and an auxiliary processing unit configured to control the peripheral connection port and to perform controlling of interruption and transmission of data from the peripheral device connected to the peripheral connection port instead of the main processing unit. The main processing section and the peripheral connection portion are connected to each other with an inner bus. The main processing unit uses a memory resource provided in the auxiliary processing unit as a part of an inner memory space of the main processing unit.
    Type: Application
    Filed: December 30, 2010
    Publication date: April 28, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: Masahiro HOUSHAKU
  • Patent number: 7917907
    Abstract: Techniques for processing transmissions in a communications (e.g., CDMA) system. An aspect of the disclosed subject matter includes a method for processing instructions on a multithreaded processor. The multithreaded processor processes a plurality of threads via a plurality of processor pipelines. The method includes the step determining the operating frequency, F, at which the multithreaded processor operates. Then, the method determines a variable thread switch timeout state for triggering the switching of the processing among the plurality of active threads. The variable thread switch timeout state varies so that each of the plurality of active threads operates at a frequency of an allocated portion of the frequency, F. The allocated portion at which the active threads operate is determined at least in part in order to optimize the operation of the multithreaded processor.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: March 29, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Muhammad Ahmed, Sujat Jamil, Erich Plondke, Lucian Codrescu, William C. Anderson
  • Patent number: 7904838
    Abstract: An integrated circuit includes a core-logic providing a core-logic output, a latch in communication with the core-logic to store a state of the core-logic output, and an isolation circuit for selectively interconnecting the core-logic output to an input of the latch. The circuit also includes and a power consumption controller in communication with the core-logic, the latch and the isolation circuit, for controlling the latch to store a state of the core-logic output, and output a corresponding signal. The controller is further operable to signal the isolation circuit to isolate the core-logic output from the latch by providing an output corresponding to predetermined value and transition the core-logic from a high power state and a low power state. This prevents transient signals from propagating to interconnected circuit blocks and external devices.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: March 8, 2011
    Assignee: ATI Technologies ULC
    Inventors: Aris Balatsos, Charles Leung, Siva Raghu Ram Voleti