Abstract: This processing is distributed among number of simple hexagonal units distributed in a honeycomb layer, consisting of a central hexagram surrounded by six receiving cells, each representing an invariable binary place fed into central hexagram's CPU controlled by a simple program. The activated receiving cells indicate the presence of a stimulus. The interconnected layers overlap so that the higher-level receiving cells get input from the lower-level central hexagrams and higher-level output modifies lower-level programs as well as sends input to other levels or Memory Units. Integration of layer output is achieved in 3D Memory Unit Complex consisting of truncated octagons, where each hexagonal side represents a binary number linked to 6 others through one binary place that makes adjacent numbers different. The input into each Memory Unit comes from the output of a Patch of central hexagrams a clocked input, other-layer output or a Memory Unit feedback.

Abstract: During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in the chip to execute them, and accesses RAM and peripheral circuits in the chip. For motor control circuits that exist only in the target chip, the CPU accesses them via serial communication. When the one-chip microcomputer operates alone, its CPU switches a switching circuit to a JTAG interface side to actuate a motor control circuit via internal serial communication.

Abstract: A DSP (Digital Signal Processing) architecture with a wide memory bandwidth and a memory mapping method thereof. The DSP architecture includes: a first communication port; first, second, and third memory devices, which are connected with the first communication port and are arranged in a first row direction of the DSP architecture; a fourth memory device, a calculation element, and a fifth memory device, which are arranged in a second row direction below a first row direction of the DSP architecture; and sixth, seventh, and eighth memory devices, which are connected with the first communication port and arranged in a third row direction of the DSP architecture, wherein the calculation element is connected with the first through the eight memory devices.

Abstract: A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural components jointly implement a single processor and instruction set. Advantageously, the embedded logic on the DRAM chip implements the memory intensive processing tasks, thus reducing the amount of traffic that needs to be bussed back and forth between the CPU core and the embedded DRAM chips. The embedded DRAM logic monitors and manipulates the instruction stream into the CPU core. The architecture of the instruction set, data paths, addressing, control, caching, and interfaces are developed to allow the system to operate using a standard programming model. Specialized video and graphics processing systems are developed. Also, an extended very long instruction word (VLIW) architecture implemented as a primary VLIW processor coupled to an embedded DRAM VLIW extension processor efficiently deals with memory intensive tasks.

Abstract: A DSP superscalar architecture employing dual multiply accumulate pipelines. Dual MAC pipelines allow for a seem less transition between established RISC instruction sets and extended DSP instructions sets. Relocatable opcodes are provide to allow further extensions of RISC instruction sets. The DSP superscalar architecture also provides memory pointers with hardware circular buffer support, an interruptible and nested zero-overhead loop counter, and prioritized low-overhead interrupts.

Abstract: A matrix data processor is implemented wherein data elements are stored in physical registers and mapped to logical registers. After being stored in the logical registers, the data elements are then treated as matrix elements. By using a series of variable matrix parameters to define the size and location of the various matrix source and destination elements, as well as the operation(s) to be performed on the matrices, the performance of digital signal processing operations can be significantly enhanced.

Abstract: A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maintaining the simplicity of programming and allowing efficient physical implementation. Most of the application code can be encoded using two sets of narrow size instructions to achieve high code density. Adding a third (and larger, i.e. VLIW) instruction size allows the architecture to encode multiple operations per instruction for the performance critical section of the code. Further, each operation of the VLIW format instruction can optionally be a SIMD operation that operates upon vector data. A scheme for the optimal utilization (highest achievable performance for the given amount of hardware) of multiply-accumulate (MAC) hardware is also provided.

Abstract: A system-on-chip (SoC) for voice and video over data network applications includes a first and a second general purpose processors and a plurality of coprocessors. The coprocessors include: a VCODEC engine for video compression/decompression, a security engine for data encryption/decryption, a network processor for processing data packets, a video scaling controller for scaling up/down video frames, and digital signal coprocessors for signal processing and audio codec. An on-chip shared memory (e.g., SRAM) is coupled to the processors and some of the coprocessors. The SoC also includes: i) a stream controller for controlling various properties of a stream buffer in the shared memory according to a user defined context; ii) a transaction management engine for managing data especially stream transactions in accordance with one or more task queues created by the processors; and iii) a bi-directional stream bus coupled to the shared memory and a plurality of peripheral controllers.

Abstract: A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.

Abstract: An architecture for a digital signal processor alleviates the difficulties and complexities normally associated with writing and optimizing programs to avoid stalls during which one instruction awaits the result of a prior instruction. The architecture coordinates the processing of data for multiple instructions through a multiple stage data pipeline. As a result, the architecture not only supports simultaneous execution of multiple programs, but also permits each program to execute without delays caused by inter-relationships between instructions within the program.

Abstract: The present invention generally relates to a method, system and program product for distributing portal content processing. Specifically, a request for portal content is received on a surrogate system and then passed to a portal system. The portal system will obtain and aggregate a first type of the requested content, and then package the aggregated content into a response. The response will also include place holders that correspond to the remaining type of the requested content. The response will then be transmitted to the surrogate system, which will, based upon the place holders, obtain the remaining type of portal content. Once obtained, the remaining type of portal content will replace the place holders in the response, and the response will be rendered for the requesting portal user.

Abstract: A communication device is provided which has a programmable multichannel signal processor for real time processing of user data, which are to be transmitted, within the framework of a plurality of real time applications. The real time applications are each assigned different, application-specific programmed processing channels of the multichannel signal processor for program-controlled processing of user data.

Abstract: The disclosure is a data processing device with selective data cache architecture and a computer system including the data processing device. The data processing device is comprised of a microprocessor, a coprocessor, a microprocessor data cache, an X-data cache, and a Y-data cache. The microprocessor fetches and executes instructions, and the coprocessor carries out digital signal processing functions. The microprocessor data cache stores data provided from the microprocessor. The X-data cache stores a first group of data provided from the coprocessor while the Y-data cache stores a second group of data provided from the coprocessor.

Abstract: In a mobile unit of a GSM network (Global System for Mobile Communications), various tasks are performed under real-time constraints. After starting an execution of a first task, the execution of the first task is suspended a plurality of times for a respective plurality of time intervals. A second task is executed during at least one of the plurality of time intervals. The first and second tasks are performed by a single-core microprocessor digital signal processor with a microprocessor and a digital signal processor combined on a single chip.

Abstract: An integrated circuit comprising a reduced instruction set computer (RISC) controller to execute RISC instructions, one or more digital signal processing (DSP) units to execute DSP instructions, and a unified instruction pipeline coupled to the RISC controller and the one or more DSP units, the unified instruction pipeline to decode and initiate execution of the RISC instructions and the DSP instructions of a unified RISC and DSP instruction set, the unified instruction pipeline to decode and initiate the RISC instructions when the DSP instructions are inactive, and to decode and initiate the DSP instructions when the RISC instructions are inactive.

Abstract: A bus monitor is provided as a tool for developing, debugging and testing a system having an embedded processor. The bus monitor resides within the same chip or module as the processor, which allows connection to internal processor buses not accessible from external contacts. The monitor uses a separate circular buffer to continuously store, in real-time, data traces from each of one or more internal processor buses. Upon the occurrence of a trigger condition, storage stops and a trace is preserved. Trigger conditions can depend on events occurring on multiple buses and are downloaded via an interface from an external device. Data traces are uploaded via the interface to an external device for evaluation of processor operation.

Abstract: The invention describes a digital signal processor to execute at least one dedicated operation of a dedicated system such as an digital front-end of any digital subscriber line system.

Abstract: An external ROM stores a control program PG for controlling a microcomputer. An MPU executes copy processing to copy a high-speed processing part PGM1 stored in the external ROM to a high-speed processing region of an internal RAM. When a fetch address AZ1 specified by the MPU indicates a region of the external ROM in which the high-speed processing part PGM1 is stored, the address translation unit translates the fetch address AZ1 to the address AF of a region of the internal RAM corresponding to the high-speed processing part PGM1.

Abstract: An integrated digital subscriber line transceiver includes a single integrated circuit that has a digital signal processing engine, a time division multiplexing framer (for example, a T1/E1 framer), and a static random access memory. The integrated circuit also includes a microprocessor coupled to the digital signal processing engine, the time division multiplexing framer, and the static random access memory. The digital signal processing engine, in one embodiment, includes an HDSL2/G.SHDSL data pump and an HDSL2/G.SHDSL framer.

Abstract: An apparatus and method for providing enhanced performance for multi-processor multimedia chips. In one embodiment, the present invention is comprised of a data and communication apparatus coupled with the multimedia system in which the multi-processor multimedia chips are disposed. The present invention is comprised of a data memory to retrievably store data. The present invention is further comprised of an instruction memory to retrievably store instructions. The present invention is also comprised of an incoming buffer which permits transfer of data into the data and communication apparatus and provides fast access to streaming data. The present invention is additionally comprised of an outgoing buffer which monitors and permits transfer of data out of the data and communication apparatus.

Abstract: A multi-processor arrangement having an interprocessor communication path between each of every possible pair of processors, in addition to I/O paths to and from the arrangement, having signal processing functions configurably embedded in series with the communication paths and/or the I/O paths. Each processor is provided with a local memory which can be accessed by the local processor as well as by the other processors via the communications paths. This allows for efficient data movement from one processor's local memory to another processor's local memory, such as commonly done during signal processing corner turning operations. The configurable signal processing logic may be configured to host one or more signal processing functions to allow data to be processed prior to its deposit into local memory.

Abstract: A digital signal processor operates in conjunction with a scheduler hardware module and a scheduler software module in executing a highest priority runnable event among a plurality of events. The scheduler hardware module communicates an interrupt request signal to the DSP that is indicative of any change in a highest priority runnable event. The scheduler software module is executed by the DSP in response to the interrupt request signal indicating a change in highest priority runnable event. An execution of the scheduler software module by the DSP implements one of a various modes of an interrupt request routine.

Abstract: A method and a digital processor circuit to process digital delays are provided. The digital processor circuit may comprise circuit memory and a processor module such as a digital signal processor (DSP), a delay line module, a filter module and a sample rate converter module. The circuit memory may comprise a digital delay line memory portion to provide a plurality of digital delay lines; and a cache memory portion to perform a pre-fetch data transfer operation from the main memory to the cache memory portion. The cache memory portion may comprise a plurality of delay caches that are updated with data samples from corresponding delay lines in the main memory. The sizes (e.g., the relative sizes) of the delay line memory portion and the cache memory portion of the circuit memory may be adjustable. The sizes may be dependent upon algorithms executed by the processor module.

Abstract: A computing system includes a digital signal processor, a storage medium for storing parameter tables, a central processing unit coupled to the digital signal processor and the storage medium, and a shared memory coupled to the digital signal processor and the central processing unit. The digital signal processor stores a data request in the shared memory and issues a request command to the central processing unit when access to the parameter tables is desired. Upon receipt of the request command, the central processing unit reads the data request in the shared memory, accesses the storage medium for retrieving requested data that corresponds to the data request, stores the requested data in the shared memory, and issues a response command to the digital signal processor. The digital signal processor retrieves the requested data from the shared memory upon receipt of the response command from the central processing unit.

Abstract: An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.

Abstract: A stateless message-passing scheme for interactions between a network processor and a coprocessor is provided. The network processor, when receiving data frames for transmission from a network element to another network element encapsulates the entire packet that it receives within a frame. In this frame, there is provided a header field and a data field. The data field contains the data that needs to be transferred, and the header field contains all of the information regarding the deep-processing that the coprocessor is to perform so that no information of any type need be stored either by the network processor or separately regarding the processing of the data in the data packet. The coprocessor performs the operation designated by the header and returns the altered packet and header to the network processor.

Abstract: The present invention relates to a digital signal processing apparatus comprising a plurality of available hardware resource means and a first instruction set means having access to said available hardware resource means, so that at least a part of said hardware resource means execute operations under control of said first instruction set means, and further comprising a second instruction set means having access to only a predetermined limited subset of said plurality of available hardware resource means, so that at least a part of said predetermined limited subset of said hardware resource means execute operations under control of said second instruction set means.

Abstract: A plug-and-play architecture including an extension of a general purpose processor media framework for adjoining DSP processing power.

Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

Abstract: An effects processor for an effects module. The effects processor comprises a RISC processor, a DSP for fast integer multiplication and a small memory. The processor uses VARK language and a lookup table of VARK scripts to apply a variety of effects to images stored outside the effects module. The effects processor includes a serial bus interface which communicates with the Serial Bus of a compact printer system comprising one or more further modules. The Serial Bus communicates power and data between the effects module and one or more of the further modules. Methods of compositing, convolving, warping and color substitution are described.

Abstract: Executing digital signal processing (DSP) instructions in a digital signal processor integrated circuit comprising receiving a DSP instruction in digital signal processor integrated circuit to process one or more complex number operands; fetching a first operand with a first data type, the first operand having real and imaginary values with a complex data type; fetching a second operand with a second data type; prior to executing a DSP operation, determining a permutation of the first operand, the second operand, or both the first operand and the second operand, and permuting instances of the first operand, the second operand, or both the first operand and the second operand to execute the DSP operation; and executing the DSP operation in the digital signal processor integrated circuit using the first operand and the second operand to obtain a result, the result having real and imaginary values with a complex data type.

Abstract: The present invention is a system in which a multiplicity of diverse dedicated hardware off-core execution units are connected to a core processor in order to increase the speed, power, and flexibility of the processor, and a method of operating the system. Reference instructions executed by the core processor initiate the execution of Configurable Long Instruction Word (CLIW) instructions stored in a CLIW memory. The operation of the off-core execution units is controlled by CLIW instructions. These CLIW instructions may also control operations performed by the core processor, and may be in addition to any other CLIW instructions that control the core processor exclusively. The off-core logic units are operationally connected to the data memory of the core processor under the control of the core processor's data address logic.

Abstract: This invention generally relates to one or more computer networks having computers like personal computers or network servers with microprocessors linked by broadband transmission means and having hardware, software, firmware, and other means such that at least one parallel processing operation occurs that involve at least two computers in the network. More particularly, this invention relates to one or more large networks composed of smaller networks and large numbers of computers connected, like the Internet, wherein more than one separate parallel processing operation involving more than one different set of computers occurs simultaneously and wherein ongoing processing linkages can be established between virtually any microprocessors of separate computers connected to the network.

Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.

Abstract: Herein disclosed is a function-variable type DSP apparatus comprising: a storage section for storing a plurality of DSP microprogram parts; and a plurality of DSP executing sections each for executing the DSP microprogram parts to implement a DSP function, each of the DSP microprogram parts being executable by each of the DSP executing sections to perform a set of steps necessary to implement a DSP base function forming part of a DSP function, whereby the DSP executing sections are operative to receive the DSP microprogram parts simultaneously from the storage section, and selectively execute the DSP microprogram parts in a sequence to respectively implement desired DSP functions.

Abstract: A mobile station includes an RF transceiver and a user interface. The mobile station further includes a plurality of data processor cores each having a first interface supporting a first bus coupled to an associated one of a plurality of program memories, a second interface supporting a second bus coupled to a common data memory, and a third interface supporting a third bus coupled to at least one input/output device. Each of the first, second and third buses include an address bus that is sourced from the processor core and a data bus. The plurality of data processor cores may be contained within a single integrated circuit package, such as an ASIC, in a System on Chip (SoC) configuration. In this case a first processor core may function as a CPU for controlling the overall operation of the mobile station, including the user interface, while a second processor core functions as a DSP for controlling operation of the RF transceiver.

Abstract: A heterogeneous integrated circuit having a digital signal processor and at least one programmable logic core. An AMBA AHB couples the cores and most other functional units on the IC. The PLCs are also coupled to the DSP through a separate DMA sharing unit to the DSP, and particularly to the DSP memory. The memory sharing arrangement provides a separate high-speed data transfer mechanism between the PLCs and the DSP. Memory sharing is controlled to allocate the full bandwidth of the DSP memory to the PLCs and other DMA devices in proportion to their operating speeds. The AMBA AHB allows the DSP to control the PLC operations without interference with high-speed data transfers.

Abstract: A circuit employing an array of reconfigurable processing elements for wireless baseband processing. The circuit includes a first linear array of reconfigurable processing elements for processing signals from a first channel, and a second linear array of reconfigurable processing elements, coupled in parallel with the first linear array of reconfigurable processing elements, for processing signals from a second channel that is concurrent with the first channel. The circuit also includes a frame buffer array having a number of frame buffers that corresponds to a number of reconfigurable processing elements in the first and second linear arrays of processing elements. A point-to-point data bus is connected between each reconfigurable processor and an associated frame buffer. A shared data bus is connected between the first and second linear arrays of reconfigurable processing elements and the frame buffer array.

Abstract: Preparing one or more secure media effect programs, generating a binary image of the programs and associated data, loading the binary image into memory of a secondary processor, and executing the programs of the binary image with the secondary processor, substantially independent from a primary processor. A binary image builder automatically maps one or more programs and data to secondary processor memory by changing encoded binary instructions of each program before execution by the secondary processor. The changes identify locations at which the programs and data will be stored in secondary processor memory, identify locations of parameters that can be updated in real time, and enable execution control to return to a secondary processor execution kernel. The secondary processor execution kernel polls flags in a main memory to determine whether to download new or updated state data and/or program code from main memory to the secondary processor memory.

Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.

Abstract: Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.

Abstract: A bridge board connects a TMS470 processor evaluation module and a TMS320C54XX processor evaluation module. The bridge board performs translation of signal formats on both of the boards and also synchronizes the signal formats on both boards so that both boards are able to operate together. With this bridge board, and its specific connections to both of the evaluation modules, a single workstation, preferably connected to the TMS470 module is able to not only control the TMS470 module but also the TMS320 module. Software for the TMS320 can be loaded from the workstation through the TMS470 module, through the bridge board and into the TMS320 module. The software in both of the evaluation modules can then operate and interact with each other through the bridge board.

Abstract: The present invention is an integrated circuit containing multiple digital signal processors (DSPs). A single host processor interface is also placed on the chip to connect the multiple DSPs to the host. A separate direct memory access (DMA) unit is provided for each DSP to facilitate flow of data to and from a data memory for each DSP. Each DSP also includes an instruction memory.

Abstract: A single integrated circuit includes first and second data processors operating on different instruction sets independently operating on disjoint programs and data. The single integrated circuit preferably includes an external interface, a shared data transfer controller and shared memory divided into plural independently accessible memory banks. The two data processors are preferably a digital signal processor (DSP) and a reduced instruction set computer (RISC) processor. The DSP and RISC processors are suitably programmed to perform differing aspects of computer image processing.

Abstract: A matrix data processor is implemented wherein data elements are stored in physical registers and mapped to logical registers. After being stored in the logical registers, the data elements are then treated as matrix elements. By using a series of variable matrix parameters to define the size and location of the various matrix source and destination elements, as well as the operation(s) to be performed on the matrices, the performance of digital signal processing operations can be significantly enhanced.

Abstract: A circuit according to an embodiment of the present invention can load data in parallel to a barrel shifter, and output data to a pipelined multiplexer stage. The multiplexer is used to direct data from predetermined barrel slots to a predetermined number of output data slots. A control logic circuit will determine which of the barrel shifter entries are the oldest, and will drive the selects of the multiplexer to direct them to the output. The second stage of the multiplexer will drive the four 16-bit outputs to generate the 64-bit user data path. Methods for implementing the embodiments of the invention are also disclosed.

Abstract: Method and apparatus for performing a critical task using a load that is speculative. Specifically, a method of computation for performing critical tasks with speculative operations is described in one embodiment. The critical task is performed to achieve a first result while a condition of a processor used to perform said critical task is unknown. In parallel, the condition of the processor is determined. If the condition is as expected, then the first result is committed. If the condition is not as expected, then the condition is fixed to be as expected. The first result benignly fails. Also, the critical task is re-performed using the operation that is speculative resulting in a second result. The second result is then committed.

Abstract: An integrated circuit having statistical processing capability. The integrated circuit has an input for receiving input data in a first data domain. A data converter is provided for converting received input data from the first domain to a second domain different from the first domain. A statistical processor is provided for obtaining statistical information from the output of the data converter and processing the obtained statistical information in accordance with a predetermined processing algorithm. An output on the integrated circuit allow access of the processed statistical information by the statistical processor external to the integrated circuit.

Abstract: A digital signal processor comprises an arithmetic device 12 wherein a reservation processing register 26, to which setting to which from the arithmetic device 11 is possible and which has a construction for storing an address and an execution mode as a task list 18, and a clear circuit 27 for clearing the execution mode when the address in the reservation processing register 26 is copied to a program counter 21, are newly added. Threreby, in the digital signal processor comprising two arithmetic devices, it is possible to remove the processing waiting time as well as to change the processing order at respective arithmetic devices.

Abstract: A system and process are disclosed for automatically resuming data communication using an IEEE-1394 PHY when communication is suspended because input bias is momentarily lost. The PHY determines whether data communication is suspended due to the PHY being disconnected from a network by checking the status of a connected flag. If the connected flag is still set to TRUE, the PHY was not intentionally disconnected from the network and it automatically attempts to resume communication by setting a resume flag to TRUE. The invention finds application in any type of communication device using the IEEE-1394 high-speed serial bus standard including audio and video sources, which may readily be connected to a personal computer for data storage or editing. The system and process may be implemented using software code and included within a digital signal processor (DSP).