Abstract: A high performance digital signal processor includes a bidirectional communication port for communication with an external device. The bidirectional communication port includes a first transmitting circuit for transmitting to the external device a first clock on a first control line in a transmit mode and for transmitting data words on plural data lines in synchronism with the first clock, and a first receiving circuit for receiving a first acknowledge signal on a second control line in the transmit mode. The communication port further includes a second receiving circuit for receiving a second clock on the second control line in a receive mode and for receiving data words on the data lines in synchronism with the second clock, and a second transmitting circuit for transmitting a second acknowledge signal on the first control line in the receive mode. The communication port further includes switching means for switching between the transmit mode and the receive mode.

Abstract: An improved PC system that includes a main CPU microprocessor, a file-based operating system, and a DSP microprocessor arranged so that the DSP can execute main CPU operations during time intervals in which the main CPU is otherwise occupied, thereby increasing the bandwidth of the system is provided. This PC system may include multiple CPUs and/or multiple DSPs.

Abstract: A data processing device uses a processor such as a central processing unit and a special-purpose hardware circuit, such as an accelerator for accelerating the software operation using the operation program of the processor by replacing the software operation partially by the hardware. A practical application of this processor arrangement is found in mobile communication terminal devices including a digital cellular portable telephone in which a digital signal processor of a mobile communication terminal device operates in association with an accelerator for accelerating specific signal processings such as waveform equalization. The processor provides input data to the accelerator and the results of operation by the accelerator are output to a register or memory based on a cycle of operation to be read periodically by the processor.

Abstract: A peripheral module capable of interaction with a host system comprises a digital signal processor (DSP), a cache controller, and minimal or no resident memory for initial storage of instructions and data. The peripheral module utilizes the memory resources (e.g., ROM and RAM) of a host system. The cache controller interfaces to the DSP and provides an instruction and data stream, upon request, from a resident cache. A bus interface unit arbitrates access to the host system via a host bus for access to host system resources by the cache controller for extracting DSP information (e.g., instructions and data) from the host system for utilization by the DSP within the peripheral module. The cache controller and cache thereby provide the instruction and data stream as required by the DSP for digital signal processing applications and relieve the need for resident storage within the peripheral module.

Abstract: An associative signal processing apparatus for processing a plurality of samples of an incoming signal in parallel, the apparatus comprising: (a) an array of processors, each processor including a multiplicity of associative memory cells, the memory cells being operative to perform: (i) compare operations, in parallel, on the plurality of samples of the incoming signal; and (ii) write operations, in parallel, on the plurality of samples of the incoming signal; and (b) an I/O buffer register including a multiplicity of associative memory cells, the register being operative to: (i) input the plurality of samples of the incoming signal to the array of processors in parallel by having the I/O buffer register memory cells perform at least one associative compare operation and the array memory cells perform at least one associative write operation; and (ii) receive, in parallel, a plurality of processed samples from the array of processors by having the array memory cells perform at least one associative compare op

Abstract: Data is allocated into multiple memories with selective variable replication for maximizing performance by minimizing concurrent memory access conflicts. Requirements for concurrent access are summarized in a transformed concurrent access graph. Graph vertices are merged to disallow variable replication. All potential graph merges that cause a reduction in machine cycle time are identified. The ratios of saved cycles/memory cost in bytes are then computed for each potential merge. The potential merges are then sorted by their saved cycles/bytes ratio. Finally, potential merges resulting in replicated variables are selected based on their cycles/bytes ratios until a predefined memory target size is achieved. Either graph coloring or clique partitioning can be used to allocate variables into memory banks.

Abstract: This invention relates to the allocation of object code in multi-processor systems. In particular, techniques are disclosed for efficiently allocating signal processing instructions to a large array of parallel signal processing units.

Abstract: An information processor comprises a program storage unit and a control unit, the control unit includes a procedure insertion table in which information regarding an embedding point in a program and information regarding an insertion procedure to be inserted in the embedding point are described in correlation with each other, and a program dynamically changing unit for saving an instruction at an embedding point of the program held in the program storage unit in a predetermined instruction saving region with reference to the procedure insertion table, rewriting the last instruction of an insertion procedure into a branch instruction to branch to an instruction subsequent to a saved instruction, and writing the branch instruction to branch to the insertion procedure at the embedding point, thereby, at the time of execution of the insertion procedure, executing the instruction saved in the instruction saving region immediately before executing the last branch instruction.

Abstract: A processor having a modified Harvard architecture having first and second memories, an address register file divided into first and second sets of registers, first and second stream registers, and a general purpose register file for performing data streaming. The first and second sets of registers respectively address the first and second memories which, in turn, load data into the first and second stream registers. An arithmetic logic unit (ALU) accepts the stream registers and general purpose registers as inputs. Stream instructions are encoded such that a single instruction specifies an ALU operation performed on selected ALU inputs and where to store the results of the ALU operation, loads new values into the stream registers, and updates the address registers. A stream instruction has three operand fields respectively specifying two operands for the next ALU operation and a location to store the result of the current ALU operation.

Abstract: A high performance digital signal processor includes a memory for storing instructions and operands for digital signal computations and a core processor connected to the memory. The memory includes first, second and third memory banks connected to the core processor by first, second and third data and address buses, respectively. The core processor includes a program sequencer and first and second computation blocks for performing first and second subsets, respectively, of the digital signal computations. Single, dual or quad data words of 32 bits each may be accessed in each of the memory banks during each clock cycle. The multiple data words may be transferred to one or both of the first and second computation blocks.