Abstract: A method and system for performing a task in an intrinsically safe environment using an intrinsically safe, integrated module located on the safe side to convey signals to and from a field device on the hazardous side. The integrated module is configurable in order to suit the electrical characteristics and requirements of the field device. Preferably, the integrated module is software configurable, in that the module can be configured by a command signal without using switches. Furthermore, the integrated module is configurable in order to control the field device in performing the task. The integrated module includes an input/output module which is electrically connected to the field device through a Zener barrier or a galvanic isolation barrier, and a power supply to power the field device through a Zener barrier.

Abstract: Method of processing several computer-controlled technical applications. The applications are executed within the same computer working in successive work cycles by allotting thereto during the work cycles at least one time slot of a previously fixed duration. At the end of the time slot allotted to a technical application, a start interrupt is generated which is aimed at starting the execution of another technical application. Each technical application has allotted thereto at least one memory space slot for writing data. The memory space slot is write-inaccessible to the other technical applications so that a technical application which during execution possesses a given level of criticality does not disturb another application having a higher or equal level of criticality.

Abstract: The present invention relates to a method, apparatus and system for managing virtual memory, in which a co-processor (224) is adapted to use virtual memory with a host processor (202). A host memory (203) is coupled to the host processor (202) to implement the virtual memory. The co-processor (224) includes a virtual-physical memory mapping device (915) for interrogating a virtual memory table and for mapping one or more virtual memory addresses (880) requested by the co-processor (224) into corresponding physical addresses (873) in the host memory (203). The virtual memory table is stored in two or more non-contiguously addressable regions of the host memory (203), and is preferably a page table. The memory mapping device (915) further includes a multiple-entry translation lookaside buffer (889) for caching virtual-to-physical address mappings (872), where entries in the buffer (889) are replaced on a least recently used replacement basis.

Abstract: A multi-core digital signal processor is disclosed having a shared program memory with conditional write protection. In one embodiment, the digital signal processor includes a shared program memory, an emulation logic module, and multiple processor cores each coupled to the shared program memory by corresponding instruction buses. The emulation logic module preferably determines the operating modes of each of the processors, e.g., whether they are operating in a normal mode or an emulation mode. In the emulation mode, the emulation logic can alter the states of various processor hardware and the contents of various registers and memory. The instruction buses each include a read/write signal that, while their corresponding processor cores are in normal mode, is maintained in a read state. On the other hand, when the processor cores are in the emulation mode, the processor cores are allowed to determine the state of the instruction bus read/write signals.

Abstract: A signal processing system includes a control processor that has a bi-directional port, signal processors that each have a serial port, a bridge that has serial ports each operatively connected to a serial port of one of the signal processors, and a bi-directional port operatively connected to the bi-directional port of the control processor.

Abstract: A plurality of modems or modem types can run on a host processor, a digital signal processor or both, either concurrently or selectively. Modules of more than one modem program can be swapped in and out of DSP memory space. Common modem code can be run on either a host processor or on a DSP using respective command libraries.

Abstract: A master processor, such as a processor embedded in a network interface card, is coupled to a memory via a memory data bus. The master processor generates addresses for the memory and controls the reading and writing of the memory at addressed locations. A slave processor, such as an optional encryption engine, has a data input/output bus connected to the memory data bus. The master processor also controls the reading and writing of data to/from the slave processor via the memory data bus. The master processor effects data transfers from the memory to the slave processor over the data bus by generating a series of memory addresses to read the data from the memory onto the data bus. As each data word appears on the data bus, it is written into the slave processor.

Abstract: A processing system in accordance with the present invention is disclosed. The processing system comprises a processor and a microcode sequencer coupled to the processor. The microcode sequencer includes a plurality of modules. Each of the modules enables a specific function based upon a selection signal from the processor. A system and method in accordance with the present invention provides for many advantages over conventional systems. First of all, there is an efficient register bank and the hardware is smaller and more efficient than a DSP. Finally, since it is possible to program macro instructions for different applications, it is more flexible than DSP systems. It also is smaller, has a lower gate count and is faster to market because it is software programmable. Unlike RISC or coprocessor type systems, only a single assembler is needed to handle DSP and multimedia instructions. In addition, a large cache memory is not required while having a higher code density for a particular application.

Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.

Abstract: A DSP (Digital Signal Processor) having a pipe line structure which is capable of decreasing the time required for storing a result of a computation. Data stored in a cache memory is output when an instruction input into a judging unit is a judged to be a computation instruction and when an address of the stored data is the same as a previously stored address in the judging unit. The cache memory temporarily stores data inputted through a decoder and is controlled by the judging unit.

Abstract: A communication system (100) includes at least one digital signal processor (DSP) and a WAN driver (80) operating on a processor that is electrically coupled to a memory. The WAN driver (80) receives task allocation requests from a host to open/close communication channels that are handled by the at least one DSP. Each task is allocated to one of the at least one DSP according to a total current task processing load for each of the at least one DSP, a maximum processing capability for each of the at least one DSP, and a processing requirement for each task being allocated to the one of the at least one DSP that can handle the additional processing load of the task being allocated. A configuration controller (92) keeps track of the MIPs processing requirement of each task available for allocation across the plurality of DSPs and the maximum processing capability of each DSP of the plurality of DSPs in response to changes in configuration of the communication system (100).

Abstract: A DSP coprocessor 2 is connected to a host sub-system (3). The host sub-system (3) has a host processor (4), a host RAM (5), and shared RAM banks (6, 7). Multiplexers (11) provide access for either the DSP or the host to a shared RAM bank. Macro commands for functions of the DSP coprocessor are retrieved from the shared RAM banks. This allows comprehensive interaction of the host and the DSP coprocessor.

Abstract: A digital signal processor includes a computation block with an arithmetic logic unit, a multiplier, a shifter and a register file. The computation block includes a plurality of registers for storing instructions and operands in a bit format as a continuous bit stream, and utilizes a bit transfer mechanism for transferring in a single cycle a bit field of an arbitrary bit length between the plurality of registers and the shifter. The plurality of registers may be general purpose registers located in the register file. The register file may further include at least one control information register for storing control information used by the bit transfer mechanism.

Abstract: A novel multi-DSP system allows a main DSP to operate concurrently with an auxiliary DSP for implementing a filter algorithm. The main DSP and auxiliary DSP have separate program memories but share the same data memory. The auxiliary DSP program memory is mapped to the main DSP program memory to allow the main DSP to download filter process instructions from its program memory into the auxiliary DSP program memory. The auxiliary DSP fetches the instructions from its program memory to execute them. The auxiliary DSP is prevented from access to the shared data its program memory when this memory is occupied by the main DSP. An arbitration mechanism gives the auxiliary DSP access to the data memory only when the main DSP is not using this memory.

Abstract: An application specific signal processor (ASSP) performs vectorized and nonvectorized operations. Nonvectorized operations may be performed using a saturated multiplication and accumulation operation. The ASSP includes a serial interface, a buffer memory, a core processor for performing digital signal processing which includes a reduced instruction set computer (RISC) processor and four signal processing units. The four signal processing units execute the digital signal processing algorithms in parallel including the execution of the saturated multiplication and accumulation operation. The ASSP is utilized in telecommunication interface devices such as a gateway. The ASSP is well suited to handling voice and data compression/decompression in telecommunication systems where a packetized network is used to transceive packetized data and voice.

Abstract: A reduced programmable controller for an extensible digital signal processing architecture supports particular instructions to facilitate common digital signal processing operations. These instructions include extract and insert instructions, which are useful in managing the storage and extraction of digital signal processing variables to and from registers, and also useful in assembling fixed-length digital signal parameters from a section of a bitstream stored in a register. These instructions further include leading value detect instructions, including a leading zero detect instruction and a leading one detect instruction which are useful in parsing unique prefix codes such as Huffman codes used in MPEG encoding of video and other variable length codes, and useful in handling of a priority encoder such as a task manager.

Abstract: A microcomputer for feeding source data necessary for operations without any delay while retaining the consistency on instruction lines between the ordinary single operations and the SIMD (Single Instruction Multiple Data) type parallel operations. The microcomputer comprises: a first memory and a second memory adapted to be individually fed with a common address from the address generating unit; a first execution unit coupled to the first memory and the second memory; and a second execution unit coupled to the first memory and the second memory. The second execution unit is mounted together with the central processing unit, the first memory, the second memory and the first execution unit on a common semiconductor substrate.

Abstract: In an information processing apparatus, priorities are assigned to a plurality of central processing units (CPUS) and the CPUs transfer their respective display lists of drawing instructions to a drawing unit on a priority basis. With such a scheme, when a master CPU (Geometry Subsystem 0) is creating a display list (List #0-1) and a drawing unit (a rendering system) is in an idle state, a right to make an access to the drawing unit is handed over to a slave CPU (Geometry Subsystem 1), enabling the slave CPU to supply a display list (List 1-1) created thereby, if any, to the drawing unit. Receiving the display list (List #1-1), the drawing unit starts drawing processing in accordance with List #1-1. As the master CPU completes the creation of the display list (List #0-1), the slave CPU returns the right to make an access to the drawing unit to the master CPU, enabling the master CPU to supply List #0-1 to the drawing unit.

Abstract: The control unit of this invention has a microcode control system or systems for special purpose circuit suitable for specific data processing and a microcode control system for general purpose separately. In addition, the control unit has a fetch unit common for the above control systems. Therefore, in the data processing system having the control unit of this invention, the general purpose process and the process using the special purpose circuit, which is different from the general purpose process, are multiply executed, and synchronizing of this multiprocessing is solved in a instruction level.

Abstract: The present invention provides apparatus and methods which allow music synthesis and audio processing tasks to dynamically scale from a default processor to additional processors in a heterogeneous array of processors in a manner transparent to the user. A router running on one of the processors in the array knows or estimates the load on each processor, and dynamically allocates processing tasks based upon the current load on each processor and its capacity. Processing parameters are shared between all the audio processors to ensure that perceived audio quality is independent of where a task is running.

Abstract: The present invention provides an audio signal processor and method of operation thereof that enables efficient digital signal processing. Fast multiply-accumulate (MAC) and vector processing capabilities are implemented in a RISC architecture giving the high speed capabilities of a digital signal processing system the speed and efficiency of a RISC processor.

Abstract: A single integrated circuit includes first and second data processors operating on different instruction sets independently operating on disjoint programs and data. The single integrated circuit preferably includes an external interface, a shared data transfer controller and shared memory divided into plural independently accessible memory banks. The two data processors are preferably a digital signal processor (DSP) and a reduced instruction set computer (RISC) processor. The DSP and RISC processors are suitably programmed to perform differing aspects of computer image processing.

Abstract: A system is disclosed that includes a plurality of processors, which in some embodiments include DSPs and other microprocessors, and a distributed uniform memory. The distributed uniform memory is subdivided into a plurality of addressable memory spaces each of which are respectively primarily associated with one of the processors in the plurality of processors. At least an addressably contiguous portion of the addressable memory space primarily associated with one processor is mapped into the addressable memory space primarily associated with another processor. Thus, a processor will have access to the addressable memory space primarily associated with another processor, but will have such access independent of the load and timing requirements of the other processors.

Abstract: A data processing system includes a digital signal processor core and a co-processor. The co-processor has a local memory within the address space of the said digital signal processor core. The co-processor responds commands from the digital signal processor core. A direct memory access circuit autonomously transfers data to and from the local memory of the co-processor. Co-processor commands are stored in a command FIFO memory mapped to a predetermined memory address. Control commands includes a receive data synchronism command stalling the co-processor until completion of a memory transfer into the local memory. A send data synchronism command causes the co-processor to signal the direct memory access circuit to trigger memory transfer out of the local memory. An interrupt command causes the co-processor to interrupt the digital signal processor core.

Abstract: A pair of communications adapters each include a number of digital signal processors and network interface circuits for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor. Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: An input/output bus architecture that includes: an input/output bus; an input/output device connected to the input/output bus; a main processor, connected to the input/output bus, for executing a device driver corresponding to the input/output device, the device driver generating load/store commands for the input/output device; and a load/store assist engine, connected to the input/output bus and yet independent of the main processor, for loading/storing data to/from the input/output device according to the load/store commands from the device driver. The load/store assist engine decouples the main processor from latencies associated with execution of the load/store commands. The device driver is reassigned to the main processor, rather than being found in a device that is external to the main processor, such as an input/output processor.

Abstract: A data processing system for processing digital data comprises a first program bus for transferring a unit instruction, a second program bus for transferring a multi instruction consisting of unit instructions, a first program memory connected with said first program bus for storing the unit instruction, a second program memory connected with the second program bus for storing the multi instruction, and a process core for executing the unit or multi instruction fetched. The first and second program memories preferably have different bits widths. The process core includes an instruction input interface circuit for adding NOP instructions to a unit instruction fetched from the first program memory so as to form a multi instruction.

Abstract: An improved PC system that includes a main CPU microprocessor, a file-based operating system, and a DSP microprocessor arranged so that the DSP can execute main CPU operations during time intervals in which the main CPU is otherwise occupied, thereby increasing the bandwidth of the system is provided. This PC system may include multiple CPUs and/or multiple DSPs.

Abstract: An improved PC system that includes a main CPU microprocessor, a file-based operating system, and a DSP microprocessor arranged so that the DSP can execute main CPU operations during time intervals in which the main CPU is otherwise occupied, thereby increasing the bandwidth of the system is provided. This PC system may include multiple CPUs and/or multiple DSPs.

Abstract: Five processing units, namely one data memory, three arithmetic units, and one data memory, are connected together in a cascade arrangement so as to form a single arithmetic pipeline. Likewise, five control devices are connected together in a cascade arrangement and a control signal requesting that a series of data processing operations should start is sent to the first stage control device. Each control device starts to send a micro instruction to a corresponding processing unit upon detection of a processing start request bit in the received control signal and sends a signal which lags the control signal by a delay time equal to a number of cycles required to complete a processing operation of the processing unit, to the next stage control device. The first stage control device is provided with a loop counter operable to count the number of times processing is repeated and automatically generates a processing start request and a processing end request to the next stage control device.

Abstract: On a microprocessor chip mounting a central processing unit (CPU) for controlling the entire operation of electronic equipment and a digital signal processor (DSP) for processing a specific signal in the electronic equipment, an instruction cache for temporarily storing a DSP program and a cache controller are additionally mounted, and the DSP program and a CPU program are stored in an externally provided instruction memory. The cache controller controls the DSP to wait and interrupts the CPU when a cache miss occurs. The CPU executes a predetermined interrupt processing routine so as to supplement an instruction block including the instruction code from the instruction memory to the instruction cache. Thus, an on-chip memory used for storing instruction codes to be decoded and executed by the DSP can be reduced.

Abstract: An improved PC system that includes a main CPU microprocessor, a file-based operating system, and a DSP microprocessor arranged so that the DSP can execute main CPU operations during time intervals in which the main CPU is otherwise occupied, thereby increasing the bandwidth of the system is provided. This PC system may include multiple CPUs and/or multiple DSPs.

Abstract: An interface device between first and second computer busses includes a data input having a first data width, a data output having a second data width different from the first data width, an address input and an address output. The interface device includes constructed on a single integrated circuit parallel FIFOs, a multiplexer circuitry having a first input connected to the output of a first FIFO, a second input connected to the output of a second FIFO, an output and a control input, and an address translation circuit translating first addresses received at the address input into second addresses supplied to the address output. The less significant bit of the address input coupled to the control input of the multiplexer circuitry. The integrated circuit may further include a digital signal processor coupled to said address input and said data input. The two FIFOs are bidirectional and include byte enable outputs.

Abstract: A signal processor includes at least one data source (3), a plurality of input registers (11, 12, 13, 14, . . . ) whose inputs are coupled to the data source by data buses (9, 10), a plurality of multipliers (19, 20; 71, 72 . . . ) for multiplying data buffered in the input registers, and a processing arrangement spread over a plurality of data processor branches (4-0, 4-1, . . . , 4-N) for processing products (p0, p1, . . . ), generated by the multipliers by arithmetic and/or logic operations. For achieving enhanced flexibility of the signal processor and increasing the number of possible applications, multiplexers (15, 16, 17, 18; 70) are provided which are used for coupling the multipliers to a respective part of the input registers in dependence on control signals (I, II, III, IV). Such a signal processor is preferably used in mobile radio technology. Further fields of application are, for example, audio, video, medical and automotive technology, ISDN systems, and digital radio.

Abstract: A data processor of the invention includes plural memories, plural arithmetic units, a data transfer unit and a network. The data transfer unit transfers various data to predetermined memories, and switches the connections between the memories and the arithmetic units by using the network. The control unit adds a processability judgement signal to a data read from a predetermined memory in reading the data, so as to make a pair of the data and the processability judgement signal. Each of the arithmetic units receives the data and the processability judgement signal, conducts predetermined processing on the received data, delays the received processability judgement signal by the number of cycles equal to its own processing cycle, and outputs resultant data obtained through the processing and the delayed processability judgement signal.

Abstract: A communications system includes multiple processors (14, 16) and a protocol timer (18). The protocol timer (18) controls the timing of events in the communications system and operates autonomously after it is loaded with initial instructions by one of the multiple processors (14, 16). The protocol timer (18) utilizes a frame event table (50) and a macro event table (46, 48) to trigger events and to generate interrupts of the multiple processors (14, 16). By allowing the protocol timer (18) to operate autonomously, the processors (14, 16) are relieved of timing control, and can be powered down when not in use, thus reducing power consumption of the communications system. Also, by using the protocol timer (18) to control the timing of events, software related errors and interrupt latencies are reduced.

Abstract: A signal processing apparatus is disclosed which includes a low speed ROM (9) for storing a plurality of signal procedures, a high speed RAM (4) used by a digital signal processor DSP (5), a control processor CPU (8) for transferring a signal procedures from the low speed ROM (9) to the high speed RAM (4), a digital signal processor DSP (5) for processing the signal procedures loaded in the high speed RAM (4). Accordingly, a signal processing apparatus of the present invention is constructed with low cost memory, then reduces manufacturing cost of the apparatus.

Abstract: An application-specific single chip digital processor having flexible design expansion capability with minimal impact on the performance of a processor core. The processor core has an ALU and a register file (accumulators). The output of the ALU is connected to a multiplexer whose output is connected to the input of the register file. The output of the register file connects to one input of the ALU. A function unit, separate from the core, has an input connected to the output of the register file and an output connected to another input to the multiplexer. The core operates with a predefined instruction set. The function unit, which may be redesigned depending on the application, operates with a reserved (uncommitted) instruction set under control of the core.

Abstract: A system in accordance with the invention allows a signal processing system to be configured to perform almost any signal processing function. Such a system includes a redefinable signal processing subsystem and a function-specific module. The system can be defined to perform a particular function by attaching a function-specific module to the redefinable subsystem and downloading function-defining code into the subsystem. The redefinable subsystem includes at least a DSP, a local memory interface, a host interface, and a function module interface. The function-specific module includes at least a subsystem interface, an identifier storage unit, a signal format converter, and a communication adapter. In operation, after a function-specific module is coupled to the subsystem, the subsystem receives a function identifier from the identifier storage unit on the module. The subsystem then requests and receives function-defining code from a host.

Abstract: A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. In a first embodiment, the CPU receives general purpose instructions, such as X86 instructions, wherein certain X86 instruction sequences implement DSP functions. The CPU includes a processor mode register which is written with one or more processor mode bits to indicate whether an instruction sequence implements a DSP function. The CPU also includes an intelligent DSP function decoder or preprocessor which examines the processor mode bits and determines if a DSP function is being executed. If a DSP function is being implemented by an instruction sequence, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction.

Abstract: A signal processing apparatus executes a plurality of microprograms stored in a microprogram memory device in a time-sharing manner, so as to perform arithmetic operations on a digital signal entered by a signal input device. A delay memory device that delays the digital signal. The delay memory device has a plurality of delay areas that are independently provided for the respective microprograms, such that each of the microprograms that is being executed uses a corresponding one of the plurality of delay areas so as to delay the digital signal, and a common area that can be accessed by all of the microprograms. As a result, data such as tables for use in common by the plurality of microprograms can be stored, and the stored data can be easily used by each microprogram, without making the system complicated or increasing the cost of the apparatus.

Abstract: Buffers 101 and 103 are provided in an input and an output of a signal processing circuit 102 for performing a data transformation between a first digital data signal and a second digital data signal, respectively, and data of one of the first and second digital data signals is interpolated by a data interpolation circuit 106 on the basis of a deviation between sampling frequencies of the first and second digital data signals detected by an out-of-sync detection circuit 104 on the basis of two clocks driving the buffers 101 and 103. Further, an amount of jitter between the two clocks driving the respective buffers 101 and 103 is detected by a jitter detection circuit 105 and the amount of interpolation data is controlled in the data interpolation circuit 106 on the basis of the amount of jitter.

Abstract: An audio information processing subsystem 200 is disclosed which includes a stream processor 100 for simultaneously processing multiple streams of audio data. Processing subsystem 200 also includes a program memory 202 coupled to stream processor 100 for storing instructions for controlling processing system 200 and a data memory 203/204 also coupled to stream processor 100. Additionally, a direct memory access circuitry 208 is provided for controlling direct memory accesses to a selected one of program memory 202 and data memory 203/204.

Abstract: A first register stores a value that can be used as a pointer to indirectly address a second register. The first register is referred to as a pointer register and the pointer as a register pointer. The second register may be a conventional register that stores a conventional register value (i.e., a data value or a pointer to a data value stored in external memory) or another pointer register. In certain embodiments, a pointer register can also be used to store conventional register values. Pointer registers of the present invention can be used to implement efficiently certain types of digital processing, such as circular buffers, vector processing, convolutional processing, and partitioned processing, using data in registers rather than memory.

Abstract: A method and apparatus for coupling an External Device to a Host Computer, such that program code to be executed by the external device may be stored in the Host Computer memory and yet be essentially independent of the Host Computer. Hardware and software enable the logical displacement of a program and address bus across inter-processor interfaces. An External Device preferably provides direct access to program code stored within Host Computer memory by means of a conventional DMA function. Program code which is to be executed by the External Processor within the External Device is transferred from the Host Memory to an Instruction Buffer memory within the External Device. The External Processor determines when to request additional instructions from the Host Memory over the DMA channel on a timed interrupt basis.

Abstract: A circuit arrangement and method utilize a distributed extensible processing architecture to allocate various DSP functions or operations between multiple processing cores disposed on an integrated circuit device. Each processing core includes one or more hardwired datapaths to provide one or more DSP operations. Moreover, each processing core includes a programmable controller that controls the operation of each hardwired datapath via a local computer program executed by the controller. Furthermore, the processing cores are coupled to one another over a communications bus to permit data to be passed between the cores and thereby permit multiple DSP operations to be performed on data supplied to the device.

Abstract: A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. In a first embodiment, the CPU receives general purpose instructions, such as X86 instructions, wherein certain X86 instruction sequences implement DSP functions. The CPU includes a processor mode register which is written with one or more processor mode bits to indicate whether an instruction sequence implements a DSP function. The CPU also includes an intelligent DSP function decoder or preprocessor which examines the processor mode bits and determines if a DSP function is being executed. If a DSP function is being implemented by an instruction sequence, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction.

Abstract: The present invention comprises an architecture that involves an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a micro-controller interface, a DSP operating system (OS), a data flow model, and an interface for hardware blocks. The design allows software to control much of the configuration of the architecture while using hardware to provide efficient data flow, signal processing, and memory access. In devices with embedded DSPs, memory access is often the bottleneck and is tightly coupled to the efficiency of the design. The platform architecture involves a method that allows the sharing of the DSP memory with other custom hardware blocks or the micro-controller. The DSP can operate at full millions-of-instructions-per-second (MIPS) while another function is transferring data to and from memory. This allows for an efficient use of the memory and for a partitioning of the DSP tasks between software and hardware.

Abstract: A computer system for performing distributed processing, particularly of digital audio data, is disclosed. The system has a number of digital signal processors linked to a host computer through a time division multiplex bus. The system includes means for assigning to a particular processor a specific processing task or tasks, as well as a means for assigning additional specific processing tasks to that same processor to maximize its use. When the processor performing a specific processing task has reached its capacity, the system assigns a new processor to perform that task. To enhance the efficiency of the processor to perform the specific processing task, the processor cyclically runs a specific set of instructions for performing that specific processing task, and waits for the system to send it digital data to be processed.