Abstract: A method for learning and detecting an abnormal part of a device through artificial intelligence comprises: an information collection step for collecting a current waveform of a current value that changes over time in a driving state of at least one device and collecting information about a faulty part of the device, together with current waveform information before a fault occurs in the device; a model setting step for learning, by a control unit, information collected in the information collection step and setting a reference model of a current waveform for each faulty part of the device; and a detection step for, when an abnormal symptom of the device is detected in a real-time driving state, comparing, by the control unit, a real-time current waveform of the device and the reference model, and detecting and providing an abnormal part regarding the abnormal symptom of the device.

Abstract: In response to identifying one or more applications on a computing device, terms and conditions associated with the one or more applications are identified. A knowledge base based on the identified terms and conditions is generated. The knowledge base includes a determination of sensitive information of a user required by each of the identified one or more applications. Secondary associations of the identified one or more applications are identified from a plurality of external data sources with information related to the identified one or more applications. In response to identifying the secondary associations, it is determined whether sensitive information about the user is found in one or more of the identified secondary associations. In response to determining that sensitive information about the user is found, an advisory is transmitted to the user.

Abstract: A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

Abstract: Techniques are disclosed relating to floating-point circuitry configured to perform a corner check instruction for a floating-point power operation. In some embodiments, the power operation is performed by executing multiple instructions, including one or more instructions specify to generate an initial power result of a first input raised to the power of a second input as 2(second input*log2(first input)). In some embodiments, the corner check instruction operates on the first and second inputs and outputs output a corrected power result based on detection of a corner condition for the first and second inputs. Corner check circuitry may share circuits with other datapaths. In various embodiments, the disclosed techniques may reduce code size and power consumption for the power operation.

Abstract: A method is provided that includes performing, by a processor in response to a vector permutation instruction, permutation of values stored in lanes of a vector to generate a permuted vector, wherein the permutation is responsive to a control storage location storing permute control input for each lane of the permuted vector, wherein the permute control input corresponding to each lane of the permuted vector indicates a value to be stored in the lane of the permuted vector, wherein the permute control input for at least one lane of the permuted vector indicates a value of a selected lane of the vector is to be stored in the at least one lane, and storing the permuted vector in a storage location indicated by an operand of the vector permutation instruction.

Abstract: An aircraft includes an electrical system and an electronic controller. The electronic controller includes a main processor and a multi-core processor. The multi-core processor includes a control core in signal communication with the electrical system, and one or more prognostics cores configured to process and analyze prognostics and diagnostics data of the electrical system independently from operation of the control core. A wireless device is in signal communication with one or more of the prognostics cores to receive the prognostics and diagnostics data therefrom. The aircraft further includes a prognostics and health monitoring (PHM) system located remotely from the electronic controller. The PHM system is configured to wirelessly receive the prognostics and diagnostics data from the wireless device.

Abstract: A method, a computer program product and a system are provided. A case expression is analyzed for redundant expressions, patterns equivalent to a built-in function, and specific functions to form a simplified expression, wherein the case expression is written in a language supported by a database management system. The simplified expression is optimized based on a cost benefit evaluation of no optimization, native code generation, hashing inputs, and a results caching algorithm to form an execution plan. The execution plan is utilized in the database management system for the case expression.

Abstract: A method is provided that includes performing, by a processor in response to a vector permutation instruction, permutation of values stored in lanes of a vector to generate a permuted vector, wherein the permutation is responsive to a control storage location storing permute control input for each lane of the permuted vector, wherein the permute control input corresponding to each lane of the permuted vector indicates a value to be stored in the lane of the permuted vector, wherein the permute control input for at least one lane of the permuted vector indicates a value of a selected lane of the vector is to be stored in the at least one lane, and storing the permuted vector in a storage location indicated by an operand of the vector permutation instruction.

Abstract: The disclosure relates to an apparatus for encoding an input audio signal, wherein the input audio signal comprises a plurality of input audio channels. The apparatus comprises a KLT-based pre-processor configured to transform the plurality of input audio channels into a plurality of eigenchannels and to provide metadata in the form of a plurality of metadata elements, wherein the metadata allows reconstructing the plurality of input audio channels on the basis of the plurality of eigenchannels, a metadata re-arrangement unit configured to re-arrange the plurality of metadata elements on the basis of a re-arrangement scheme into one or more metadata blocks, wherein each of the one or more metadata blocks is a multi-dimensional array, and a metadata encoder configured to encode each of the one or more metadata blocks.

Abstract: The invention provides a method and system for monitoring one or more properties of an asset such as a long distance pipeline using a plurality of mobile sensor nodes. The method includes generating a time-based schedule for the plurality of mobile sensor nodes for monitoring the one or more properties of the asset, wherein the time-based schedule defines a time slot corresponding to a mobile sensor node to perform a data collection operation. The data collection operation is then initiated at a first mobile sensor node of the plurality of mobile sensor nodes based on a first time slot as defined in the time-based schedule. The data collection operation of the first mobile sensor node is then managed based on the time-based schedule and an energy status of the first mobile sensor node. Finally, the data pertaining to the one or more properties of the asset is collected from the plurality of mobile sensor nodes.

Abstract: An integrated controller for motion control and motor control comprises a first processor, a second processor, a cache and a shared memory. The first processor is configured to run an operating system and at least perform motion control. The second processor is configured to at least perform motor control and normally not run the operating system. The cache is coupled to the first processor and the second processor. The shared memory maps onto the cache. The first processor and the second processor are configured to share the shared memory and accordingly perform data transmission via the cache during the periods of motion control and motor control. The first processor, the second processor and the cache are integrated in a same chip.

Abstract: Disclosed are methods, devices and systems for all-in-one signal processing, linear and non-linear vector arithmetic accelerator. The accelerator, which in some implementations can operate as a companion co-processor and accelerator to a main system, can be configured to perform various linear and non-linear arithmetic operations, and is customized to provide shorter execution times and fewer task operations for corresponding arithmetic vector operation, thereby providing an overall energy saving. The compact accelerator can be implemented in devices in which energy consumption and footprint of the electronic circuits are important, such as in Internet of Things (IoT) devices, in sensors and as part of artificial intelligence systems.

Abstract: A computer-implemented method is provided for hiding overheads on a parallel computing platform. The computer-implemented method includes loading a first kernel overhead and a second kernel overhead in a queue of a second thread, and loading a dummy kernel overhead between the first and second kernel overheads in the queue of second thread. The computer-implemented method further includes loading a waiting process in the queue of a first thread, the waiting process remaining active until a previous kernel of the first and second kernel overheads ends. The computer-implemented method furthers include allocating memory copy overheads related to the previous kernel in the queue of the first thread and allocating a stop process in the queue of the first thread, the stop process configured to stop a dummy kernel, the dummy kernel related to the dummy kernel overhead.

Abstract: Method and system are provided for software application execution including switching between optimized code for use profiles. The method includes: accessing an application having multiple executables for the same function for multiple use profiles. The method includes: executing code for a first use profile; receiving a prompt to change to a second use profile; suspending the execution of the code for the first use profile; retrieving switching code from a pre-computed data structure, wherein the switching code is for carrying out operations to transfer from executing code for a first use profile to executing code for a second use profile; performing the operations of the switching code; and resuming executing the application by executing code for the second use profile.

Abstract: Systems and methods for forecasting events can be provided. A measurement database can store sensor measurements, each having been provided by a non-portable electronic device with a primary purpose unrelated to collecting measurements from a type of sensor that collected the measurement. A measurement set identifier can select a set of measurements. The electronic devices associated with the set of measurements can be in close geographical proximity relative to their geographical proximity to other devices. An inter-device correlator can access the set and collectively analyze the measurements. An event detector can determine whether an event occurred. An event forecaster can forecast a future event property. An alert engine can identify one or more entities to be alerted of the future event property, generate at least one alert identifying the future event property, and transmit the at least one alert to the identified one or more entities.

Abstract: The overall architecture and details of a scalable video fingerprinting and identification system that is robust with respect to many classes of video distortions is described. In this system, a fingerprint for a piece of multimedia content is composed of a number of compact signatures, along with traversal hash signatures and associated metadata. Numerical descriptors are generated for features found in a multimedia clip, signatures are generated from these descriptors, and a reference signature database is constructed from these signatures. Query signatures are also generated for a query multimedia clip. These query signatures are searched against the reference database using a fast similarity search procedure, to produce a candidate list of matching signatures. This candidate list is further analyzed to find the most likely reference matches. Signature correlation is performed between the likely reference matches and the query clip to improve detection accuracy.

Abstract: A network device enables browsing of a plurality of pre-defined VMs associated with IoT devices. The network device receives, from a user device, selection of a first pre-defined VM from the plurality of pre-defined VMs, wherein the first pre-defined VM includes at least one first device state and at least one first sensor type, and receives, from the user device, instructions to modify the first pre-defined VM, by adding an additional device state or an additional sensor type to the first pre-defined VM or by removing the at least one first device state or the at least one first sensor type from the first pre-defined VM, to create a first customized VM associated with a first physical IoT device. The network device stores the first customized VM in a database, and uses the first customized VM for accessing or controlling the first physical IoT device.

Abstract: A method and a device are provided for waking up a MCU. The method includes: determining whether a second MCU is in a deep sleep state, when a first MCU triggers a communication event of transmitting data to the second MCU; and when the second MCU is in the deep sleep state, sending an interrupt wakeup signal to the second MCU via a wakeup pin connected between the first MCU and the second MCU, so as to wake up the second MCU.

Abstract: A method for assigning relative order to messages by using vector clocks under a distributed server environment is disclosed. The method includes the steps of: (a) a server assigning a vector clock to a message and storing the message to which the vector clock is assigned if the message required to be assigned relative order is acquired through a network; and (b) the server transmitting an increased vector clock to one or more other servers connected with itself through the network and supporting said other servers to update their vector clocks by referring to the increased vector clock.

Abstract: This document discusses systems and methods that track overall time for processing operations such that the processing time can be shared among the resources efficiently. Processing time can be shifted to image processing to provide the most benefit to image quality. Moreover, access time from one process is banked to be used by a subsequent process or on a subsequent group of pixels. This document discusses systems and methods that provide additional processing power on an as needed basis. For example, a processing stage and its controller are outside the normal pixel processing flow path. When it is determined that additional processing is required, the processing stage and its controller are activated to perform the additional processing. This document discusses systems and methods that provide parallel processing in a processing stage such that the data can flow internal to the controller linked to the processing stage and globally.

Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.

Abstract: According to an embodiment, an information processing apparatus includes: an acquiring unit that acquires a job list in which a job, authorization information expressing authorization over a process of a job, and level of priority of the job are associated with one another; and an output unit that outputs preferentially a job with high level of the priority over a job with low level of the priority.

Abstract: A server is deployed on a network and manages operation of a plurality of server instances each with a virtual frame buffer. A client establishes a connection with the server at a start of a session. The server allocates a server instance to the client and a user interface application renders a corresponding graphical user interface to the virtual frame buffer of the allocated server instance. The server forwards updates of the graphical user interface from the virtual frame buffer to the client, where at least some of the updates include transparency information for blending the graphical user interface with additional visual information at the client. When the session is complete the server reclaims the server instance allocated to the client. In-room device requirements in guest rooms of a hospitality establishment are thereby minimized while providing enhanced user interface performance. Locations in other applications include private residences and businesses.

Abstract: One or more techniques and/or systems are disclosed for high fidelity conversion of a document to a less rich format. A bounding area can be identified in the document that comprises an unsupported element, and/or a blending of elements that is not supported in the less rich format. The bounding area that comprises the unsupported element(s) can be rasterized, by creating an image and identifying raster data for the image. Those elements in the document that are outside the bounding area are not rasterized, and their vector data-based format is retained in the converted document.

Abstract: A data processing apparatus includes a connecting unit that distributes the plurality of processing modules over the stages, and connects the plurality of processing modules such that a plurality of partial data are processed in parallel. The data processing apparatus detects, with respect to at least a part of the stages, a ratio of an amount of data for which processing in the subsequent stage has been executed, as a passage rate, acquires a processing time for a data amount to be processed in each stage, for which the passage rate was detected, based on the passage rate, and determines the number of processing modules distributed to each stage based on the data amount.

Abstract: A high performance computing system is provided with an ASIC that communicates with another device in the system according to a protocol defined by the other device. The ASIC is coupled to a reconfigurable protocol table, in the form of a high speed content-addressable memory (“CAM”). The CAM includes instructions to control the execution of the protocol by the ASIC. The CAM may include instructions to control the ASIC in the event that unanticipated signals or other errors are encountered while executing the protocol. Internal ASIC state data may be routed to the CAM to permit the ASIC to generate a reasonable response to errors either in the design or fabrication of the ASIC or the device with which it is communicating.

Abstract: A data processing apparatus comprises a primary processor, a secondary processor configured to perform secure data processing operations and non-secure data processing operations and a memory configured to store secure data used by the secondary processor when performing the secure data processing operations and configured to store non-secure data used by the secondary processor when performing the non-secure data processing operations, wherein the secure data cannot be accessed by the non-secure data processing operations, wherein the secondary processor comprises a memory management unit configured to administer accesses to the memory from the secondary processor, the memory management unit configured to perform translations between virtual memory addresses used by the secondary processor and physical memory addresses used by the memory, wherein the translations are configured in dependence on a page table base address, the page table base address identifying a storage location in the memory of a set of des

Abstract: One embodiment of the present includes a heterogeneous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.

Abstract: A high performance computing system is provided with an ASIC that communicates with another device in the system according to a protocol defined by the other device. The ASIC is coupled to a reconfigurable protocol table, in the form of a high speed content-addressable memory (“CAM”). The CAM includes instructions to control the execution of the protocol by the ASIC. The CAM may include instructions to control the ASIC in the event that unanticipated signals or other errors are encountered while executing the protocol. Internal ASIC state data may be routed to the CAM to permit the ASIC to generate a reasonable response to errors either in the design or fabrication of the ASIC or the device with which it is communicating.

Abstract: A circuit arrangement, method, and program product for dynamically providing a status of a hardware thread/hardware resource independent of the operation of the hardware thread/hardware resource using an inter-thread communication protocol. A master hardware thread may be configured to communicate status requests to associated slave hardware threads and/or hardware resources. Each slave hardware thread/hardware resource may be configured with hardware logic configured to automatically determine status information for the slave hardware thread/hardware resource and communicate a status response to the master hardware thread independent of the operation of the slave hardware thread/hardware resource.

Abstract: A method and circuit arrangement tightly couple together decode logic associated with multiple types of execution units and having varying priorities to enable instructions that are decoded as valid instructions for multiple types of execution units to be forwarded to a highest priority type of execution unit among the multiple types of execution units. Among other benefits, when an auxiliary execution unit is coupled to a general purpose processing core with the decode logic for the auxiliary execution unit tightly coupled with the decode logic for the general purpose processing core, the auxiliary execution unit may be used to effectively overlay new functionality for an existing instruction that is normally executed by the general purpose processing core, e.g., to patch a design flaw in the general purpose processing core or to provide improved performance for specialized applications.

Abstract: In one embodiment, a fabric of a processor such as a system on a chip includes at least one data buffer including a plurality of entries each to store data to be transferred to and from a plurality of agents and to and from a memory, a request tracker to maintain track of pending requests to be output to an ordered domain of the fabric, and an output throttle logic to control allocation into the ordered domain between write transactions from a core agent and read completion transactions from the memory. Other embodiments are described and claimed.

Abstract: An information processing system has a power supply section which detects a predetermined potential applied to a USB terminal and supplying the potential as a source potential, an information detection section which detects the predetermined information supplied to the USB terminal, and a processing section which executes, subsequent to the detection of the predetermined potential, the encoding process or the decoding process in accordance with at least the operating information supplied from the operation key arranged on the body and in accordance with the predetermined information supplied to the USB terminal after detection of the predetermined information. The recording and reproducing operation can be performed with the operating key on the body with power supplied only from the USB terminal.

Abstract: A system for performing finite input response filtering. The system includes an array of random access memories (RAMs) for storing at least one two-dimensional (2D) block of pixel data. The pixel data is stored such that one of each type of column or row from the 2D block of pixel data is stored per RAM. A control block provides address translation between the 2D block of pixel data and corresponding addresses in the array of RAMs. An input crossbar writes pixel data to the array of RAMs as directed by the control block. An output crossbar simultaneously reads pixel data from each of the array of RAMs and passes the data to an appropriate replicated data path, as directed by the control block. A single instruction multiple data path block includes a plurality of replicated data paths for simultaneously performing the FIR filtering, as directed by the control block.

Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers.

Abstract: A processor has a plurality of PEs (processing elements) that operate in parallel based on operation commands and an information collection unit that collects the data of the plurality of PEs, wherein each of the plurality of PEs holds data and a condition flag, supplies the data and the condition flag to the information collection unit upon receiving an operation command, and upon receiving an update request for updating the condition flag, updates the condition flag in accordance with the update request that was received; and the information collection unit, upon receiving the data and the condition flags, selects one PE based on a predetermined order of priority from among the PEs for which the received condition flags are active and both supplies the data of the selected PE as collection result data and supplies an update request for updating the condition flag of the PE that was selected.

Abstract: A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.

Abstract: Self-similar processing by unit processing cells may together solve a problem. A unit processing cell may include a processor, a memory and a plurality of Input/Output (IO) channels coupled to the processor. The memory may include a dictionary having one or more instructions that configure the processor to perform at least one function. The plurality of IO channels may be used to communicably couple the unit processing cell with a plurality of other unit processing cells each including their own respective dictionary. The processor may update the dictionary so that the unit processing cell builds a different dictionary from the plurality of other unit processing cells, thereby being self-similar to the plurality of other unit processing cells.

Abstract: A data acquisition system includes an analog-to-digital converter (ADC) having a MUX control outputs, a controller coupled to the ADC, a multiplexer coupled to the MUX control outputs of the ADC, and an operational amplifier coupling an analog data output of the multiplexer to an input of the ADC. An ADC having integrated multiplexer control includes control logic circuitry, ADC circuitry, MUX logic and an oscillator coupled to the control logic circuitry, the ADC circuitry, and the MUX logic.

Abstract: An apparatus includes a processor to determine an extremum among a series of values that are successively provided to a first register and a second register. The processor is configured to execute a single cycle search instruction, including compare a value in the first register with a value in a first accumulator, and store an extremum of the two values in the first accumulator; and compare a value in the second register with a value in a second accumulator, and store an extremum of the two values in the second accumulator. The processor is configured to execute a single cycle select instruction, including compare the value in the first accumulator with the value in the second accumulator, and store an extremum of the two values in the first accumulator, the extremum stored in the first accumulator representing the extremum of the series of numbers.

Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers.

Abstract: A device including a data analysis element including a plurality of memory cells. The memory cells analyze at least a portion of a data stream and output a result of the analysis. The device also includes a detection cell. The detection cell includes an AND gate. The AND gate receives result of the analysis as a first input. The detection cell also includes a D-flip flop including an output coupled to a second input of the AND gate.

Abstract: A programmable filter processor which is adaptable to different filtering algorithms, a plurality of different software algorithms being executable, the programmable filter processor including a logic unit which includes a plurality of pipeline stages; a first memory in which the software algorithms are stored; a second memory in which raw data and parameters for the different filter algorithms are stored; and an address generating unit which is controllable via a program counter, the address generating unit being developed to generate control commands for the second memory and the logic unit.

Abstract: An image processing system includes a first image processor that reads out a first image written in a main memory to apply a first process to the first image and write in the main memory as a second image, a second image processor that reads out a second image written in the main memory to apply a second process to the second image and write in the main memory as a second image, and an address snooping apparatus that snoops an address of the image written in the main memory to start the first process when the address is indicated to a previously set first value and start the second process when the address is indicated to a previously set second value, effectively enabling synchronization between a process by a CPU or a special purpose processor and a data delivery/receipt process between pipeline stages.

Abstract: An arithmetic processing apparatus includes an operation circuit group that performs encryption and a redundant operation circuit group configured the same as the operation circuit group. The arithmetic processing apparatus, while performing encryption, performs normal encryption in the operation circuit group, and performs an encryption mask processing program by using data and the like randomly generated by a random data generating unit and the like in the redundant operation circuit group. The arithmetic processing apparatus, when not performing encryption, performs normal arithmetic processing in the redundant operation circuit group.

Abstract: One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.

Abstract: A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using available processing resources to produce resulting data, and the resulting data is passed to an input/output device.

Abstract: Systems, methods, and computer software for operating a device can be used to operate the device in multiple modes. The device can be operated in a first operating mode adapted for processing data, in which a first processor executes a driver for a nonvolatile memory and a second processor performs processing of data stored in files on the nonvolatile memory. An instruction can be received to switch the device to a second operating mode adapted for reading and/or writing files from or to the nonvolatile memory. The driver for the nonvolatile memory can be switched from the first processor to the second processor in response to the instruction, and the driver for the nonvolatile memory can be executed on the second processor after performing the switch. A communications driver can be executed on the first processor in response to the instruction to switch the device to the second operating mode.

Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

Abstract: An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output and memory access operations tasks into a compute intensive part that is handled by the processor and an I/O or memory intensive part that is then handled by the input/output processor. An input/output processor is designed by analyzing common input/output and memory access patterns and implementing methods tailored to efficiently handle those commonly occurring patterns. One technique that an input/output processor may use is to divide memory tasks into high frequency or high-availability components and low frequency or low-availability components.