Abstract: A reconfigurable FADEC includes a reconfigurable CPU configured for performing digital computing functions. A reconfigurable MSPD communicates with the CPU and is configured for performing analog I/O functions. A data bus is coupled to the CPU and the MSPD. The data bus is configured for connecting the CPU and the MSPD to an external connector.

Abstract: A companion chip for a microcontroller has a microprocessor bus domain and a peripheral module bus domain, which are connected to each other via a bus bridge. The microprocessor bus domain includes at least one microprocessor core, and the peripheral module bus domain includes at least one global time-management module as well as modules for communication with the outside world and for signal processing. The companion chip further includes at least one FIFO module for transmitting data within the chip, and between the chip and the microcontroller, and a management module connected to the FIFO module, which ensures the consistency of the data by associating a respective time value and/or an angle of rotation.

Abstract: A processor including a Boolean logic unit, wherein the Boolean logic unit is operated for performing the short-circuit evaluation of a Normal Form Boolean expression/operation, a plurality of input/output interfaces in communication with the Boolean logic unit, wherein the plurality of input/output interfaces are operated for receiving a plurality of compiled Boolean expressions/operations and transmitting a plurality of compiled results, and a plurality of registers coupled to the plurality of input/output interface circuits, wherein the plurality of multi-bit registers include an instruction register, a first address register and a second address register.

Abstract: A multi-core processor system including a main processor, an internal EPON bus, and a plurality of secondary core processors. The main processor includes a processing unit; an offload engine operatively connected to the processing unit for routing data to and from the processing unit; a plurality of main processor optical network units (ONU's) operatively connected to the offload engine; and, a dual optical line terminal (OLT) operatively connected to the offload engine. The internal EPON bus is operatively connected to the OLT. The plurality of secondary core processors are located physically separate from the main processor, each secondary core processor having a respective secondary core processor ONU being operatively connected to the main processor via the internal EPON bus.

Abstract: A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine, and the ACU command include instruction memory addresses corresponding to an address in an array control unit where processing array instructions are stored.

Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

Abstract: Controlling a motion system using a plurality of processors. First input data may be received which corresponds to a first portion of the motion system. Second input data may be received which corresponds to a second portion of the motion system. Execution of a first function of a plurality of sequential functions may be assigned to a first processor to determine output for the first portion based on the first input data. Execution of the first function may be assigned to a second processor to determine output for the second portion based on the second input data. The first processor executing the first function and the second processor executing the first function may be performed in parallel. The output for the first portion of the motion system may be provided to the first portion. The output for the second portion of the motion system may be provided to the second portion.

Abstract: A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency.

Abstract: Techniques are described that enable restoring interrupted program execution from a checkpoint without the need for cooperation from the computer's operating system. These techniques can be implemented by modifying existing code using an automated tool that adds instructions for enabling restoring interrupted program execution.

Abstract: The invention relates to a control device for lubrication systems, having a control processor which is arranged in a housing, having connections, which are formed on the housing, for sensor inputs and control outputs, which are connected to the control processor, and having an operator interface which is secured to the outside of the housing and is intended to input control parameters. Provision is made for the control processor to be set up with different control programs for different lubrication systems and for program switches for selecting the different control programs to be arranged inside the housing.

Abstract: A method providing simple fine-grain hardware primitives with which software engineers can efficiently implement enforceable separation of programs into modules and constraints on control flow, thereby providing fine-grain locality of causality to the world of software. Additionally, a mechanism is provided to mark some modules, or parts thereof, as having kernel privileges and thereby allows the provision of kernel services through normal function calls, obviating the expensive prior art mechanism of system calls. Together with software changes, Object Oriented encapsulation semantics and control flow integrity in hardware are enforced.

Abstract: One embodiment of the invention includes a quantum processor system. The quantum processor system includes a first resonator having a first characteristic frequency and a second resonator having a second characteristic frequency greater than the first characteristic frequency. A qubit cell is coupled to each of the first resonator and the second resonator. The qubit cell has a frequency tunable over a range of frequencies including the first characteristic frequency and the second characteristic frequency. A classical control mechanism is configured to tune the frequency of the qubit cell as to transfer quantum information between the first resonator and the second resonator.

Abstract: Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

Abstract: A timing module and a microcontroller. An independent processing unit, which is provided as a component of at least one closed-loop control circuit, is integrated in the timing module.

Abstract: A data processing architecture includes an input device that receives an incoming stream of data packets. A plurality of processing elements are operable to process data received from the input device. The input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.

Abstract: Certain exemplary embodiments can provide a programmable logic controller, which can comprise a Reduced Instruction Set Computer (RISC) processor. The RISC processor can be adapted to, responsive to a received request to process a Boolean operation, execute a single processor data access instruction addressed to a region of a memory-mapped register corresponding to the Boolean operation.

Abstract: A reconfigurable circuit includes a network circuit for controlling connections between the output terminal and the input terminal of an arithmetic unit group, and a first selector connected between the arithmetic unit group and the network circuit. When a first control signal is in a first state, the first selector connects a first terminal of the arithmetic unit group to a first terminal of the network circuit, and also connects a second terminal of the arithmetic unit group to a second terminal of the network circuit. Meanwhile, when the first control signal is in a second state, the first selector connects the first terminal of the arithmetic unit group to the second terminal of the network circuit, and also connects the second terminal of the arithmetic unit group to the first terminal of the network circuit.

Abstract: In a first data delivery apparatus, a user-input receiving unit receives data and a request for executing a workflow, a first data processing unit processes the data based on the workflow, a destination obtaining unit obtains a destination from the workflow, and a transferring unit transfers the data, the workflow, and a progress of the workflow to the destination. In a second data delivery apparatus, a transfer receiving unit receives the data, the workflow, and the progress of the workflow, a workflow executing unit executes the workflow from a non-executed part based on the progress of the workflow, and a data delivery unit delivers data to other destination.

Abstract: A digital system and method of operating the same. The system comprises a processor chip including a first elastic interface domain, wherein the first elastic interface domain comprises a first processor X logic and a first processor Y logic, wherein the first processor X and Y logic comprise first X and Y latches, respectively; and a first ASIC chip electrically coupled to the processor chip, wherein the first processor X and Y logics are configured to be simultaneously in a functional mode, wherein the first processor X logic is configured to switch from the functional mode to a scanning mode while the first processor Y logic remains in the functional mode, and wherein in response to the first processor Y logic being in the functional mode, the first processor Y logic is configured to generate a first reference ASIC clock signal to the first ASIC chip.

Abstract: The present invention provides histogram calculation for images and video applications using a SIMD and VLIW processor with vector Look-Up Table (LUT) operations. This provides a speed up of histogram calculation by a factor of N times over a scalar processor where the SIMD processor could perform N LUT operations per instruction. Histogram operation is partitioned into a vector LUT operation, followed by vector increment, vector LUT update, and at the end by reduction of vector histogram components. The present invention could be used for intensity, RGBA, YUV, and other type of multi-component images.

Abstract: An application-specific integrated circuit (ASIC) comprising a plurality of channels, each channel having circuitry for time and energy discrimination, a plurality of programmable registers, each programmable register configured to output at least one configuration parameter for the circuitry, and a channel-select register configured to identify a channel of the plurality of channels to be configured. The ASIC further includes a configuration-select register configured to identify the programmable register to be used for channel configuration, and a communications interface configured to transmit instructions received from a controller to one of the channel-select register, the configuration-select register, and the plurality of programmable registers.

Abstract: A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. Packet conversion may additionally entail converting packets generated according to a first protocol version level and processing the said packets to implement protocol conversion for generating converted packets according to a second protocol version level, but within the same protocol family type.

Abstract: Disclosed herein is a video decoding system of a mobile broadcasting receiver. The video decoding system of a mobile broadcasting receiver for decoding a compression-coded video signal includes: at least one buffer memory for performing video decoding; a plurality of coprocessors including a data processing unit partitioned into one or more hardware blocks, wherein the data processing unit performs actual video decoding via data input/output from/to the buffer memory; and a DMA (Direct Memory Access) coprocessor for performing a direct access operation to an external memory, wherein, the at least one buffer memory, the plurality of coprocessors and the DMA coprocessor take the form of hardware, and operations thereof are controlled via software in a processor.

Abstract: An application process to process communication system is provided in which seamless communication between onboard processes and off-board processes are provided. The off-board processes are typically remote and/or mobile relative to the onboard processes in which a central process maintains communication between the processes.

Abstract: A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using the available processing resources to produce resulting data, and the resulting data is passed to an input/output device.

Abstract: Techniques for utilizing processor cores include sequestering processor cores for use independently from an operating system. In at least one embodiment of the invention, a method includes executing an operating system on a first subset of cores including one or more cores of a plurality of cores of a computer system. The operating system executes as a guest under control of a virtual machine monitor. The method includes executing work for an application on a second subset of cores including one or more cores of the plurality of cores. The first and second subsets of cores are mutually exclusive and the second subset of cores is not visible to the operating system. In at least one embodiment, the method includes sequestering the second subset of cores from the operating system.

Abstract: Programmable on-chip identification circuitry and associated method are disclosed that provide integrated circuits with the ability to select and report from multiple different vendor and system identification configurations. The integrated circuit device includes programmable circuitry that utilizes vendor identification, system identification, configuration or other device information provided or selected at least in part based upon selection information from a source external to the integrated circuit. The selection information may be provided through one or more externally generated digital and/or analog control signals that are then processed within the integrated circuit device to select, access and utilize desired identification information stored in an on-chip database.

Abstract: A processor generation system includes the ability to describe processors with three instruction sizes. In one example implementation, instructions can be 16-, 24- and 64-bits. This enables a new range of architectures that can exploit parallelism in architectures. In particular, this enables the generation of VLIW architectures. According to another aspect, the processor generator allows a designer to add a configurable number of load/store units to the processor. In order to accommodate multiple load/store units, local memories connected to the processor can have multiple read and write ports (one for each load/store unit). This further allows the local memories to be connected in any arbitrary connection topology. Connection box hardware is automatically generated that provides an interface between the load/store units and the local memories based on the configuration.

Abstract: An input/output system transfers data packets to and from a SIMD array of processing elements (PEs) such that different sizes of data packets are transferred to respective ones of the PEs. The packets are transferred in batches to respective different addresses in the array under the control of the PEs. Transfer to or from the array may be carried out when either a batch or part of a batch is ready for transfer. The decision to transfer either full or part batches is made in dependence upon the speed of the PEs and the speed and intermittency of the data packets.

Abstract: In general, in one aspect, a processing unit includes an input buffer to store data received by the processing unit, a memory, an arithmetic logic unit coupled to the input buffer and to the memory, an output buffer; and control logic having access to a control store of program instructions, the control logic to process instructions including an instruction to transfer data from the input buffer to the memory and an instruction to cause the arithmetic logic unit to perform an operation on operands provided by at least one of the memory and the input buffer, the instruction to output results of the operation to at least one of the memory and the output buffer.

Abstract: A multiprocessor system comprises first and second processors connected to a multi-port semiconductor memory device. The multi-port semiconductor memory device comprises a shared memory area and a plurality of mailbox areas used for inter-processor communication. The first and second processors use a single nonvolatile memory device for storing boot data and transmit information for booting via the shared memory area.

Abstract: An apparatus and method for controlled sharing of personal information are provided which allow confident and accurate indications of, and alterations to, the level of personal information being shared by all personal information sharing capable (i.e. source) applications of a portable electronic device. Controlled personal information sharing is achieved through the application of sharing modes which are enabled through the cooperation of a plurality of applications which share personal information, a detecting module which detects requests to control the continued sharing of personal information and a controlling module controls the continued sharing of personal information by the plurality of applications. A universal sharing toggle is provided which allows a user of a portable electronic device to control the sharing of all personal information by the device.

Abstract: Controlling a motion system using a plurality of processors. First input data may be received which corresponds to a first portion of the motion system. Second input data may be received which corresponds to a second portion of the motion system. Execution of a first function of a plurality of sequential functions may be assigned to a first processor to determine output for the first portion based on the first input data. Execution of the first function may be assigned to a second processor to determine output for the second portion based on the second input data. The first processor executing the first function and the second processor executing the first function may be performed in parallel. The output for the first portion of the motion system may be provided to the first portion. The output for the second portion of the motion system may be provided to the second portion.

Abstract: A mechanism enabling a processor in a multiprocessor complex to function as a coprocessor to execute a specific function. The method includes a mechanism for activating a coprocessor to function as a coprocessor as well as a mechanism to execute a coprocessor request on the system. The present invention also provides a mechanism for efficient processor to processor communication for processors coupled to a common bus. Overall system performance is enhanced by significantly reducing the use of hardware interrupts for processor to processor communication.

Abstract: A processor subunit for a processor for processing data. The processor subunit includes registers, and at least one functional unit for executing instructions on data. One or more registers of the registers are connected to an input of the at least one functional unit, where each register connected to the input of the at least one functional unit which has an input multiplexer. One or more registers of the registers are connected to an output of the at least one functional unit, where each register connected to the output of the at least one functional unit which has an input multiplexer. At least one output bus is connected to at least one register. At least one input bus is connected to at least one register. The processor subunit may be used in a processor, which may be used in a data streaming accelerator.

Abstract: This invention describes an apparatus, architecture, method, operating system, data network, and application program products for a hybrid digital system with multiple heterogeneous components. This invention is applied to a multiple generic microprocessor architecture s with a set (e.g., one or more cores) of controlling components and a set of groups of sub-processing components. Under this arrangement, different technology cores and functional components, such as memory, are organized in a way that different technologies can collaborate as a system.

Abstract: A distributed memory architecture for a layer 2 processing circuit chip (50) is described. In one implementation, the layer 2 processing circuit chip (50) comprises an external memory interface configured to provide access to data packets stored in an external memory (52), a layer 2 processor (54) coupled to the external memory interface (56) and configured to process data packets retrieved from the external memory (56) to generate RLC SDUs, and an on-chip memory (58) coupled to the layer 2 processor (54) and configured to store the RLC PDUs generated by the layer 2 processor (54) prior to their transmission. Upon a request to retransmit an RLC PDU, the layer 2 processor (54) is configured to selectively read the RLC PDU to be retransmitted from the on-chip memory (58) or a data packet comprising the RLC PDU to be retransmitted from the external memory (52).

Abstract: One or more circuits in a mobile phone may be utilized for up sampling two or more audio signals to a same data sampling rate. Each audio signal, such as digital audio, voice, and polyringer, for example, may be received at one of a plurality of data sampling rates and one or more of the following wireless standards: WCDMA, HSDPA, GSM, GPRS, EDGE, and/or Bluetooth. Audio signals may be equalized and/or compensated with an FIR filter before up sampling or with an IIR filter to reduce overall processing latency. Multiple half-band interpolation operations may perform the up sampling. The first half-band filter may be replaced by an IIR filter to reduce overall processing latency. A gain of the up-sampled data may be adjusted to reduce noise effects. The channels of the up-sampled audio signals may be mixed and later further up sampled for subsequent communication to an output device.

Abstract: A microprocessor apparatus is provided, for performing a cryptographic operation. The microprocessor apparatus includes an x86-compatible microprocessor that has fetch logic, a cryptography unit, and an integer unit. The fetch logic is configured to fetch an application program from memory for execution by the x86-compatible microprocessor. The application program includes an atomic instruction that directs the x86-compatible microprocessor to perform the cryptographic operation. The atomic instruction has and opcode field and a repeat prefix field. The opcode field prescribes that the device accomplish the cryptographic operation as further specified within a control word stored in a memory. The repeat prefix field is coupled to the opcode field. The repeat prefix field indicates that the cryptographic operation prescribed by the atomic instruction is to be accomplished on a plurality of blocks of input data.

Abstract: The present invention features a non-peripherals-based processing control unit having an encasement module that is very small and durable compared to conventional computer encasement structures. The process control unit is capable of being incorporated into various devices and/or environments, of accepting applied and impact loads, of functioning as a load bearing structure, as well as being able to be processed coupled together with one or more processing control units to provide scaled processing power. The processing control unit of the present invention further features a unique method of cooling using natural convection, as well as utilizing known cooling means, such as liquid or thermoelectric cooling.

Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. A multi-stage data stream based processor incorporates a parallel/pipelined architecture optimized to perform data stream processing efficiently. The multi-stage parallel/pipelined processor provides significantly higher processing speeds by combining multiple RCUs wherein input data samples are input in parallel to all RCUs while computation results from one RCU are used by adjacent downstream RCUs. A register file provides storage for historical values while local storage in each RCU provides storage for temporary results.

Abstract: A packet processor whose processing capabilities are optimized by concurrently processing multiple packets within various pipelined stages. At each stage, multiple packets are processed via an internally pipelined sub-processor. In one embodiment, the packets are processed in a round robin fashion. When a particular packet is done processing at a particular stage, it may pass another packet whose processing is not complete, and move to a next stage. In another embodiment, a packet is processed until a conditional branch instruction or any other instruction causing a potential stall is encountered. If such an instruction is encountered, a next available packet is selected and processed instead of wasting processing cycles during the stall, or proceeding with the processing of the current packet based on a predicted result. The sub-processor resumes processing of the packet once the stall is over.

Abstract: Power management methods and systems. First, a running cycle of a processing unit processing a data unit is recorded. A gating signal is generated according to the running cycle and a performance requirement, and a working clock is adjusted according to the gating signal. Thereafter, the adjusted working signal is provided to the processing unit.

Abstract: An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols. The Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm. The application specific processor includes a Load-Store, Logical and De-puncturing (LLD) slot that performs a Load-Store function, a Logical function, a De-puncturing function, and a Trace-back Address generation function, a Branch Metric Compute (BMU) slot that performs a Radix-2 branch metric computations, a Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations, and an Add-Compare-Select (ACS) slot that performs a Radix-2 Path metric computations, a Radix-4 Path metric computations, a best state computations, and a decision bit generation. The LLD slot, the BMU slot and the ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions.

Abstract: An apparatus for counting microcode instruction execution in a microprocessor includes a first register, a second register, a comparator, and a counter. The first register stores an address of a microcode instruction. The microcode instruction is stored in a microcode memory of the microprocessor. The second register stores an address of the next microcode instruction to be retired by a retire unit of the microprocessor. The comparator compares the addresses stored in the first and second registers to indicate a match between them. The counter counts the number of times the comparator indicates a match between the addresses stored in the first register and the second register. The first register is user-programmable and the counter is user-readable. A mask register may be included to create a range of microcode memory addresses so that executions of microcode instructions within the range are counted.

Abstract: A data acquisition system including a readout Application Specific Integrated Circuit (ASIC) having a plurality of channels, each channel having a time discriminating circuit and an energy discriminating circuit, wherein the ASIC is configured to receive a plurality of signals from a semiconductor radiation detector. The data acquisition system also includes a digital-to-analog converter (DAC) electrically coupled to the ASIC and configured to provide a reference signal to the ASIC used in the generation of digital outputs from the ASIC, and a controller electrically coupled to the ASIC and to the DAC, the controller configured to instruct the DAC to provide the reference signal to the ASIC.

Abstract: Embodiments of the present invention are directed to parallel, pipelined, integrated-circuit implementations of computational engines designed to solve complex computational problems. One embodiment of the present invention is a family of video encoders and decoders (“codecs”) that can be incorporated within cameras, cell phones, and other electronic devices for encoding raw video signals into compressed video signals for storage and transmission, and for decoding compressed video signals into raw video signals for output to display devices. A highly parallel, pipelined, special-purpose integrated-circuit implementation of a particular video codec provides, according to embodiments of the present invention, a cost-effective video-codec computational engine that provides an extremely large computational bandwidth with relatively low power consumption and low-latency for decompression and compression of compressed video signals and raw video signals, respectively.

Abstract: Disclosed are methods and systems, among which is a system that includes a pattern-recognition processor, a central processing unit (CPU) coupled to the pattern-recognition processor via a pattern-recognition bus, and memory coupled to the CPU via a memory bus. In some embodiments, the pattern-recognition bus and the memory bus form about the same number of connections to the pattern-recognition processor and the memory, respectively.

Abstract: There is provided a streaming processor which includes one general-purpose processor core and multiple operation processor cores and which performs parallel processing by assigning multiple processes of decoding processing of an encoded stream to the operation processor cores. The streaming processor performs stream analysis processing for estimating a processing load for each stream on the basis of stream information and assigning processes to be performed by the operation processor cores on the basis of the estimated processing load.

Abstract: An electronic gaming machine (EGM) implements a multi-core processor. A first of the processor cores is adapted to perform or otherwise control a first set of operations. The first set of operations can include, for example, game manager operations and other operations of the EGM that are more time-sensitive. A second one of the processor cores is adapted to perform or otherwise control a second set of operations. The second set of operations can include, for example, operations related to multimedia presentation associated with the running/playing of a game and/or other operations of the EGM that are not time-sensitive or are otherwise less time-sensitive than the operations performed/controlled by the first processor core. Each of the processor cores may run an operating system that matches the needs of its respective processor core.