By Clock Speed Control (e.g., Clock On/off) Patents (Class 713/322)
  • Patent number: 11048318
    Abstract: A system on a chip is described that comprises a processor and a set of memory components that store instructions, which when executed by the processor cause the system on a chip to: generate, by a set of data collectors of a telemetry subsystem, a set of streams of telemetry metadata describing operation of the processor, forward one or more streams of telemetry metadata from the set of streams of telemetry metadata to a set of machine learning-driven adaptation decision models, receive, from the set of machine learning-driven adaptation decision models, a set of configuration parameters for controlling operation of the processor based on the one or more streams of telemetry metadata, and modify operation of the processor based on the set of configuration parameters.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: June 29, 2021
    Assignee: Intel Corporation
    Inventors: Julien Sebot, Rangeen Basu Roy Chowdhury, Rustam Miftakhutdinov, Stephen J. Tarsa, Gautham N. Chinya, Eric Donkoh
  • Patent number: 11042406
    Abstract: Technologies for providing predictive thermal management include a compute device. The compute device includes a compute engine and an execution assistant device to assist the compute engine in the execution of a workload.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: June 22, 2021
    Assignee: Intel Corporation
    Inventors: ChungWen Ma, ShuLing Chiu
  • Patent number: 11029745
    Abstract: Systems and methods are disclosed method for controlling instantaneous current changes in parallel processors with arrays of parallel computing elements, such as neural processors. An exemplary method comprises monitoring the array of computing elements and determining a transition from a first activity level of the array to a second activity level of the array, such as an idle-to-active or active-to-idle transition. Once a transition is determined, the array is selectively controlled to minimize the instantaneous current change from the transition from the first activity level to the second activity level.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: June 8, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Kyle Ernewein, Jason Edward Podaima, Francisco Perez, John Daniels, Alex Miler, Jeffrey Gemar, Rexford Alan Hill, Haoping Xu
  • Patent number: 11023245
    Abstract: Closed loop performance controllers of asymmetric multiprocessor systems may be configured and operated to improve performance and power efficiency of such systems by adjusting control effort parameters that determine the dynamic voltage and frequency state of the processors and coprocessors of the system in response to the workload. One example of such an arrangement includes applying hysteresis to the control effort parameter and/or seeding the control effort parameter so that the processor or coprocessor receives a returning workload in a higher performance state. Another example of such an arrangement includes deadline driven control, in which the control effort parameter for one or more processing agents may be increased in response to deadlines not being met for a workload and/or decreased in response to deadlines being met too far in advance. The performance increase/decrease may be determined by comparison of various performance metrics for each of the processing agents.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: June 1, 2021
    Assignee: Apple Inc.
    Inventors: Aditya Venkataraman, Bryan R. Hinch, John G. Dorsey
  • Patent number: 11016556
    Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Doron Rajwan, Tal Kuzi, Dean Mulla, Ariel Szapiro, Nir Tell
  • Patent number: 11003827
    Abstract: Examples described herein provide a non-transitory computer-readable medium storing instructions, which when executed by one or more processors, cause the one or more processors to perform operations. The operations include: generating, using the one or more processors, a plurality of child processes according to a number of programmable dies of the multi-die device, each of the plurality of child processes corresponding to a respective programmable die of the multi-die device, wherein the plurality of child processes execute on different processors; partitioning a design for the multi-die device into a plurality of portions, each of the portions to be used to configure one of the programmable dies of the multi-die device; transmitting the plurality of portions of the design to the plurality of child processes for placement; and receiving placements from the plurality of child processes.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: May 11, 2021
    Assignee: XILINX, INC.
    Inventors: Paul D. Kundarewich, Grigor S. Gasparyan, Mehrdad Eslami Dehkordi, Guenter Stenz, Zhaoxuan Shen, Amish Pandya
  • Patent number: 10976801
    Abstract: In one embodiment, a processor includes: a plurality of cores to execute instructions, at least some of the plurality of cores to be allocated to a plurality of virtual machines (VMs); and a power controller coupled to the plurality of cores. The power controller may include a power distribution circuit to distribute an energy budget to the at least some of the plurality of cores according to priority information associated with the plurality of VMs. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Avinash Ananthakrishnan, Nikhil Gupta
  • Patent number: 10969839
    Abstract: Apparatuses, methods and storage medium associated with restricting current draw in wearable devices are disclosed herein. In embodiments, a wearable computing device may include a power source, one or more components coupled with each other and to the power source to perform wearable computing; and control circuitry coupled with the one or more components, the control circuitry to: identify a threshold selected based on a power consumption model of the wearable computing device; ascertain whether current draw from the power source is greater than the threshold; and restrict the current draw from the power source of the wearable computing device based on a signal output from one of the one or more components, in response to the current draw is ascertained to be greater than the threshold. Other embodiments may be disclosed or claimed.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Devin Cass, David Niemira
  • Patent number: 10963036
    Abstract: Systems and method for idle loop detection and control are disclosed. A processor operates in operating modes including an active mode and a disabled mode, and an interconnect bus is coupled between the processor and one or more additional electronic circuits. Logic within the processor is coupled to snoop the interconnect bus, and the logic is programmed to detect a new idle loop based upon repeated instructions on the interconnect bus and to place the processor in the disabled mode based upon execution of the new idle loop, which represents a previously unknown idle loop for the processor. Further, the logic can be programmed to store state data for the processor when the new idle loop is detected, and the logic can also be programmed to place the processor in the active mode based upon detection of a wakeup event for the new idle loop on the interconnect bus.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: March 30, 2021
    Assignee: NXP USA, Inc.
    Inventors: Ashish Mathur, Sandeep Jain
  • Patent number: 10948968
    Abstract: In an embodiment, a processor includes a core to execute instructions, a power controller to control an operating frequency of the core, and a context filter logic coupled to the power controller to prevent a performance state change request from being granted by the power controller based at least in part on a context of a system including the processor. Other embodiments are described and claimed.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventor: Ghim Boon Lim
  • Patent number: 10942622
    Abstract: Disclosed are a method and a computer system for splitting and merging files via a motion input on a graphical user interface. The method comprises determining existence of a motion input; splitting the file into split multiple partial files based on pre-configurations; and generating multiple partial file icons representing the split multiple partial files on the graphical user interface. The multiple partial files may be subsequently merged together.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: March 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: David S C Chen, Micky W T Chiang, Chao Y. Huang, Chia-Hsueh Lin, Der-Joung Wang
  • Patent number: 10936039
    Abstract: In one embodiment, an apparatus of an edge computing system includes memory that includes instructions and processing circuitry coupled to the memory. The processing circuitry implements the instructions to process a request to execute at least a portion of a workflow on pooled computing resources, the workflow being associated with a particular tenant, determine an amount of power to be allocated to particular resources of the pooled computing resources for execution of the portion of the workflow based on a power budget associated with the tenant and a current power cost, and control allocation of the determined amount of power to the particular resources of the pooled computing resources during execution of the portion of the workflow.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: March 2, 2021
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Suraj Prabhakaran, Timothy Verrall, Karthik Kumar, Mark A. Schmisseur
  • Patent number: 10928849
    Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: February 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho Yeon Jeon, Ah Chan Kim, Jae Gon Lee
  • Patent number: 10891242
    Abstract: A method of operating an embedded USB2 (eUSB2) repeater includes receiving a downstream packet at a USB2 port and transitioning a USB transmitter from an idle state to a standby state responsive to receiving the downstream packet. The method further includes transitioning the USB transmitter from the standby state to an active state if an upstream packet is received at an eUSB2 port within a first time period of receiving the downstream packet and transmitting the upstream packet. The method also includes transitioning the USB transmitter from the active state to the standby state after transmission of the upstream packet. The method also includes transitioning the USB transmitter from the standby state to the idle state if more upstream packets are not received at the eUSB2 port within a second time period.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: January 12, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Douglas Edward Wente, Suzanne Mary Vining, Win Naing Maung, Julie Marie Nirchi
  • Patent number: 10892754
    Abstract: A semiconductor apparatus may include logic circuits and a control logic. The control logic may be configured to monitor characteristics of the logic circuits to allow the semiconductor apparatus to perform at different operating speeds.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: January 12, 2021
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 10891171
    Abstract: A clock task processing method includes before or when running a service process by using at least one data core, disabling a clock interrupt of the at least one data core, and processing a clock task in the at least one data core by using at least one control core of multiple control cores that cannot process service data.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: January 12, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xuesong Pan, Jianfeng Xiu, Zichang Lin
  • Patent number: 10863432
    Abstract: Example implementations relate to an access point (AP) that can via up from power save mode via a including Bluetooth low energy (BLE) system-on-chip (SoC) within the AP. The AP can include a power source, a power reset logic component in communication with the power source, a BLE SoC, a processor, and a non-transitory memory resource instructions executable by the processor that signals the AP is in a power save mode, receives an indication, via the BLE SoC, to wake up the AP, and wake up, via the BLE SoC, the AP in response to receiving the indication.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: December 8, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Berend Dunsbergen, Kannan Konath, Mohd Shahnawaz Siraj
  • Patent number: 10845856
    Abstract: In an embodiment, a system may support a “coast mode” in which the power management unit (PMU) that supplies the supply voltage to an integrated circuit is disabled temporarily for certain modes of the integrated circuit. The integrated circuit may continue to operate, consuming the energy stored in capacitance in and/or around the integrated circuit. When coast mode is initiated, a time interval for coasting may be determined. When the time interval expires, the PMU may re-enable the power supply voltage.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: November 24, 2020
    Assignee: Apple Inc.
    Inventors: Joseph T. DiBene, II, Inder M. Sodhi, Gerard R. Williams, III
  • Patent number: 10817039
    Abstract: Examples herein relate to an adjustment of a power limit of a processor. Examples disclose setting the power limit of the processor. The examples also obtaining a temperature difference between a die temperature of a core within the processor and a throttle temperature. In response to a determination that the temperature difference is at most equal to a temperature activation point, adjusting the power limit of the processor so that the adjust power limit is less than the set power limit.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: October 27, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Vincent Nguyen, Robert E. Van Cleve, Pranay Mahendra, Arthur Volkmann
  • Patent number: 10817042
    Abstract: Embodiments are generally directed to providing power savings for a neural network architecture with zero activations during inference. An embodiment of an apparatus includes one or more processors including one or more processor cores; and a memory to store data for processing including neural network processing, wherein the apparatus to perform a fast clear operation to initialize activation buffers for a neural network by updating metadata to indicate zero values, the neural network including a plurality of layers, wherein the apparatus is to compare outputs for the neural network to the metadata values and to write an output to memory only if the output is non-zero.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: October 27, 2020
    Assignee: INTEL CORPORATION
    Inventors: Kinchit Desai, Sanjeev Jahagirdar, Prasoonkumar Surti, Joydeep Ray
  • Patent number: 10802567
    Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Nadav Bonen, Ron Gabor, Zeev Sperber, Vjekoslav Svilan, David N. Mackintosh, Jose A. Baiocchi Paredes, Naveen Kumar, Shantanu Gupta
  • Patent number: 10795850
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to transition devices between operational modes. An example apparatus comprising: an activity detector configured to be coupled to a communication bus; a communication bus controller coupled to the activity detector; a hardware wakeup controller coupled to the activity detector; a switching circuit coupled to the hardware wakeup controller; a first oscillator coupled to the switching circuit; and a second oscillator the second oscillator coupled to the switching circuit and the hardware wakeup controller.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: October 6, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chung San Roger Chan, T-Pinn Koh, Gary Chard, Bennett Lau, Adam Rappoport
  • Patent number: 10795422
    Abstract: A method and apparatus for mission critical standby of a portable communication device are disclosed. A portable communication device may include a primary processor for a first operating platform, a secondary processor for a second operating platform and communicatively coupled to the primary processor, and a power state manager that may have a first mode and a second mode. The power state manager may be configured to determine whether the primary processor is in a powered off state and sequence supply of power to the secondary processor. The first mode may allow the primary processor to monitor a power state of the secondary processor based on a determination that the primary processor is not in the powered off state and the second mode may enable the power state manager to monitor the power state based on a determination that the primary processor is in the powered off state.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: October 6, 2020
    Assignee: Motorola Solutions, Inc.
    Inventors: Daniel Grobe Sachs, Graeme Johnson, Stephen C. Glass, Peter J. Bartels, Javier Alfaro, Carlos Camps
  • Patent number: 10789192
    Abstract: A method and system for programming a microcontroller (MCU) to implement a data transfer, the MCU having a flash memory, a central processing unit (CPU) and a direct memory access controller (DMAC). In one embodiment, the method includes calling a function stored in the flash memory, wherein a first parameter is passed to the function when it is called, wherein the first parameter identifies a first data structure that is stored in flash memory, and wherein the first data structure includes first DMAC control values. The CPU reads the first DMAC control values in response to the CPU executing instructions of the function. The CPU then writes the first DMAC control values to respective control registers of the DMAC in response to the CPU executing instructions of the function.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: September 29, 2020
    Assignee: RENESAS ELECTRONICS AMERICA INC.
    Inventor: Dale Sparling
  • Patent number: 10775863
    Abstract: Methods and apparatuses to manage working states of a data processing system. At least one embodiment of the present invention includes a data processing system with one or more sensors (e.g., physical sensors such as tachometer and thermistors, and logical sensors such as CPU load) for fine grain control of one or more components (e.g., processor, fan, hard drive, optical drive) of the system for working conditions that balance various goals (e.g., user preferences, performance, power consumption, thermal constraints, acoustic noise). In one example, the clock frequency and core voltage for a processor are actively managed to balance performance and power consumption (heat generation) without a significant latency. In one example, the speed of a cooling fan is actively managed to balance cooling effort and noise (and/or power consumption).
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: September 15, 2020
    Assignee: Apple Inc.
    Inventors: Michael Culbert, Keith Alan Cox, Brian Howard, Josh de Cesare, Richard Charles Williams, Dave Robbins Falkenburg, Daisie Iris Huang, David Radcliffe
  • Patent number: 10761774
    Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: September 1, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Olivier Alavoine, Sejoong Lee, Tauseef Kazi, Simon Booth, Edoardo Regini, Renatas Jakushokas, Saurabh Patodia, Jeffrey Gemar, Michael Hawjing Lo, Vinod Chamarty, Boris Andreev, Tao Shen, Aravind Bhaskara, Wenbiao Wang, Stephen Molloy
  • Patent number: 10761559
    Abstract: In one embodiment, a clock-gating system for a pipeline includes a clock-gating device configured to gate or pass a clock signal to the pipeline, and a clock controller. The clock controller is configured to track a number of input packets at an input of the pipeline, to track a number of output packets at an output of the pipeline, to determine whether to gate or pass the clock signal based on the number of the input packets and the number of the output packets, to instruct the clock-gating device to pass the clock signal if a determination is made to pass the clock signal, and to instruct the clock-gating device to gate the clock signal if a determination is made to gate the clock signal.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: September 1, 2020
    Assignee: QUALCOMM Incorporated
    Inventor: Adam Andrew Zerwick
  • Patent number: 10748635
    Abstract: The present disclosure relates to a device including a built-in-self-test (BIST) circuit configured to run a BIST pattern in a loop mode on a memory which is customized for activity factors corresponding to a programmable number of operations, the BIST circuit being further configured to measure dynamic power on a supply while running the BIST pattern in the loop mode on the memory.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: August 18, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Igor Arsovski, Kyle M. Holmes
  • Patent number: 10747278
    Abstract: Noise generation caused by sudden rising of a rotational speed of a heat radiation fan when a user has no intension is prevented. A temperature management system located on an information processing apparatus is configured by a system including a processor and scheduled tasks, a performance control system which controls processing ability of the processor and a temperature control system which includes a heat radiation fan and controls a heat radiation amount thereof. The processor executes the scheduled tasks when a state where a usage rate is low, such as an idle state, lasts. The temperature control system controls the rotational speed of the heat radiation fan in accordance with temperatures of electronic devices including the processor. The performance control system lowers processing ability of the processor before the rotational speed of the heat radiation fan rises in accordance with a temperature of the processor which executes the scheduled tasks.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: August 18, 2020
    Assignee: LENOVO (SINGAPORE) PTE. LTD.
    Inventors: Kazuhiro Kosugi, Yuhsaku Sugai
  • Patent number: 10747297
    Abstract: A method of operating an application processor including a central processing unit (CPU) with at least one core and a memory interface includes measuring, during a first period, a core active cycle of a period in which the at least one core performs an operation to execute instructions and a core idle cycle of a period in which the at least one core is in an idle state, generating information about a memory access stall cycle of a period in which the at least one core accesses the memory interface in the core active cycle, correcting the core active cycle using the information about the memory access stall cycle to calculate a load on the at least one core using the corrected core active cycle, and performing a DVFS operation on the at least one core using the calculated load on the at least one core.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok-Ju Yoon, Nak-Woo Sung, Seung-Chull Suh, Taek-Ki Kim, Jae-Joon Yoo, Eun-Ok Jo
  • Patent number: 10739842
    Abstract: In some examples, a peak power system includes a plurality of system components, one or more of the system components to dynamically provide a peak power requirement of the component. The system also includes a peak power manager to receive the peak power requirement of the one or more of the system components. The peak power manager can also dynamically provide, based on a system peak power limit and based on at least one updated peak power requirement received from at least one of the one or more system components, an updated component peak power limit to one or more of the system components.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: August 11, 2020
    Assignee: Intel Corporation
    Inventors: Eugene Gorbatov, Alexander B. Uan-Zo-Li, Muhammad Abozaed, Efraim Rotem, Tod F. Schiff, James G. Hermerding, II, Chee Lim Nge
  • Patent number: 10725524
    Abstract: Systems and a method for controlling power of a device with power management software are described. In one embodiment, a computer implemented method initiates power control having ON-OFF keying to control power consumption of a device for energy efficiency and energy conservation. An ON-OFF period of the ON-OFF keying for the device is computed. The method sets a target frequency, a target supply voltage, and a power gate control for the device based on the ON-OFF keying.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Jawad Nasrullah, Kelvin Kwan, David Roger Ditzel, Vjekoslav Svilan
  • Patent number: 10725525
    Abstract: A method of operating a system-on-chip (SOC) including a central processing unit (CPU) and a target hardware to which a dynamic voltage and frequency scaling (DVFS) is applied, includes determining an operating scheme of the target hardware, setting a DVFS application scheme for applying the DVFS to the target hardware, based on the operating scheme of the target hardware, and performing the DVFS on the target hardware, based on the DVFS application scheme.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: July 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Lae Park, Seok-Ju Yoon, Young-Tae Lee, Lak-Kyung Jung
  • Patent number: 10726117
    Abstract: A method for recovering a digital file from a locked device is provided. An identity token is received at a recovery app on the locked device. The recovery app retrieves a digital file from the locked device and sends the digital file and the identity token to a service external to the device.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: July 28, 2020
    Assignee: MOTOROLA SOLUTIONS, INC.
    Inventors: Thomas S. Messerges, Katrin Reitsma
  • Patent number: 10719117
    Abstract: The present control apparatus includes a timer for measuring a predetermined time and a clock generation circuit for supplying a clock to a peripheral device. Furthermore, the control apparatus includes a CPU for alternatingly stopping and restarting driving of the clock generation circuit based on the measuring of the predetermined time performed by the timer. On the other hand, the peripheral device includes an interrupt mask that restricts output of an interrupt signal to the control apparatus via the peripheral bus. When the driving of the clock generation circuit is to be stopped, the control apparatus sets the interrupt mask, and when the driving of the clock generation circuit is to be restarted, the control apparatus cancels the interrupt mask.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: July 21, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Keigo Goda
  • Patent number: 10705594
    Abstract: A Universal Serial Bus 2.0 (USB2 or eUSB2) device includes an integrated circuit (IC) having a physical layer to send and receive data on a pair of signal lines, a repeater communicatively coupled to the physical layer via the pair of signal lines, and having a port to send and receive data on a second pair of signal lines and a power management unit to provide power to the physical layer and the repeater during an active state and to gate power to the physical layer and the repeater during a low power state.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: July 7, 2020
    Assignee: INTEL CORPROATION
    Inventor: Amit Kumar Srivastava
  • Patent number: 10698473
    Abstract: A method for reducing power consumption in an electronic control unit (ECU) equipped with an Ethernet communication function and mounted in a vehicle include initializing a physical layer upon restarting of the physical layer and setting a transmission mode to a data mode. The method includes generating a clock signal having a first frequency for Ethernet communication, checking presence or absence of a normal frame to be transmitted, checking presence or absence of an idle frame based on a reception signal symbol, and determining whether to change the frequency of the clock signal based on checking results in the checking of presence or absence of a normal frame and the checking of presence or absence of an idle frame.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: June 30, 2020
    Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS COMPANY
    Inventor: Soon Chul Park
  • Patent number: 10678556
    Abstract: An integrated circuit device is provided. The integrated circuit device may include a central processing unit (CPU) configured to operate in one of a plurality of modes and a wake-up control circuit configured to control the CPU. The wake-up control circuit may include a clock generator configured to generate an internal clock signal, a multiplexer configured to select a signal from among an external signal and the internal clock signal and to provide the CPU with the selected signal as an operating clock signal, and a controller configured to control the CPU and the clock generator based on the external signal.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: June 9, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaehyeok Jang, Yae Seul Lee, Sang-Yong Park, Tae Sun You, Seong Wook Hwang
  • Patent number: 10664324
    Abstract: The disclosed embodiments provide a system that intelligently migrates workload between servers in a data center to improve efficiency in associated power supplies. During operation, the system receives time-series signals associated with the servers during operation of the data center, wherein the servers include low-priority servers and high-priority servers. Next, the system analyzes the time-series signals to predict a load utilization for the servers. The system then migrates workload between the servers in the data center based on the predicted load utilization so that: the high-priority servers have sufficient workload to ensure that associated power supplies for the high-priority servers operate in a peak-efficiency range; and the low-priority servers operate with less workload or no workload.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: May 26, 2020
    Assignee: Oracle International Corporation
    Inventors: Kenny C. Gross, Sanjeev Sondur
  • Patent number: 10667219
    Abstract: A method for power management of a mobile device includes detecting whether a removable power source has been removed from the mobile device. In response to detecting that the power source has been removed, entering a hot swap mode for a first time period by deactivating a first component of the mobile device and maintaining, via a backup power source in the mobile device, a powered state of a second component of the mobile device and an application state of the mobile device. The method further includes, after the first time period, entering a suspend mode for a second time period by deactivating the second component and continuing to maintain the application state of the mobile device for the second time period.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: May 26, 2020
    Assignee: Symbol Technologies, LLC
    Inventors: Adrian J. Stagg, Steve Maddigan, Kevin Kar-Yin Chan, James Shoong-Leac Chen
  • Patent number: 10656701
    Abstract: Processor frequencies can be managed. For example, a computing device can determine (i) a first estimate of an operating characteristic of a processor in using a first pair of frequencies to perform a task, and (ii) a second estimate of the operating characteristic of the processor in using a second pair of frequencies to perform the task. The computing device can select the first pair of frequencies based on determining that the first estimate is closer to a target operating-characteristic of the processor while performing the task than the second estimate. Based on selecting the first pair of frequencies, the computing device can set a clock rate of the processor to a lower frequency in the first pair of frequencies while performing the task. The computing device can also set the clock rate of the processor to a higher frequency in the first pair of frequencies while performing the task.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: May 19, 2020
    Assignee: Red Hat, Inc.
    Inventor: Marcelo Wormsbecker Tosatti
  • Patent number: 10656694
    Abstract: A method for controlling an operation unit, a system for controlling an operation unit, and a computer storage medium are provided. The method includes: determining a relative current value; determining target frequencies corresponding to all currently running operation units, determining the temperatures of all of the currently running operation units, and calculating the sum of current values of all of the currently running operation units based on the target frequencies and the temperatures, wherein the target frequency corresponding to each running operation unit is a series of frequencies with which the operation unit can run; and comparing the calculated sum of the current values with the determined relative current value, and if the sum of the current values is smaller than the relative current value, determining the target frequency corresponding to the sum of the current values as a running frequency to be selected.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: May 19, 2020
    Assignee: ONEPLUS TECHNOLOGY (SHENZHEN) CO., LTD.
    Inventor: Wenyen Chang
  • Patent number: 10642325
    Abstract: Embodiments are directed to capturing and storing historical data regarding thermal remediations, to predicting and acting on remediation futures and to communicating with applications regarding thermal remediations implemented on the computer system. In one scenario, a computer system determines which thermal remediations are currently being implemented on a monitored computing device. The thermal remediations are based on the monitored computing device's current operating environment including the physical thermal environment and/or the current software execution environment. The computer system further tracks thermal remediation levels for those thermal remediations that are currently being implemented on the monitored computing device, the thermal remediation levels indicating the degree to which each thermal remediation is implemented.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: May 5, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Bruce Lee Worthington, Tristan A. Brown, Iulian Doroftei Calinov
  • Patent number: 10642340
    Abstract: Methods and apparatus relating to rotational graphics sub-slice and Execution Unit (EU) power down to improve power performance efficiency are described. In one embodiment, power-gating is rotated amongst single sub-slices within each slice of a plurality of slices based on an indication to reduce power consumption of a computational logic. The computational logic includes the plurality of slices and each of the plurality of slices includes a plurality of sub-slices to perform one or more computations. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventor: Linda L. Hurd
  • Patent number: 10606304
    Abstract: In an embodiment, a processor may include a first clock circuit to generate a first clock signal, a plurality of functional blocks, and clock logic. Each functional block may include a sub-clock circuit to generate a second clock signal based on the first clock signal, and a counter to store a count of active consumer of the second clock signal. The clock logic may, in response to a determination that the counter of a first functional block has a value less than one, disable the sub-clock circuit of the first functional block. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: March 31, 2020
    Assignee: Intel Corporation
    Inventor: Eckhart Koppen
  • Patent number: 10606530
    Abstract: A printing apparatus which prevents communication from becoming impossible. The printing apparatus has a control unit and a printer unit. At start-up of the control unit, a first communication speed is set as a communication speed for communication between the control unit and the printer unit, and also a predetermined command is transmitted to the printer unit. Whether or not a response to the predetermined command has been received from the printer unit is determined. As a result of the determination, when no response to the predetermined command has been received from the printer unit, a second communication speed different from the first communication speed is set as the communication speed for the communication between the control unit and the printer unit, and also, a reset command is transmitted to the printer unit.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 31, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hiroto Tsujii
  • Patent number: 10593382
    Abstract: A memory device performs first training including a plurality of loop operations to align a main clock signal and a data clock signal, which are received from a memory controller. A method of operating the memory device includes generating division ratio information indicating a division ratio set based on a frequency ratio of the main clock signal to the data clock signal and transmitting the division ratio information to the memory controller to perform the first training.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: March 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Seok Kang, Byung-Chul Kim
  • Patent number: 10585448
    Abstract: A low power autonomous peripheral operative to receive configuration or command data and to perform the designated operation(s) without interaction of a processor.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: March 10, 2020
    Assignee: Ambiq Micro, Inc.
    Inventors: Stephen James Sheafor, Scott Hanson, Donovan Popps
  • Patent number: 10587265
    Abstract: Provided are a semiconductor device and a semiconductor system. A semiconductor device includes a hardware auto clock gating (HWACG) logic configured to provide clock gating of an intellectual property (IP) block; and a memory power controller configured to perform power gating of a memory electrically connected with the IP block, based on the HWACG logic providing the clock gating for the IP block. The HWACG logic includes a first clock source configured to provide a first clock signal; a second clock source configured to receive the first clock signal provided by the first clock source, and provide a second clock signal to the IP block; a first clock control circuit configured to control the first clock source; and a second clock control circuit configured to transmit a clock request to the first clock control circuit, and control the second clock source, based on an operation state of the IP block.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: March 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoo Seok Shon, Sang Woo Kim, Byung Tak Lee, Yun Ju Kwon, Joon-Woo Cho
  • Patent number: 10558607
    Abstract: The present disclosure relates to a bus interface system including a bus line, master integrated circuitry (IC), and slave IC. The master IC is coupled to the bus line and configured to transmit the data signal to the slave IC through the bus line. The slave IC is coupled to the bus line so as to receive the data signal from the master IC and includes a supply capacitor, which is configured to store power from the data signal and provide a supply voltage to the slave IC. When the bus line is in the low state, the supply capacitor is isolated from the bus line. When the bus line is in the high state, the supply capacitor is allowed to extract power from the data signal on the bus line.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: February 11, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Christopher Truong Ngo, Praveen Varma Nadimpalli, Alexander Wayne Hietala