Abstract: This application discloses example frequency control methods, frequency controllers, processors, and electronic devices. One example method includes obtaining at least two temperatures of a processor core, where each of the at least two temperatures corresponds to a frequency. A load change mode of the processor core is determined, where the load change mode indicates a change status of a load of the processor core. A target temperature is determined from the at least two temperatures of the processor core based on the load change mode. A frequency of the processor core is adjusted based on the target temperature.

Abstract: A delay adjustment cell is disposed in a channel of at least one regional clock of a chip clock architecture, and the delay adjustment cell includes a plurality of parallel delay paths with different delay values. The delay adjustment cell gates one of the delay paths based on an obtained configuration signal such that a connected regional clock has a corresponding target delay, and a target delay of each regional clock corresponds to a clock skew mode of the programmable logic chip. A clock skew between different regional clocks is adjusted by controlling the gated delay path in the delay adjustment cell, such that a clock skew of the chip can be adjusted in a relatively large range. Under the same resource configuration, different path choices of the delay adjustment cell lead to different clock skews to meet different clock skew modes in different application scenarios.

Abstract: Disclosed is a user system which includes a first device and a second device, which share a shared voltage, and a power management integrated circuit (PMIC) generating the shared voltage. An operation method of the user system includes performing a first operation of the first device, determining whether a second operation of the second device is to be performed while the first device performs the first operation, based on an operation profile, and when it is determined that the second operation of the second device is to be performed while the first device performs the first operation, changing a power mode of the PMIC from a first power mode to a second power mode, before the second device performs the second operation. The PMIC generates the shared voltage based on the first power mode or the second power mode.

Abstract: A power management integrated circuit (PMIC) includes voltage regulators, a conversion circuit, a measurement cycle controller, an oscillator, and a control logic. The voltage regulators generate regulator voltages. The conversion circuit converts analog signals indicating load currents of the voltage regulators to generate digital signals corresponding to the load currents. The measurement cycle controller operates in response to a first clock signal having a first frequency and generates an oscillation enable signal that is activated during a measurement period. The oscillator generates a second clock signal having a second frequency higher than the first frequency in response to the oscillation enable signal. The control logic operates in response to the second clock signal and generates power information, indicating power consumed by the load currents during the measurement period, using the digital signals.

Abstract: Systems, apparatuses, and methods for enabling localized control of link states in a computing system are disclosed. A computing system includes at least a host processor, a communication fabric, one or more devices, one or more links, and a local link controller to monitor the one or more links. In various implementations, the local link controller detects and controls states of a link without requiring communication with, or intervention by, the host processor. In various implementations, this local control by the link controller includes control over the clock signals provided to the link. For example, the local link controller can directly control the frequency of a clock supplied to the link. In addition, in various implementations the link controller controls the power supplied to the link. For example, the link controller can control the voltage supplied to the link.

Abstract: A includes a plurality of power supply units, a processor, and a non-transitory computer readable medium having instructions stored thereon that, when engaged by the processor, cause performance of a set of functions. The set of functions includes detecting an overcurrent of a first power supply unit of the plurality of power supply units. The set of functions includes determining that the overcurrent of the first power supply unit corresponds to current sharing between the plurality of power supply units. The set of functions includes in response to determining that the overcurrent of the first power supply corresponds to the current sharing, suppressing an overcurrent protection mode of the first power supply.

Abstract: Apparatuses, and methods, for digital cells power reduction are disclosed. For an embodiment, a first plurality of digital logic cells are directly connected to a Vdd terminal and a Vss terminal that have a potential difference of VDD, a second plurality of digital logic cells being directly connected to a Vdd_R terminal and a Vss_R terminal, wherein a potential difference between the Vdd_R terminal and the Vss terminal is (VDD?X1), and a potential difference between the Vss_R terminal and the Vss terminal is X2, wherein at least one digital logic cell has at least one of (a) an input connected to an output of at least one digital logic cell of the second plurality, or (b) an output connected to an input of at least one digital logic cell of the second plurality. Vdd, Vdd_R and Vss_R terminal voltages can be generated by an array of devices.

Abstract: A domain control circuit includes a power regulator to supply power for a first domain on a power rail and a sequencing circuit to control the power regulator, and a clock gate signal to activate the domain. The sequencing circuit receives a domain control signal to control activation and deactivation of the domain. The domain control circuit deactivates the clock gate signal to the domain after controlling the power regulator to supply power for the domain on a power rail. In this manner, a voltage droop in a supply voltage on a power rail is reduced. In some examples, the clock gate signal to the domain is deactivated after a voltage increase on the power rail. In some examples, the power regulator includes a plurality of parallel regulator circuits and a regulator control circuit to determine a number of the parallel regulator circuits to be activated to power the domain.

Abstract: Methods, systems, and devices for dynamic low power mode are described. An apparatus may include a memory device and a controller. The controller may receive a command to transition from a first power state to a second power state, the first power state associated with executing received command and the second power state associated with deactivating one or more components of the memory device. The controller may execute, while in the first power state, a set of operations associated with the transition from the first power state to second power state. The controller may determine whether a duration to execute the set of operations satisfies a delay duration between receiving the command and transitioning to the second power state from the first power state. The controller may transition from the first power state to the second power state based on determining whether the duration satisfies the delay duration.

Abstract: A semiconductor circuit device includes a first clock gating circuit that outputs a first gated clock signal generated from a clock signal and a first enable signal, a non-volatile first flip-flop that operates in response to a clock pulse of the first gated clock signal, an acquisition circuit that acquires data inputted from the first flip-flop according to a second enable signal that enables or disables the acquisition of the data from the first flip-flop, and a power gating circuit that supplies electric power to the first flip-flop and receives the first and second enable signals as power source control signals. The power gating circuit includes a power switch, and supplies the electric power to the first flip-flop by turning ON the power switch when the power source control signals have logical values that enable the clock signal or the acquisition of the data in the acquisition circuit.

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

Abstract: An image processing device includes: a circuit block in which an operation period is predetermined and intermittent operation is performed according to the operation period; a plurality of SRAMs; and a dummy control circuit configured to increase an intensity of a dummy operation of an unused SRAM among the plurality of SRAMs for a certain period of time before the operation period of the circuit block, and to decrease the intensity of the dummy operation of the unused SRAM among the plurality of SRAMs for a certain period of time after the operation period of the circuit block.

Abstract: A memory controller couples to a data fabric clock domain, and to a physical layer interface circuit PHY clock domain. A first interface circuit adapts transfers between the data fabric clock domain (FCLK) and the memory controllers clock domain, and a second interface circuit couples the memory controller to the PHY clock domain. A power controller responds to a power state change request by sending commands to the second interface circuit to change parameters of a memory system and to update a set of timing parameters of the memory controller according to a selected power state of a plurality of power states. The power controller further responds to a request to synchronize with a new frequency on the FCLK domain by changing a set of timing parameters of the clock interface circuit without changing the set of timing parameters of the memory system or the selected power state.

Abstract: A powered device interface assembly includes an optocoupler and a powered device interface. The opto-coupler is electrically coupled with a microcontroller of the power device interface. The powered device interface includes a telemetry circuit coupled with the opto-coupler and configured to generate encoded telemetry information for output via a single pin of the powered device interface for transmission to the microcontroller of the powered device, wherein the opto-coupler is coupled with the single pin and is configured to electrically isolate the single pin from the microcontroller.

Abstract: A communication apparatus includes a communication circuit, a clock supply circuit, a CPU and a memory storing a program which, when executed by the CPU, causes the communication apparatus to function as a control unit which causes the communication circuit to operate in one of a first mode in which the communication circuit performs a normal communication with the external apparatus and a second mode in which the communication circuit operates with lower power consumption than in the first mode. In the second mode, the control unit controls the clock supply circuit so as not to supply the clock signal to the communication circuit. While the communication circuit is operating in the second mode and the clock signal is not being supplied to the communication circuit, the control unit controls the clock supply circuit to start supply of the clock signal to the communication circuit in response to a predetermined signal.

Abstract: Computer-implemented methods for mitigating temperature induced performance variation in a cloud computing system are provided. Aspects include distributing a plurality of microservices among a plurality of compute nodes in a cloud computing system and monitoring a temperature of processors executing each of the plurality of microservices on each of the plurality of compute nodes. Aspects also include calculating a distribution of the temperatures of the processors including a mean temperature and identifying a first group of computing nodes from the plurality of compute nodes having temperatures within a threshold deviation from the mean temperature. Aspects further include controlling an operation of a cooling system of each of the first group of computing nodes and redistributing one or more of the plurality of microservices disposed on a remaining group of computing nodes that are not part of the first group of computing nodes.

Abstract: A memory system and a method of operating the memory system are provided. The memory system may determine, on a determination that the memory system enters thermal throttling mode, a target status read check period based on threshold voltage distribution offset for the target memory die, and set a timer to transmit a status read command for the target memory die to the memory device based on the target status read check period.

Abstract: Described herein are methods and manufacturing systems that select fasteners for pre-feeding and, in some examples, pre-feed the selected fasteners. These methods involve aggregating historical manufacturing data, comprising hole identifications and fastener grip lengths, previously selected for these hole identifications. A specific grip length and a corresponding fastener repeatability rating are then determined for each hole identification from this historical manufacturing data. For example, a specific grip length corresponds to the most frequently selected grip length for this hole identification. In some examples, the historical manufacturing data is analyzed using machine learning. The fastener repeatability rating is compared to an operating threshold, in some examples, to determine if the corresponding grip length should be selected for a particular hole location.

Abstract: Methods and apparatuses control the clock rate of a processing unit. The methods and apparatus control the clock rate by generating an output clock rate based on the determined frequency adjustment such that the processing unit maintains the overclocking. The methods include: receiving an analog voltage supply in response to detecting overclocking in the processing unit; dynamically sensing measurements of an output voltage from a voltage generator based on the received analog voltage supply; determining characteristics of a voltage droop in the output voltage based on the dynamically sensed output voltage measurements; determining a frequency adjustment for the clock rate of the processing unit based on the determined characteristics of the voltage droop; and generating an output clock rate based on the determined frequency adjustment such that the processing unit maintains the overclocking.

Abstract: Provided is a safety control method for an AI server, which is applied in an FPGA. The method includes: obtaining a current electrical current and a current power of a GPU in the AI server according to a preset frequency; determining whether the GPU satisfies a first control privilege transfer requirement; when the GPU satisfies the first control privilege transfer requirement, taking over control privilege of a heat dissipation system from a BMC; and controlling the heat dissipation system according to the current electrical current and the current power of the GPU; wherein the first control privilege transfer requirement includes: the current electrical current of the GPU exceeds a preset electrical current, or a rate of change of the current electrical current of the GPU exceeds a preset rate of change of electrical current, or the current power of the GPU exceeds a first preset power.

Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.

Abstract: Examples of the present disclosure generally relate to integrated circuits, such as a system-on-chip (SoC), that include a memory subsystem. In some examples, an integrated circuit includes a first master circuit in a first power domain on a chip; a second master circuit in a second power domain on the chip; and a first memory controller in a third power domain on the chip. The first master circuit and the second master circuit each are configured to access memory via the first memory controller. The first power domain and the second power domain each are separate and independent from the third power domain.

Abstract: A method of an electronic device are provided in which current consumption for one or more components of the electronic device is compared with a predetermined current. A first surface temperature of the electronic device is determined based on the comparison and power consumption of the one or more components. A location is detected where heat corresponding to the first surface temperature is generated. A second surface temperature of the electronic device is obtained based on power consumption of a component disposed in the electronic device corresponding to the location where the heat is generated. A target temperature is set based on the obtained second surface temperature. The component is controlled to reduce the power consumption of the component based on the target temperature.

Abstract: A device implementing adaptive memory performance control by thread group may include a memory and at least one processor. The at least one processor may be configured to execute a group of threads on one or more cores. The at least one processor may be configured to monitor a plurality of metrics corresponding to the group of threads executing on one or more cores. The metrics may include, for example, a core stall ratio and/or a power metric. The at least one processor may be configured to determine, based at least in part on the plurality of metrics, a memory bandwidth constraint with respect to the group of threads executing on the one or more cores. The at least one processor may be configured to, in response to determining the memory bandwidth constraint, increase a memory performance corresponding to the group of threads executing on the one or more cores.

Abstract: A compute device may include one or more processors operable at variable performance levels depending upon power supplied from a compute device power supply. A baseboard management controller of the compute device may periodically calculate an adjustment value for the power supply to adjust the power delivered to the one or more processors. The adjustment value may be calculated as a function of a thermal margin between the temperature of the one or more processors over time and a thermal operating limit of the one or more processors.

Abstract: A computer program product provides program instructions that are executable by a processor to cause the processor to perform various operations. The operations may include monitoring a performance metric for a workload instance being executed by a composed system within a pool of composable resources in a composable computing system. The composed system includes a compute resource and an associated hardware resource selected from a data storage resource, a memory resource and/or a graphic processing resource. A service level agreement is identified for the workload instance, wherein the agreement includes a minimum level of the performance metric that the composed system must provide to support the workload instance. A power cap may be imposed on the compute resource, and a power cap may be imposed on the associated hardware resource by sending a power capping command to a baseboard management controller on a server including the associated hardware resource.

Abstract: A monitoring system predicts voltage droops at a processor by monitoring one or more performance characteristics of the processor, selecting a response policy based on the prediction, and adjusting a parameter of the processor. Multiple predictions of voltage droop conditions at different locations of the processor are made simultaneously, with the processor generating one or more responses and resulting in adjusting one or more parameters of the processor. By predicting voltage droop conditions before they occur, the deleterious effects of such droop conditions can be minimized or avoided.

Abstract: In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.

Abstract: Disclosed are a power consumption reduction circuit for Graphics Processing Units (GPUs) in a server and a server. The power consumption reduction circuit includes a frequency reduction control chip. The frequency reduction control chip, after receiving an overpower alarm signal generated by a Power Supply Unit (PSU), generates a frequency reduction control signal to a Power Break (PWRBRK) pin of each GPU so as to start a frequency reduction operation of each GPU. It can be seen that, in the present application, an underlying hardware circuit is directly used for implementation with relatively quick responses and without intervention of an operating system, whereby the whole frequency reduction operation of the GPU may be completed within 5 ms, and the PSU is prevented from triggering overpower protection within relatively short time. Therefore, loss of service data of a user caused by an exceptional power failure of the server is avoided.

Abstract: An electronic device is provided. The electronic device includes a housing, a wireless charging coil disposed inside the housing, a fan disposed inside the housing and in proximity to the coil, a temperature sensor disposed inside the housing and in proximity to the coil, a wireless charging circuit having the coil and configured to transmit power wirelessly to an external device via the coil, and a control circuit electrically connected to the fan, the temperature sensor, and the wireless charging circuit. The control circuit may be configured to receive a signal from the external device, receive data related to a temperature of the coil from the temperature sensor, and control the fan at least partially on the basis of at least one of the signal and the data.

Abstract: A latchup immune microcontroller system with a power supply and a filter designed to eliminate external risks of triggering a latchup of a microcontroller caused by the power supply; a clock circuit with a clock frequency and a layout for eliminating external risks of triggering a latchup of the microcontroller caused by a high-frequency clock signal; a reset circuit that uses an optical triggering mechanism acting as a common power supply and an isolated power supply, the power detection circuit and a discharge circuit react in chain in time, avoid risks of triggering latchups of the microcontroller caused by reset signals; an interrupt with a high priority level and the discharge circuit react in chain in time to enhance data security, and output terminals are turned off in sequence to remove external causes of latchup. An application method of an I/O port to eliminate triggers of latchup of the microcontroller.

Abstract: A temperature control system, adapted to a central processing unit powered by a power supply module of an electronic device, is provided. The temperature control system includes a setting module, a first temperature detecting module, a second temperature detecting module, and a power adjusting module. The setting module is configured to set a target temperature of the CPU and a target temperature of the power supply module. The first temperature detecting module is configured to obtain a detected temperature of the CPU. The second temperature detecting module is electrically connected to the power supply module, to obtain a detected temperature of the power supply module.

Abstract: In general, embodiments are disclosed herein for tracking and allocating graphics hardware resources. In one embodiment, a software and/or firmware process constructs a cross-application command queue utilization table based on one or more specified command queue quality of service (QoS) settings, in order to track the target and current utilization rates of each command queue on the graphics hardware over a given frame and to load work onto the graphics hardware in accordance with the utilization table. Based on the constructed utilization table for a given frame, any command queues that have exceed their respective target utilization value may be moved to an “inactive” status for the duration of the current frame. For any command queues that remain in an “active” status for the current frame, work from those command queues may be loaded on to slots of the appropriate data masters of the graphics hardware in any desired order.

Abstract: A method for operating a memory system including a memory device and a controller which controls the memory device includes identifying a target command among a plurality of commands queued in a host command queue; comparing an estimated power with a power limit; checking an estimated de-queuing time in the case where the estimated power is larger than or equal to the power limit; dequeuing the target command from the host command queue to a memory command queue in the case where the estimated de-queuing time is smaller than a predetermined threshold value; de-queueing the target command from the memory command queue to the memory device; and performing an operation corresponding to the target command.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to reduce temperature of a networked device. An example apparatus includes, a temperature threshold monitor to identify a temperature condition associated with the device, a window information retriever to retrieve a current value of a network receive capacity parameter, and a window adjustor to reduce the temperature of the device by generating a modified network receive capacity parameter, the modified network receive capacity parameter based on a ratio of the current value of the network receive capacity parameter and a decrease factor.

Abstract: A resource scheduling method and apparatus, an electronic device, and a storage medium are provided, which are related to the technical field of system resource scheduling. The resource scheduling method comprises: monitoring whether a current system can bear a load of a target application which has triggered and entered a high-computational-power scenario, subjecting the system to resource scheduling if the system is monitored to be unable to bear the load of the target application, and running the target application in the high-computational-power scenario based on scheduled system resources.

Abstract: Examples herein relate to assigning, by a system agent of a central processing unit (CPU), an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent. Avoiding throttling of the system agent can include maintaining a minimum performance level of the system agent. A minimum performance level of the system agent can be based on a minimum operating frequency. Assigning, by a system agent of a central processing unit, an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent can avoid a thermal limit of the CPU. Avoiding thermal limit of the CPU can include adjusting the operating frequency to the core group to avoid performance indicators of the CPU. A performance indicator can indicate CPU utilization corresponds to Thermal Design Point (TDP).

Abstract: A system and method of protecting the input components of a power supply. An input overcurrent protection module is provided, which may be implemented in firmware, which monitors the input current through an input interface of the power supply. When the input current exceeds a threshold current (i.e., a current above the maximum rating of an input component, such as an input cable), the input current protection module determines whether an input overcurrent event is occurring. When it is determined that an input overcurrent event has occurred, the input current protection module disables the output circuitry of the power supply and triggers a few timers. The input overcurrent protection module continues to monitor the input and, if the input current continues to exceed the threshold current, is configured to shut down the power supply. In this way, input components may be protected from overcurrent issues in high-power systems.

Abstract: Example implementations relate to power supply controllers. In some examples, a controller can include instructions to: set a power threshold for a power supply coupled to a computing component when the computing component is operating in a first state, determine when the computing component is alternating from the first state to a second state, and allow the power supply to exceed the power threshold for a fixed period of time in response to the computing component alternating from the first state to the second state.

Abstract: In one embodiment, the voltage droop monitoring circuit includes a ring oscillator circuit block configured to generate a plurality of oscillation signals and configured to output a selected oscillation signal from one of the plurality of oscillation signals based on a first control signal. The first control signal is based on a power supply voltage of a functional circuit block. The voltage droop monitoring circuit further includes a counter configured to generate a count value based on the selected oscillation signal, and a droop detector configured detect droop in the power supply voltage of the functional circuit block based on the count value and at least one threshold value.

Abstract: Disclosed in the present application are a control device, method and equipment for a processor. The control device for the processor comprises: an arithmetic circuit and a memory, the arithmetic circuit being connected to the memory. The arithmetic circuit is used to output a control signal according to acquired sensor data, and the control signal is used to control a processor. The control device, method and equipment for the processor according to the present invention may be used to determine whether it is necessary to start the processor according to preset key information, or whether it is necessary to reduce the energy consumption of a processor which is currently in operation, thereby improving endurance.

Abstract: A heterogeneous microprocessor configured to perform classification on an input signal. The heterogeneous microprocessor includes a die with a central processing unit (CPU) a programmable feature-extraction accelerator (FEA) and a classifier. The FEA is configured to perform feature extraction on the input signal to generate feature data. The classifier is configured to perform classification on the feature data and the CPU is configured to provide processing after classification. The FEA may be configured with a plurality of Gene-Computation (GC) Cores. The FEA may be configured for genetic programing with gene depth constraints, gene number constraints and base function constraints. The classifier may be a support-vector machine accelerator (SVMA). The SVMA may include training data based on error-affected feature data. The heterogeneous microprocessor may also include an automatic-programming & classifier training module.

Abstract: A storage system and an operating method thereof are disclosed. The storage system includes a nonvolatile memory that stores data; a computing device to perform data processing on input data provided from the nonvolatile memory or a host outside the storage system; and a controller to control a writing operation and a reading operation of the nonvolatile memory, monitor an operating state of the computing device while the computing device is performing the data processing, and dynamically manage power of the computing device according to a monitoring result.

Abstract: To provide more uniform performance levels for solid state drive (SSDs), the static power level used by an SSD in an idle state is measured and used to determine a static power offset for each of the drives. The static power offset is set as a parameter for the SSD and used to offset a received power supply level for use on the drive. For a data storage system of multiple SSDs, a common scaling factor can be used to set the degree to which the static power offset is implemented, allowing for a choice between uniformity of power and uniformity of performance for the SSDs of a data storage system.

Abstract: In some aspects, the present disclosure provides a method for power management. The method includes receiving, by a power management unit (PMU), signaling indicative of a first plurality of latency durations from a first plurality of clients, each of the first plurality of latency durations corresponding to one of the first plurality of clients, wherein each of the first plurality of clients is configured to utilize a first shared resource for communication of data. In certain aspects, the method also includes selecting, by the PMU, a first latency duration from the first plurality of latency durations based on a determination that the first latency duration is the shortest latency duration of the first plurality of latency durations, and transitioning, by the PMU, the first shared resource from an active state to the first idle state.

Abstract: In general, this disclosure describes techniques for using a random number generator to affect the lengths of clock cycles in a clock waveform that drives the timing of operations performed by processing circuitry. In one example, the processing circuitry includes a central processing unit and a clock generator. The clock generator is configured, upon receiving an indication of a boot command for the processing circuitry, generate a random number using a true random number generator and generate, based at least in part on the random number, an output clock waveform indicating at least a length of a clock cycle for the central processing unit. The central processing unit is configured to execute a boot sequence for at least the processing circuitry using the output clock waveform.

Abstract: The present disclosure relates to a semiconductor system including a semiconductor device and a controller. The semiconductor device outputs a temperature code corresponding to an internal temperature thereof. The controller controls, based on the temperature code, the semiconductor device to set a temperature measurement mode among at least two temperature measurement modes having different temperature measurement periods and to measure the internal temperature in the set temperature measurement mode.

Abstract: A control circuit is provided. A memory is configured to store a program code. A central processing unit (CPU) executes a plurality of instructions according to the program code. When a specific instruction is executed by the CPU, the CPU generates a control signal. A power mode management circuit generates a selection signal according to the control signal. A processing circuit transforms first power data according to the selection signal. A first storage circuit stores the first power data. The processing circuit generates first set data and second set data according to first power data. A first specific device operates in a first power mode according to the first set data. A second specific device operates in a second power mode according to the second set data. The first storage circuit, the power mode management circuit and the processing circuit are in an always-on state.

Abstract: In an embodiment, a method of operating a radar includes: transmitting a radiation pulse with the radar during an active mode; asserting a sleep flag after transmitting the radiation pulse; turning off a crystal oscillator circuit of the radar after the sleep flag is asserted; clocking a counter of the radar with a low power oscillator during a low power mode after the sleep flag is asserted; asserting a timer flag when the counter reaches a first threshold; and transitioning into the active mode after the timer flag is asserted.

Abstract: A data processing apparatus comprises a plurality of processor circuits to process an event stream comprising one or more high energy events. Each of the plurality of processor circuits draws power from a same power rail. Power management circuitry performs power consumption management by controlling a voltage supply to the power rail, and a frequency of a clock signal provided to the plurality of processor circuits. Status analysis circuitry obtains a status of the individual processing load of each of the processor circuits and restriction circuitry performs high energy event restriction on each of the plurality of processor circuits. The power consumption management and the high energy event restriction are both based on the individual processing load of each of the plurality of processor circuits and each of the processor circuits is restrictable by the restriction circuitry independently of others of the processor circuits.