Abstract: A system for configuring a handheld device based on a state of the handheld device includes an embedded controller (EC), a provided service, user selectable thermal tables (USTT), an Operating System (OS) scheduler, a power plan management (PPM) service and a thermal management service (TMS). The provided service communicates with the EC to determine if the handheld device is docked or coupled to a power supply, is stationary or moving, is coupled to an external display and whether a Peak Mode button is activated and communicates signals to one or more of the USTT, the OS scheduler, the PPM and the TMS to configure the handheld device in one of an Ultra Performance Mode, an Optimized Mode, a Quiet Mode or a Peak Mode.

Abstract: A multiplication-and-accumulation (MAC) circuit includes a MAC operator and a data input circuit. The MAC operator selectively performs a MAC arithmetic operation of weight data and vector data or an element-wise multiplication (EWM) arithmetic operation of the weight data and constant data. The data input circuit provides the MAC operator with the weight data and the vector data when the MAC operator performs the MAC arithmetic operation and provides the MAC operator with the weight data and the constant data when the MAC operator performs the EWM arithmetic operation.

Abstract: Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.

Abstract: An autonomous driving computing system may include an on-board computing system that is configured to perform first operations that include obtaining sensor data relating to an autonomous vehicle (AV). The first operations may include sending the obtained sensor data to an off-board cloud computing system. The autonomous driving computing system may include the off-board cloud computing system, which may be configured to perform second operations that include receiving the sensor data and performing computations relating to the driving operation of the AV based on the obtained sensor data. The second operations may include determining a control signal corresponding to a driving operation and sending the control signal to the on-board computing system. The first operations may involve the on-board computing system receiving, from the off-board cloud computing system, the control signal corresponding to the driving operation of the AV and performing the driving operation by implementing the control signal.

Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores.

Abstract: Particular embodiments described herein provide for an electronic device that includes two or more displays and a BIOS. On startup, before the premem state and MRC initialization of the boot process, the BIOS causes power to be enabled to two or more displays. A display engine determines if a hot plug for each display is asserted and for each display where the hot plug was not asserted, the path to the display where the hot plug was not asserted is closed. In an example, the BIOS communicates the signal to power enable the first display and the second display after general-purpose input/output initialization during the boot process. After the premem stage and MRC initialization are completed, the first display and the second display are both configured to begin to display pixels.

Abstract: An apparatus and method for temperature-constrained frequency control and scheduling. For example, one embodiment of a processor comprises: a plurality of cores; power management circuitry to control a frequency of each core of the plurality of cores based, at least in part, on a temperature associated with one or more cores of the plurality of cores, the power management circuitry comprising: a temperature limit-driven frequency controller to determine a first frequency limit value based on a temperature of a corresponding core reaching a first threshold; frequency prediction hardware logic to predict a temperature-constrained frequency of the corresponding core based on the first frequency limit value and an initial frequency limit value; and performance determination hardware logic to determine a new performance value for the corresponding core based on the temperature-constrained frequency, the new performance value to be provided to a task scheduler.

Abstract: The disclosed method includes observing a utilization of a target sub-component of a functional unit of a processor using a control circuit coupled to the target sub-component. The method also includes detecting that the utilization is outside a desired utilization range and throttling one or more sub-components of the functional unit to reduce a power consumption of the functional unit. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A processing-in-memory (PIM) device includes a first memory region, a second memory region, a third memory region, and a multiplication-and-accumulation MAC circuit. The first memory region is configured to store weight data comprised of elements of a weight matrix. The second memory region is configured to store vector data comprised of elements of a vector matrix. The third memory region is configured to store constant data. The MAC circuit is configured to selectively perform a MAC arithmetic operation of the weight data and the vector data or an element-wise multiplication (EWM) arithmetic operation of the weight data and the constant data.

Abstract: Systems and methods for managing performance in heterogenous computing platforms of IHS (Information Handling Systems) are described. In an illustrative, non-limiting embodiment, a heterogeneous computing platform includes devices and a memory storing firmware instructions. Based on execution of these firmware instructions by a respective device, a corresponding firmware service is provided such that one of the devices operates as an orchestrator. The orchestrator receives reports of changes in context of operation of the IHS by a user and based on the change in user context, determines responsiveness settings that are mapped to the reported user context, where the responsiveness settings adjust thread management policies by one or more processors of the heterogeneous computing platform. The orchestrator configures the one or more processors of the heterogeneous computing platform based on the responsiveness settings, and thus adjusts the performance of the IHS in response to the change in user context.

Abstract: In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.

Abstract: Providing deterministic frequency and voltage enhancements for a processor is disclosed. In an embodiment, a microcontroller on a processor identifies a plurality of parameters related to a processor, the plurality of parameters including at least a current supplied to the processor; determines, in dependence upon the plurality of parameters, one or more frequency scaling indexes including determining an effective switching capacitance ratio; identifies, in dependence upon the one or more frequency scaling indexes, a predetermined frequency parameter for the processor; and transitions, based on the frequency parameter, the processor to a target clock frequency.

Abstract: A processor in a device is configured to access a power policy for the device, where the power policy indicates a relationship between power consumption by the device and another performance variable of the device. The processor is also configured to produce an operating point for the device based at least in part on the power policy. The processor is also configured to provide information regarding the operating point to a management entity that manages the device.

Abstract: Methods and systems for reducing energy consumption. A method may include aggregating, for a prior time period, prior usage data from a plurality of computing nodes. Based on the aggregated prior usage data from the plurality of computing nodes, a usage threshold for decreasing cooling system output for the plurality of computing nodes and a local-time threshold for decreasing the cooling system output for the plurality of computing nodes are determined. Current usage data for the plurality of computing nodes is then received. When the current usage data reaches the usage threshold and the local time is after the local-time threshold, output of the cooling systems of the plurality of computing nodes is decreased.

Abstract: This application discloses example frequency control methods, frequency controllers, processors, and electronic devices. One example method includes obtaining at least two temperatures of a processor core, where each of the at least two temperatures corresponds to a frequency. A load change mode of the processor core is determined, where the load change mode indicates a change status of a load of the processor core. A target temperature is determined from the at least two temperatures of the processor core based on the load change mode. A frequency of the processor core is adjusted based on the target temperature.

Abstract: A delay adjustment cell is disposed in a channel of at least one regional clock of a chip clock architecture, and the delay adjustment cell includes a plurality of parallel delay paths with different delay values. The delay adjustment cell gates one of the delay paths based on an obtained configuration signal such that a connected regional clock has a corresponding target delay, and a target delay of each regional clock corresponds to a clock skew mode of the programmable logic chip. A clock skew between different regional clocks is adjusted by controlling the gated delay path in the delay adjustment cell, such that a clock skew of the chip can be adjusted in a relatively large range. Under the same resource configuration, different path choices of the delay adjustment cell lead to different clock skews to meet different clock skew modes in different application scenarios.

Abstract: Disclosed is a user system which includes a first device and a second device, which share a shared voltage, and a power management integrated circuit (PMIC) generating the shared voltage. An operation method of the user system includes performing a first operation of the first device, determining whether a second operation of the second device is to be performed while the first device performs the first operation, based on an operation profile, and when it is determined that the second operation of the second device is to be performed while the first device performs the first operation, changing a power mode of the PMIC from a first power mode to a second power mode, before the second device performs the second operation. The PMIC generates the shared voltage based on the first power mode or the second power mode.

Abstract: A power management integrated circuit (PMIC) includes voltage regulators, a conversion circuit, a measurement cycle controller, an oscillator, and a control logic. The voltage regulators generate regulator voltages. The conversion circuit converts analog signals indicating load currents of the voltage regulators to generate digital signals corresponding to the load currents. The measurement cycle controller operates in response to a first clock signal having a first frequency and generates an oscillation enable signal that is activated during a measurement period. The oscillator generates a second clock signal having a second frequency higher than the first frequency in response to the oscillation enable signal. The control logic operates in response to the second clock signal and generates power information, indicating power consumed by the load currents during the measurement period, using the digital signals.

Abstract: Systems, apparatuses, and methods for enabling localized control of link states in a computing system are disclosed. A computing system includes at least a host processor, a communication fabric, one or more devices, one or more links, and a local link controller to monitor the one or more links. In various implementations, the local link controller detects and controls states of a link without requiring communication with, or intervention by, the host processor. In various implementations, this local control by the link controller includes control over the clock signals provided to the link. For example, the local link controller can directly control the frequency of a clock supplied to the link. In addition, in various implementations the link controller controls the power supplied to the link. For example, the link controller can control the voltage supplied to the link.

Abstract: A includes a plurality of power supply units, a processor, and a non-transitory computer readable medium having instructions stored thereon that, when engaged by the processor, cause performance of a set of functions. The set of functions includes detecting an overcurrent of a first power supply unit of the plurality of power supply units. The set of functions includes determining that the overcurrent of the first power supply unit corresponds to current sharing between the plurality of power supply units. The set of functions includes in response to determining that the overcurrent of the first power supply corresponds to the current sharing, suppressing an overcurrent protection mode of the first power supply.

Abstract: A domain control circuit includes a power regulator to supply power for a first domain on a power rail and a sequencing circuit to control the power regulator, and a clock gate signal to activate the domain. The sequencing circuit receives a domain control signal to control activation and deactivation of the domain. The domain control circuit deactivates the clock gate signal to the domain after controlling the power regulator to supply power for the domain on a power rail. In this manner, a voltage droop in a supply voltage on a power rail is reduced. In some examples, the clock gate signal to the domain is deactivated after a voltage increase on the power rail. In some examples, the power regulator includes a plurality of parallel regulator circuits and a regulator control circuit to determine a number of the parallel regulator circuits to be activated to power the domain.

Abstract: Apparatuses, and methods, for digital cells power reduction are disclosed. For an embodiment, a first plurality of digital logic cells are directly connected to a Vdd terminal and a Vss terminal that have a potential difference of VDD, a second plurality of digital logic cells being directly connected to a Vdd_R terminal and a Vss_R terminal, wherein a potential difference between the Vdd_R terminal and the Vss terminal is (VDD?X1), and a potential difference between the Vss_R terminal and the Vss terminal is X2, wherein at least one digital logic cell has at least one of (a) an input connected to an output of at least one digital logic cell of the second plurality, or (b) an output connected to an input of at least one digital logic cell of the second plurality. Vdd, Vdd_R and Vss_R terminal voltages can be generated by an array of devices.

Abstract: Methods, systems, and devices for dynamic low power mode are described. An apparatus may include a memory device and a controller. The controller may receive a command to transition from a first power state to a second power state, the first power state associated with executing received command and the second power state associated with deactivating one or more components of the memory device. The controller may execute, while in the first power state, a set of operations associated with the transition from the first power state to second power state. The controller may determine whether a duration to execute the set of operations satisfies a delay duration between receiving the command and transitioning to the second power state from the first power state. The controller may transition from the first power state to the second power state based on determining whether the duration satisfies the delay duration.

Abstract: A semiconductor circuit device includes a first clock gating circuit that outputs a first gated clock signal generated from a clock signal and a first enable signal, a non-volatile first flip-flop that operates in response to a clock pulse of the first gated clock signal, an acquisition circuit that acquires data inputted from the first flip-flop according to a second enable signal that enables or disables the acquisition of the data from the first flip-flop, and a power gating circuit that supplies electric power to the first flip-flop and receives the first and second enable signals as power source control signals. The power gating circuit includes a power switch, and supplies the electric power to the first flip-flop by turning ON the power switch when the power source control signals have logical values that enable the clock signal or the acquisition of the data in the acquisition circuit.

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

Abstract: An image processing device includes: a circuit block in which an operation period is predetermined and intermittent operation is performed according to the operation period; a plurality of SRAMs; and a dummy control circuit configured to increase an intensity of a dummy operation of an unused SRAM among the plurality of SRAMs for a certain period of time before the operation period of the circuit block, and to decrease the intensity of the dummy operation of the unused SRAM among the plurality of SRAMs for a certain period of time after the operation period of the circuit block.

Abstract: A memory controller couples to a data fabric clock domain, and to a physical layer interface circuit PHY clock domain. A first interface circuit adapts transfers between the data fabric clock domain (FCLK) and the memory controllers clock domain, and a second interface circuit couples the memory controller to the PHY clock domain. A power controller responds to a power state change request by sending commands to the second interface circuit to change parameters of a memory system and to update a set of timing parameters of the memory controller according to a selected power state of a plurality of power states. The power controller further responds to a request to synchronize with a new frequency on the FCLK domain by changing a set of timing parameters of the clock interface circuit without changing the set of timing parameters of the memory system or the selected power state.

Abstract: A powered device interface assembly includes an optocoupler and a powered device interface. The opto-coupler is electrically coupled with a microcontroller of the power device interface. The powered device interface includes a telemetry circuit coupled with the opto-coupler and configured to generate encoded telemetry information for output via a single pin of the powered device interface for transmission to the microcontroller of the powered device, wherein the opto-coupler is coupled with the single pin and is configured to electrically isolate the single pin from the microcontroller.

Abstract: A communication apparatus includes a communication circuit, a clock supply circuit, a CPU and a memory storing a program which, when executed by the CPU, causes the communication apparatus to function as a control unit which causes the communication circuit to operate in one of a first mode in which the communication circuit performs a normal communication with the external apparatus and a second mode in which the communication circuit operates with lower power consumption than in the first mode. In the second mode, the control unit controls the clock supply circuit so as not to supply the clock signal to the communication circuit. While the communication circuit is operating in the second mode and the clock signal is not being supplied to the communication circuit, the control unit controls the clock supply circuit to start supply of the clock signal to the communication circuit in response to a predetermined signal.

Abstract: Computer-implemented methods for mitigating temperature induced performance variation in a cloud computing system are provided. Aspects include distributing a plurality of microservices among a plurality of compute nodes in a cloud computing system and monitoring a temperature of processors executing each of the plurality of microservices on each of the plurality of compute nodes. Aspects also include calculating a distribution of the temperatures of the processors including a mean temperature and identifying a first group of computing nodes from the plurality of compute nodes having temperatures within a threshold deviation from the mean temperature. Aspects further include controlling an operation of a cooling system of each of the first group of computing nodes and redistributing one or more of the plurality of microservices disposed on a remaining group of computing nodes that are not part of the first group of computing nodes.

Abstract: A memory system and a method of operating the memory system are provided. The memory system may determine, on a determination that the memory system enters thermal throttling mode, a target status read check period based on threshold voltage distribution offset for the target memory die, and set a timer to transmit a status read command for the target memory die to the memory device based on the target status read check period.

Abstract: Described herein are methods and manufacturing systems that select fasteners for pre-feeding and, in some examples, pre-feed the selected fasteners. These methods involve aggregating historical manufacturing data, comprising hole identifications and fastener grip lengths, previously selected for these hole identifications. A specific grip length and a corresponding fastener repeatability rating are then determined for each hole identification from this historical manufacturing data. For example, a specific grip length corresponds to the most frequently selected grip length for this hole identification. In some examples, the historical manufacturing data is analyzed using machine learning. The fastener repeatability rating is compared to an operating threshold, in some examples, to determine if the corresponding grip length should be selected for a particular hole location.

Abstract: Methods and apparatuses control the clock rate of a processing unit. The methods and apparatus control the clock rate by generating an output clock rate based on the determined frequency adjustment such that the processing unit maintains the overclocking. The methods include: receiving an analog voltage supply in response to detecting overclocking in the processing unit; dynamically sensing measurements of an output voltage from a voltage generator based on the received analog voltage supply; determining characteristics of a voltage droop in the output voltage based on the dynamically sensed output voltage measurements; determining a frequency adjustment for the clock rate of the processing unit based on the determined characteristics of the voltage droop; and generating an output clock rate based on the determined frequency adjustment such that the processing unit maintains the overclocking.

Abstract: Provided is a safety control method for an AI server, which is applied in an FPGA. The method includes: obtaining a current electrical current and a current power of a GPU in the AI server according to a preset frequency; determining whether the GPU satisfies a first control privilege transfer requirement; when the GPU satisfies the first control privilege transfer requirement, taking over control privilege of a heat dissipation system from a BMC; and controlling the heat dissipation system according to the current electrical current and the current power of the GPU; wherein the first control privilege transfer requirement includes: the current electrical current of the GPU exceeds a preset electrical current, or a rate of change of the current electrical current of the GPU exceeds a preset rate of change of electrical current, or the current power of the GPU exceeds a first preset power.

Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.

Abstract: A compute device may include one or more processors operable at variable performance levels depending upon power supplied from a compute device power supply. A baseboard management controller of the compute device may periodically calculate an adjustment value for the power supply to adjust the power delivered to the one or more processors. The adjustment value may be calculated as a function of a thermal margin between the temperature of the one or more processors over time and a thermal operating limit of the one or more processors.

Abstract: A method of an electronic device are provided in which current consumption for one or more components of the electronic device is compared with a predetermined current. A first surface temperature of the electronic device is determined based on the comparison and power consumption of the one or more components. A location is detected where heat corresponding to the first surface temperature is generated. A second surface temperature of the electronic device is obtained based on power consumption of a component disposed in the electronic device corresponding to the location where the heat is generated. A target temperature is set based on the obtained second surface temperature. The component is controlled to reduce the power consumption of the component based on the target temperature.

Abstract: Examples of the present disclosure generally relate to integrated circuits, such as a system-on-chip (SoC), that include a memory subsystem. In some examples, an integrated circuit includes a first master circuit in a first power domain on a chip; a second master circuit in a second power domain on the chip; and a first memory controller in a third power domain on the chip. The first master circuit and the second master circuit each are configured to access memory via the first memory controller. The first power domain and the second power domain each are separate and independent from the third power domain.

Abstract: A device implementing adaptive memory performance control by thread group may include a memory and at least one processor. The at least one processor may be configured to execute a group of threads on one or more cores. The at least one processor may be configured to monitor a plurality of metrics corresponding to the group of threads executing on one or more cores. The metrics may include, for example, a core stall ratio and/or a power metric. The at least one processor may be configured to determine, based at least in part on the plurality of metrics, a memory bandwidth constraint with respect to the group of threads executing on the one or more cores. The at least one processor may be configured to, in response to determining the memory bandwidth constraint, increase a memory performance corresponding to the group of threads executing on the one or more cores.

Abstract: A computer program product provides program instructions that are executable by a processor to cause the processor to perform various operations. The operations may include monitoring a performance metric for a workload instance being executed by a composed system within a pool of composable resources in a composable computing system. The composed system includes a compute resource and an associated hardware resource selected from a data storage resource, a memory resource and/or a graphic processing resource. A service level agreement is identified for the workload instance, wherein the agreement includes a minimum level of the performance metric that the composed system must provide to support the workload instance. A power cap may be imposed on the compute resource, and a power cap may be imposed on the associated hardware resource by sending a power capping command to a baseboard management controller on a server including the associated hardware resource.

Abstract: A monitoring system predicts voltage droops at a processor by monitoring one or more performance characteristics of the processor, selecting a response policy based on the prediction, and adjusting a parameter of the processor. Multiple predictions of voltage droop conditions at different locations of the processor are made simultaneously, with the processor generating one or more responses and resulting in adjusting one or more parameters of the processor. By predicting voltage droop conditions before they occur, the deleterious effects of such droop conditions can be minimized or avoided.

Abstract: In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.

Abstract: Disclosed are a power consumption reduction circuit for Graphics Processing Units (GPUs) in a server and a server. The power consumption reduction circuit includes a frequency reduction control chip. The frequency reduction control chip, after receiving an overpower alarm signal generated by a Power Supply Unit (PSU), generates a frequency reduction control signal to a Power Break (PWRBRK) pin of each GPU so as to start a frequency reduction operation of each GPU. It can be seen that, in the present application, an underlying hardware circuit is directly used for implementation with relatively quick responses and without intervention of an operating system, whereby the whole frequency reduction operation of the GPU may be completed within 5 ms, and the PSU is prevented from triggering overpower protection within relatively short time. Therefore, loss of service data of a user caused by an exceptional power failure of the server is avoided.

Abstract: An electronic device is provided. The electronic device includes a housing, a wireless charging coil disposed inside the housing, a fan disposed inside the housing and in proximity to the coil, a temperature sensor disposed inside the housing and in proximity to the coil, a wireless charging circuit having the coil and configured to transmit power wirelessly to an external device via the coil, and a control circuit electrically connected to the fan, the temperature sensor, and the wireless charging circuit. The control circuit may be configured to receive a signal from the external device, receive data related to a temperature of the coil from the temperature sensor, and control the fan at least partially on the basis of at least one of the signal and the data.

Abstract: A temperature control system, adapted to a central processing unit powered by a power supply module of an electronic device, is provided. The temperature control system includes a setting module, a first temperature detecting module, a second temperature detecting module, and a power adjusting module. The setting module is configured to set a target temperature of the CPU and a target temperature of the power supply module. The first temperature detecting module is configured to obtain a detected temperature of the CPU. The second temperature detecting module is electrically connected to the power supply module, to obtain a detected temperature of the power supply module.

Abstract: A latchup immune microcontroller system with a power supply and a filter designed to eliminate external risks of triggering a latchup of a microcontroller caused by the power supply; a clock circuit with a clock frequency and a layout for eliminating external risks of triggering a latchup of the microcontroller caused by a high-frequency clock signal; a reset circuit that uses an optical triggering mechanism acting as a common power supply and an isolated power supply, the power detection circuit and a discharge circuit react in chain in time, avoid risks of triggering latchups of the microcontroller caused by reset signals; an interrupt with a high priority level and the discharge circuit react in chain in time to enhance data security, and output terminals are turned off in sequence to remove external causes of latchup. An application method of an I/O port to eliminate triggers of latchup of the microcontroller.

Abstract: In general, embodiments are disclosed herein for tracking and allocating graphics hardware resources. In one embodiment, a software and/or firmware process constructs a cross-application command queue utilization table based on one or more specified command queue quality of service (QoS) settings, in order to track the target and current utilization rates of each command queue on the graphics hardware over a given frame and to load work onto the graphics hardware in accordance with the utilization table. Based on the constructed utilization table for a given frame, any command queues that have exceed their respective target utilization value may be moved to an “inactive” status for the duration of the current frame. For any command queues that remain in an “active” status for the current frame, work from those command queues may be loaded on to slots of the appropriate data masters of the graphics hardware in any desired order.

Abstract: A method for operating a memory system including a memory device and a controller which controls the memory device includes identifying a target command among a plurality of commands queued in a host command queue; comparing an estimated power with a power limit; checking an estimated de-queuing time in the case where the estimated power is larger than or equal to the power limit; dequeuing the target command from the host command queue to a memory command queue in the case where the estimated de-queuing time is smaller than a predetermined threshold value; de-queueing the target command from the memory command queue to the memory device; and performing an operation corresponding to the target command.

Abstract: A resource scheduling method and apparatus, an electronic device, and a storage medium are provided, which are related to the technical field of system resource scheduling. The resource scheduling method comprises: monitoring whether a current system can bear a load of a target application which has triggered and entered a high-computational-power scenario, subjecting the system to resource scheduling if the system is monitored to be unable to bear the load of the target application, and running the target application in the high-computational-power scenario based on scheduled system resources.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to reduce temperature of a networked device. An example apparatus includes, a temperature threshold monitor to identify a temperature condition associated with the device, a window information retriever to retrieve a current value of a network receive capacity parameter, and a window adjustor to reduce the temperature of the device by generating a modified network receive capacity parameter, the modified network receive capacity parameter based on a ratio of the current value of the network receive capacity parameter and a decrease factor.