Abstract: Provided is a safety control method for an AI server, which is applied in an FPGA. The method includes: obtaining a current electrical current and a current power of a GPU in the AI server according to a preset frequency; determining whether the GPU satisfies a first control privilege transfer requirement; when the GPU satisfies the first control privilege transfer requirement, taking over control privilege of a heat dissipation system from a BMC; and controlling the heat dissipation system according to the current electrical current and the current power of the GPU; wherein the first control privilege transfer requirement includes: the current electrical current of the GPU exceeds a preset electrical current, or a rate of change of the current electrical current of the GPU exceeds a preset rate of change of electrical current, or the current power of the GPU exceeds a first preset power.

Abstract: Examples of the present disclosure generally relate to integrated circuits, such as a system-on-chip (SoC), that include a memory subsystem. In some examples, an integrated circuit includes a first master circuit in a first power domain on a chip; a second master circuit in a second power domain on the chip; and a first memory controller in a third power domain on the chip. The first master circuit and the second master circuit each are configured to access memory via the first memory controller. The first power domain and the second power domain each are separate and independent from the third power domain.

Abstract: A method of an electronic device are provided in which current consumption for one or more components of the electronic device is compared with a predetermined current. A first surface temperature of the electronic device is determined based on the comparison and power consumption of the one or more components. A location is detected where heat corresponding to the first surface temperature is generated. A second surface temperature of the electronic device is obtained based on power consumption of a component disposed in the electronic device corresponding to the location where the heat is generated. A target temperature is set based on the obtained second surface temperature. The component is controlled to reduce the power consumption of the component based on the target temperature.

Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.

Abstract: A compute device may include one or more processors operable at variable performance levels depending upon power supplied from a compute device power supply. A baseboard management controller of the compute device may periodically calculate an adjustment value for the power supply to adjust the power delivered to the one or more processors. The adjustment value may be calculated as a function of a thermal margin between the temperature of the one or more processors over time and a thermal operating limit of the one or more processors.

Abstract: A device implementing adaptive memory performance control by thread group may include a memory and at least one processor. The at least one processor may be configured to execute a group of threads on one or more cores. The at least one processor may be configured to monitor a plurality of metrics corresponding to the group of threads executing on one or more cores. The metrics may include, for example, a core stall ratio and/or a power metric. The at least one processor may be configured to determine, based at least in part on the plurality of metrics, a memory bandwidth constraint with respect to the group of threads executing on the one or more cores. The at least one processor may be configured to, in response to determining the memory bandwidth constraint, increase a memory performance corresponding to the group of threads executing on the one or more cores.

Abstract: A computer program product provides program instructions that are executable by a processor to cause the processor to perform various operations. The operations may include monitoring a performance metric for a workload instance being executed by a composed system within a pool of composable resources in a composable computing system. The composed system includes a compute resource and an associated hardware resource selected from a data storage resource, a memory resource and/or a graphic processing resource. A service level agreement is identified for the workload instance, wherein the agreement includes a minimum level of the performance metric that the composed system must provide to support the workload instance. A power cap may be imposed on the compute resource, and a power cap may be imposed on the associated hardware resource by sending a power capping command to a baseboard management controller on a server including the associated hardware resource.

Abstract: A monitoring system predicts voltage droops at a processor by monitoring one or more performance characteristics of the processor, selecting a response policy based on the prediction, and adjusting a parameter of the processor. Multiple predictions of voltage droop conditions at different locations of the processor are made simultaneously, with the processor generating one or more responses and resulting in adjusting one or more parameters of the processor. By predicting voltage droop conditions before they occur, the deleterious effects of such droop conditions can be minimized or avoided.

Abstract: In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.

Abstract: Disclosed are a power consumption reduction circuit for Graphics Processing Units (GPUs) in a server and a server. The power consumption reduction circuit includes a frequency reduction control chip. The frequency reduction control chip, after receiving an overpower alarm signal generated by a Power Supply Unit (PSU), generates a frequency reduction control signal to a Power Break (PWRBRK) pin of each GPU so as to start a frequency reduction operation of each GPU. It can be seen that, in the present application, an underlying hardware circuit is directly used for implementation with relatively quick responses and without intervention of an operating system, whereby the whole frequency reduction operation of the GPU may be completed within 5 ms, and the PSU is prevented from triggering overpower protection within relatively short time. Therefore, loss of service data of a user caused by an exceptional power failure of the server is avoided.

Abstract: An electronic device is provided. The electronic device includes a housing, a wireless charging coil disposed inside the housing, a fan disposed inside the housing and in proximity to the coil, a temperature sensor disposed inside the housing and in proximity to the coil, a wireless charging circuit having the coil and configured to transmit power wirelessly to an external device via the coil, and a control circuit electrically connected to the fan, the temperature sensor, and the wireless charging circuit. The control circuit may be configured to receive a signal from the external device, receive data related to a temperature of the coil from the temperature sensor, and control the fan at least partially on the basis of at least one of the signal and the data.

Abstract: A latchup immune microcontroller system with a power supply and a filter designed to eliminate external risks of triggering a latchup of a microcontroller caused by the power supply; a clock circuit with a clock frequency and a layout for eliminating external risks of triggering a latchup of the microcontroller caused by a high-frequency clock signal; a reset circuit that uses an optical triggering mechanism acting as a common power supply and an isolated power supply, the power detection circuit and a discharge circuit react in chain in time, avoid risks of triggering latchups of the microcontroller caused by reset signals; an interrupt with a high priority level and the discharge circuit react in chain in time to enhance data security, and output terminals are turned off in sequence to remove external causes of latchup. An application method of an I/O port to eliminate triggers of latchup of the microcontroller.

Abstract: A temperature control system, adapted to a central processing unit powered by a power supply module of an electronic device, is provided. The temperature control system includes a setting module, a first temperature detecting module, a second temperature detecting module, and a power adjusting module. The setting module is configured to set a target temperature of the CPU and a target temperature of the power supply module. The first temperature detecting module is configured to obtain a detected temperature of the CPU. The second temperature detecting module is electrically connected to the power supply module, to obtain a detected temperature of the power supply module.

Abstract: In general, embodiments are disclosed herein for tracking and allocating graphics hardware resources. In one embodiment, a software and/or firmware process constructs a cross-application command queue utilization table based on one or more specified command queue quality of service (QoS) settings, in order to track the target and current utilization rates of each command queue on the graphics hardware over a given frame and to load work onto the graphics hardware in accordance with the utilization table. Based on the constructed utilization table for a given frame, any command queues that have exceed their respective target utilization value may be moved to an “inactive” status for the duration of the current frame. For any command queues that remain in an “active” status for the current frame, work from those command queues may be loaded on to slots of the appropriate data masters of the graphics hardware in any desired order.

Abstract: A method for operating a memory system including a memory device and a controller which controls the memory device includes identifying a target command among a plurality of commands queued in a host command queue; comparing an estimated power with a power limit; checking an estimated de-queuing time in the case where the estimated power is larger than or equal to the power limit; dequeuing the target command from the host command queue to a memory command queue in the case where the estimated de-queuing time is smaller than a predetermined threshold value; de-queueing the target command from the memory command queue to the memory device; and performing an operation corresponding to the target command.

Abstract: A resource scheduling method and apparatus, an electronic device, and a storage medium are provided, which are related to the technical field of system resource scheduling. The resource scheduling method comprises: monitoring whether a current system can bear a load of a target application which has triggered and entered a high-computational-power scenario, subjecting the system to resource scheduling if the system is monitored to be unable to bear the load of the target application, and running the target application in the high-computational-power scenario based on scheduled system resources.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to reduce temperature of a networked device. An example apparatus includes, a temperature threshold monitor to identify a temperature condition associated with the device, a window information retriever to retrieve a current value of a network receive capacity parameter, and a window adjustor to reduce the temperature of the device by generating a modified network receive capacity parameter, the modified network receive capacity parameter based on a ratio of the current value of the network receive capacity parameter and a decrease factor.

Abstract: Examples herein relate to assigning, by a system agent of a central processing unit (CPU), an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent. Avoiding throttling of the system agent can include maintaining a minimum performance level of the system agent. A minimum performance level of the system agent can be based on a minimum operating frequency. Assigning, by a system agent of a central processing unit, an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent can avoid a thermal limit of the CPU. Avoiding thermal limit of the CPU can include adjusting the operating frequency to the core group to avoid performance indicators of the CPU. A performance indicator can indicate CPU utilization corresponds to Thermal Design Point (TDP).

Abstract: A system and method of protecting the input components of a power supply. An input overcurrent protection module is provided, which may be implemented in firmware, which monitors the input current through an input interface of the power supply. When the input current exceeds a threshold current (i.e., a current above the maximum rating of an input component, such as an input cable), the input current protection module determines whether an input overcurrent event is occurring. When it is determined that an input overcurrent event has occurred, the input current protection module disables the output circuitry of the power supply and triggers a few timers. The input overcurrent protection module continues to monitor the input and, if the input current continues to exceed the threshold current, is configured to shut down the power supply. In this way, input components may be protected from overcurrent issues in high-power systems.

Abstract: Example implementations relate to power supply controllers. In some examples, a controller can include instructions to: set a power threshold for a power supply coupled to a computing component when the computing component is operating in a first state, determine when the computing component is alternating from the first state to a second state, and allow the power supply to exceed the power threshold for a fixed period of time in response to the computing component alternating from the first state to the second state.

Abstract: In one embodiment, the voltage droop monitoring circuit includes a ring oscillator circuit block configured to generate a plurality of oscillation signals and configured to output a selected oscillation signal from one of the plurality of oscillation signals based on a first control signal. The first control signal is based on a power supply voltage of a functional circuit block. The voltage droop monitoring circuit further includes a counter configured to generate a count value based on the selected oscillation signal, and a droop detector configured detect droop in the power supply voltage of the functional circuit block based on the count value and at least one threshold value.

Abstract: Disclosed in the present application are a control device, method and equipment for a processor. The control device for the processor comprises: an arithmetic circuit and a memory, the arithmetic circuit being connected to the memory. The arithmetic circuit is used to output a control signal according to acquired sensor data, and the control signal is used to control a processor. The control device, method and equipment for the processor according to the present invention may be used to determine whether it is necessary to start the processor according to preset key information, or whether it is necessary to reduce the energy consumption of a processor which is currently in operation, thereby improving endurance.

Abstract: A heterogeneous microprocessor configured to perform classification on an input signal. The heterogeneous microprocessor includes a die with a central processing unit (CPU) a programmable feature-extraction accelerator (FEA) and a classifier. The FEA is configured to perform feature extraction on the input signal to generate feature data. The classifier is configured to perform classification on the feature data and the CPU is configured to provide processing after classification. The FEA may be configured with a plurality of Gene-Computation (GC) Cores. The FEA may be configured for genetic programing with gene depth constraints, gene number constraints and base function constraints. The classifier may be a support-vector machine accelerator (SVMA). The SVMA may include training data based on error-affected feature data. The heterogeneous microprocessor may also include an automatic-programming & classifier training module.

Abstract: A storage system and an operating method thereof are disclosed. The storage system includes a nonvolatile memory that stores data; a computing device to perform data processing on input data provided from the nonvolatile memory or a host outside the storage system; and a controller to control a writing operation and a reading operation of the nonvolatile memory, monitor an operating state of the computing device while the computing device is performing the data processing, and dynamically manage power of the computing device according to a monitoring result.

Abstract: To provide more uniform performance levels for solid state drive (SSDs), the static power level used by an SSD in an idle state is measured and used to determine a static power offset for each of the drives. The static power offset is set as a parameter for the SSD and used to offset a received power supply level for use on the drive. For a data storage system of multiple SSDs, a common scaling factor can be used to set the degree to which the static power offset is implemented, allowing for a choice between uniformity of power and uniformity of performance for the SSDs of a data storage system.

Abstract: In some aspects, the present disclosure provides a method for power management. The method includes receiving, by a power management unit (PMU), signaling indicative of a first plurality of latency durations from a first plurality of clients, each of the first plurality of latency durations corresponding to one of the first plurality of clients, wherein each of the first plurality of clients is configured to utilize a first shared resource for communication of data. In certain aspects, the method also includes selecting, by the PMU, a first latency duration from the first plurality of latency durations based on a determination that the first latency duration is the shortest latency duration of the first plurality of latency durations, and transitioning, by the PMU, the first shared resource from an active state to the first idle state.

Abstract: In general, this disclosure describes techniques for using a random number generator to affect the lengths of clock cycles in a clock waveform that drives the timing of operations performed by processing circuitry. In one example, the processing circuitry includes a central processing unit and a clock generator. The clock generator is configured, upon receiving an indication of a boot command for the processing circuitry, generate a random number using a true random number generator and generate, based at least in part on the random number, an output clock waveform indicating at least a length of a clock cycle for the central processing unit. The central processing unit is configured to execute a boot sequence for at least the processing circuitry using the output clock waveform.

Abstract: The present disclosure relates to a semiconductor system including a semiconductor device and a controller. The semiconductor device outputs a temperature code corresponding to an internal temperature thereof. The controller controls, based on the temperature code, the semiconductor device to set a temperature measurement mode among at least two temperature measurement modes having different temperature measurement periods and to measure the internal temperature in the set temperature measurement mode.

Abstract: A control circuit is provided. A memory is configured to store a program code. A central processing unit (CPU) executes a plurality of instructions according to the program code. When a specific instruction is executed by the CPU, the CPU generates a control signal. A power mode management circuit generates a selection signal according to the control signal. A processing circuit transforms first power data according to the selection signal. A first storage circuit stores the first power data. The processing circuit generates first set data and second set data according to first power data. A first specific device operates in a first power mode according to the first set data. A second specific device operates in a second power mode according to the second set data. The first storage circuit, the power mode management circuit and the processing circuit are in an always-on state.

Abstract: A data processing apparatus comprises a plurality of processor circuits to process an event stream comprising one or more high energy events. Each of the plurality of processor circuits draws power from a same power rail. Power management circuitry performs power consumption management by controlling a voltage supply to the power rail, and a frequency of a clock signal provided to the plurality of processor circuits. Status analysis circuitry obtains a status of the individual processing load of each of the processor circuits and restriction circuitry performs high energy event restriction on each of the plurality of processor circuits. The power consumption management and the high energy event restriction are both based on the individual processing load of each of the plurality of processor circuits and each of the processor circuits is restrictable by the restriction circuitry independently of others of the processor circuits.

Abstract: In an embodiment, a method of operating a radar includes: transmitting a radiation pulse with the radar during an active mode; asserting a sleep flag after transmitting the radiation pulse; turning off a crystal oscillator circuit of the radar after the sleep flag is asserted; clocking a counter of the radar with a low power oscillator during a low power mode after the sleep flag is asserted; asserting a timer flag when the counter reaches a first threshold; and transitioning into the active mode after the timer flag is asserted.

Abstract: A semiconductor device containing a CPU capable of receiving an interrupt request signal and a task control circuit is provided. The semiconductor device includes a CPU (processor), a save circuit, and a task control circuit. The CPU includes a program counter that is updated when a task is executed. The semiconductor device includes an interrupt-related data save circuit that stores the data of the program counter when the CPU receives a CPU interrupt request signal. The data of the program counter stored in the interrupt-related data save circuit is stored in an save circuit and is used for restoring from the interrupt processing.

Abstract: A system for detecting a false linkup state in an Ethernet communication link includes at least one processor programmed or configured to determine a block type of a block of bits received from a serializer/deserializer (SerDes), increment a first counter based on determining that the block type of the block of bits corresponds to a data block type or an error block type, determine whether the first counter satisfies a first threshold, enable a flag indicating that there is a false linkup state in an Ethernet communication link, and transmit a message indicating that there is a false linkup state for the Ethernet communication link to an Ethernet network device that is a link partner of the Ethernet communication link. A method and a computer program product are also provided.

Abstract: Systems and methods are disclosed for scheduling threads on an asymmetric multiprocessing system having multiple core types. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Metrics for workloads offloaded to co-processors can be tracked and integrated into metrics for the offloading thread group.

Abstract: Apparatus, systems, methods, and articles of manufacture to manage power of deep learning accelerator systems are disclosed. An example apparatus includes a power manager and a power controller. The power manager is to generate a power table to allocate power frequencies between an accelerator and memory based on a ratio of compute tasks and bandwidth tasks in a first workload; update the power table based on a request to at least one of add a second workload or remove the first workload; and determine an index into the power table. The power controller is to determine a power consumption based on the power table; determine whether to update the index based on a power budget and the power consumption; and allocate power to the accelerator and the memory according to the power table.

Abstract: Disclosed are an integrated circuit for controlling function modules to a low-power status depending on an operating status, an electronic device, and a control method thereof. An integrated circuit includes at least one clock generator, a clock distribution circuit that distributes a clock generated by the at least one clock generator, a plurality of function modules that receive the clock distributed by the clock distribution circuit, a monitoring circuit that monitors operating statuses of the at least one clock generator and the clock distribution circuit, a memory, and at least one control circuit.

Abstract: In some examples, a non-transitory machine-readable medium can include instructions executable by a processing resource to: monitor system power for a computing system that includes a first computing component type and a second computing component type, determine a power event type for the computing system based on the monitored system power, and alter a power limit of the second computing component type by a predetermined increment based on the power event type while maintaining a power limit of the first computing component type when the second computing component type is a sub-system of the computing system.

Abstract: A memory sub-system includes a plurality of memory components where at least two of the memory components are configured to operate at different supply voltages. A capacitive voltage divider (CVD) configured to, responsive to a status of use of each of the memory components, select between a plurality of connections of a plurality of capacitors to reduce an input voltage of the memory sub-system. The plurality of connections is configured to provide different voltage magnitudes that correspond to the different supply voltages, and the CVD is further configured to output the different supply voltages to enable the use of each of the memory components.

Abstract: A computing device, a power consumption prediction method thereof, and a non-transitory computer-readable storage medium are provided. In one embodiment, leakage power consumption of a graphics processor is obtained. Switching power consumption data corresponding to the graphics processor running a frame of image is obtained. Switching power consumption is estimated according to the switching power consumption data. Overall power consumption of the graphics processor is obtained according to the leakage power and the switching power consumption. Overall power consumption of the graphics processor processing one frame of image is estimated based on the overall power consumption. Power consumption performance of the graphics processor is therefore predicted in real-time.

Abstract: According to one embodiment, a DP accelerator includes one or more execution units (EUs) configured to perform data processing operations in response to an instruction received from a host system coupled over a bus. The DP accelerator includes a security unit (SU) configured to establish and maintain a secure channel with the host system to exchange commands and data associated with the data processing operations. The DP accelerator includes a time unit (TU) coupled to the security unit to provide timestamp services to the security unit, where the time unit includes a clock generator to generate clock signals locally without having to derive the clock signals from an external source. The TU includes a timestamp generator coupled to the clock generator to generate a timestamp based on the clock signals, and a power supply to provide power to the clock generator and the timestamp generator.

Abstract: An information processing apparatus includes a memory; and a processor coupled to the memory and configured to generate a performance model for calculating a performance value of an application program from a power restriction for each set of parameters of the application program, based on data acquired when a computing apparatus executes the application program for each set of parameters of the application program under each of a plurality of power restrictions; calculate, for each set of parameters of the application program, the performance value of the application program from a first power restriction different from any of the plurality of power restrictions, based on the performance model generated for each set of parameters of the application program; and output a set of parameters of the application program corresponding to a highest performance value of the calculated performance values.

Abstract: A chip includes a receiving, a transmission, a control, and a switch circuit. The receiving circuit is operated at a first voltage and receives a first data. The transmission circuit is operated at the first voltage. Under general mode, the control circuit is operated at a second voltage and generates a second data to the transmission circuit according to the first data. The control circuit includes a first clock source configured to provide a first clock under general mode. The control circuit is operated according to the first clock. Under general mode, the switch circuit is operated at the first voltage, and controls the second voltage to pause the second voltage supplying to the control circuit to enter sleep mode. Under sleep mode, the switch circuit controls the supply of the second voltage to the control circuit according to the first data to return to general mode.

Abstract: A method for storing input data in a flash memory. The method comprising generating a codeword by encoding the input data with an error correcting code and generating a shaped codeword by applying a shaping function to at least a part of the codeword. The shaping function comprising logically inverting every n-th occurrence of a bit associated with a high-charge storage state in the part of the codeword. The method further comprising writing the shaped codeword to the flash memory, generating an estimated shaped codeword by reading the flash memory, generating soft decision information for the estimated shaped codeword, and retrieving the input data by decoding the soft decision information using an error correcting code soft decoder.

Abstract: Embodiments of the invention include a communication interface and protocol for allowing communication between devices, circuits, integrated circuits and similar electronic components having different communication capacities or clock domains. The interface supports communication between any components having any difference in capacity and over any distance. The interface utilizes request and acknowledge phases and signals and an initiator-target relationship between components that allow each side to throttle the communication rate to an accepted level for each component or achieve a desired bit error rate.

Abstract: Techniques are disclosed regulating an amount of power consumed by a server from a set of power supplies in which at least one power supply of the set is inactive. The power to a server, upon detecting that at least one power supply is inactive, is restricted based on a degree to which a power threshold value for the remaining power supplies is exceeded. The applied power reduction may be based on a proportion of a measurement interval during which an alert signal is received. The longer the alert signal is received by the system, the more server power consumption is reduced.

Abstract: A computer-implemented method of controlling communication resources and computation resources of a computerized system includes continually monitoring dual observables. The dual observables include one or more communication observables pertaining to one or more communication channels of the system, and one or more compute observables pertaining to a computational workload execution by a processor of the system. The method also includes jointly adjusting dual resources of the system based on the dual observables monitored, where the dual resources include communication resources for the one or more communication channels, and computation resources for the computational workload execution. Such a method can be used for sprinting both communication and computational resources, in a consistent way, for the system to best cope with temporary situations, in terms of both workload execution and data traffic. The invention is further directed to related systems and computer program products.

Abstract: Systems and methods are disclosed for scheduling threads on an asymmetric multiprocessing system having multiple core types. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Metrics for workloads offloaded to co-processors can be tracked and integrated into metrics for the offloading thread group.

Abstract: Apparatuses comprising data processing circuitry and a wakeup interrupt controller and methods of operating the apparatuses are disclosed. Prior to the processing circuitry entering a low power state, indications of pending interrupts are transferred to the wakeup interrupt controller. Further indications of interrupts received whilst the processing circuitry is in the low power state may be accumulated in the wakeup interrupt controller. When the wakeup interrupt controller receives a wakeup signal, the indications of pending interrupts are transferred to the processing circuitry and the processing circuitry exits the low power state.

Abstract: Methods that can transition between multiple operating states are disclosed. One method includes monitoring an amount of power consumed by an information handling device operating in an idle state after transitioning from an active state to the idle state, transitioning an operating state of the information handling device to the active state in response to detecting that the amount of power consumed by the information handling device in the idle states exceeds a predetermined power consumption threshold value, and causing the operating state of the information handling device to transition back to the idle state subsequent to transitioning to the active state. Apparatuses and computer program products for performing the method are also disclosed.

Abstract: A system for allocating power includes a plurality of receptacles and a power delivery controller communicatively coupled to the plurality of receptacles. The power delivery controller is to: detect a new connection to a first receptacle of the plurality of receptacles; receive a request from the first receptacle which would exceed an amount of uncommitted available power; request a device attached to a second receptacle of the plurality of receptacles reduce an amount of power being received from the second receptacle; and in response to detecting a reduction of power to the second receptacle, provide power to the first receptacle as indicated in the request.