Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to reduce temperature of a networked device. An example apparatus includes, a temperature threshold monitor to identify a temperature condition associated with the device, a window information retriever to retrieve a current value of a network receive capacity parameter, and a window adjustor to reduce the temperature of the device by generating a modified network receive capacity parameter, the modified network receive capacity parameter based on a ratio of the current value of the network receive capacity parameter and a decrease factor.

Abstract: Examples herein relate to assigning, by a system agent of a central processing unit (CPU), an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent. Avoiding throttling of the system agent can include maintaining a minimum performance level of the system agent. A minimum performance level of the system agent can be based on a minimum operating frequency. Assigning, by a system agent of a central processing unit, an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent can avoid a thermal limit of the CPU. Avoiding thermal limit of the CPU can include adjusting the operating frequency to the core group to avoid performance indicators of the CPU. A performance indicator can indicate CPU utilization corresponds to Thermal Design Point (TDP).

Abstract: A system and method of protecting the input components of a power supply. An input overcurrent protection module is provided, which may be implemented in firmware, which monitors the input current through an input interface of the power supply. When the input current exceeds a threshold current (i.e., a current above the maximum rating of an input component, such as an input cable), the input current protection module determines whether an input overcurrent event is occurring. When it is determined that an input overcurrent event has occurred, the input current protection module disables the output circuitry of the power supply and triggers a few timers. The input overcurrent protection module continues to monitor the input and, if the input current continues to exceed the threshold current, is configured to shut down the power supply. In this way, input components may be protected from overcurrent issues in high-power systems.

Abstract: Example implementations relate to power supply controllers. In some examples, a controller can include instructions to: set a power threshold for a power supply coupled to a computing component when the computing component is operating in a first state, determine when the computing component is alternating from the first state to a second state, and allow the power supply to exceed the power threshold for a fixed period of time in response to the computing component alternating from the first state to the second state.

Abstract: In one embodiment, the voltage droop monitoring circuit includes a ring oscillator circuit block configured to generate a plurality of oscillation signals and configured to output a selected oscillation signal from one of the plurality of oscillation signals based on a first control signal. The first control signal is based on a power supply voltage of a functional circuit block. The voltage droop monitoring circuit further includes a counter configured to generate a count value based on the selected oscillation signal, and a droop detector configured detect droop in the power supply voltage of the functional circuit block based on the count value and at least one threshold value.

Abstract: Disclosed in the present application are a control device, method and equipment for a processor. The control device for the processor comprises: an arithmetic circuit and a memory, the arithmetic circuit being connected to the memory. The arithmetic circuit is used to output a control signal according to acquired sensor data, and the control signal is used to control a processor. The control device, method and equipment for the processor according to the present invention may be used to determine whether it is necessary to start the processor according to preset key information, or whether it is necessary to reduce the energy consumption of a processor which is currently in operation, thereby improving endurance.

Abstract: A heterogeneous microprocessor configured to perform classification on an input signal. The heterogeneous microprocessor includes a die with a central processing unit (CPU) a programmable feature-extraction accelerator (FEA) and a classifier. The FEA is configured to perform feature extraction on the input signal to generate feature data. The classifier is configured to perform classification on the feature data and the CPU is configured to provide processing after classification. The FEA may be configured with a plurality of Gene-Computation (GC) Cores. The FEA may be configured for genetic programing with gene depth constraints, gene number constraints and base function constraints. The classifier may be a support-vector machine accelerator (SVMA). The SVMA may include training data based on error-affected feature data. The heterogeneous microprocessor may also include an automatic-programming & classifier training module.

Abstract: A storage system and an operating method thereof are disclosed. The storage system includes a nonvolatile memory that stores data; a computing device to perform data processing on input data provided from the nonvolatile memory or a host outside the storage system; and a controller to control a writing operation and a reading operation of the nonvolatile memory, monitor an operating state of the computing device while the computing device is performing the data processing, and dynamically manage power of the computing device according to a monitoring result.

Abstract: To provide more uniform performance levels for solid state drive (SSDs), the static power level used by an SSD in an idle state is measured and used to determine a static power offset for each of the drives. The static power offset is set as a parameter for the SSD and used to offset a received power supply level for use on the drive. For a data storage system of multiple SSDs, a common scaling factor can be used to set the degree to which the static power offset is implemented, allowing for a choice between uniformity of power and uniformity of performance for the SSDs of a data storage system.

Abstract: In some aspects, the present disclosure provides a method for power management. The method includes receiving, by a power management unit (PMU), signaling indicative of a first plurality of latency durations from a first plurality of clients, each of the first plurality of latency durations corresponding to one of the first plurality of clients, wherein each of the first plurality of clients is configured to utilize a first shared resource for communication of data. In certain aspects, the method also includes selecting, by the PMU, a first latency duration from the first plurality of latency durations based on a determination that the first latency duration is the shortest latency duration of the first plurality of latency durations, and transitioning, by the PMU, the first shared resource from an active state to the first idle state.

Abstract: In general, this disclosure describes techniques for using a random number generator to affect the lengths of clock cycles in a clock waveform that drives the timing of operations performed by processing circuitry. In one example, the processing circuitry includes a central processing unit and a clock generator. The clock generator is configured, upon receiving an indication of a boot command for the processing circuitry, generate a random number using a true random number generator and generate, based at least in part on the random number, an output clock waveform indicating at least a length of a clock cycle for the central processing unit. The central processing unit is configured to execute a boot sequence for at least the processing circuitry using the output clock waveform.

Abstract: The present disclosure relates to a semiconductor system including a semiconductor device and a controller. The semiconductor device outputs a temperature code corresponding to an internal temperature thereof. The controller controls, based on the temperature code, the semiconductor device to set a temperature measurement mode among at least two temperature measurement modes having different temperature measurement periods and to measure the internal temperature in the set temperature measurement mode.

Abstract: A control circuit is provided. A memory is configured to store a program code. A central processing unit (CPU) executes a plurality of instructions according to the program code. When a specific instruction is executed by the CPU, the CPU generates a control signal. A power mode management circuit generates a selection signal according to the control signal. A processing circuit transforms first power data according to the selection signal. A first storage circuit stores the first power data. The processing circuit generates first set data and second set data according to first power data. A first specific device operates in a first power mode according to the first set data. A second specific device operates in a second power mode according to the second set data. The first storage circuit, the power mode management circuit and the processing circuit are in an always-on state.

Abstract: In an embodiment, a method of operating a radar includes: transmitting a radiation pulse with the radar during an active mode; asserting a sleep flag after transmitting the radiation pulse; turning off a crystal oscillator circuit of the radar after the sleep flag is asserted; clocking a counter of the radar with a low power oscillator during a low power mode after the sleep flag is asserted; asserting a timer flag when the counter reaches a first threshold; and transitioning into the active mode after the timer flag is asserted.

Abstract: A data processing apparatus comprises a plurality of processor circuits to process an event stream comprising one or more high energy events. Each of the plurality of processor circuits draws power from a same power rail. Power management circuitry performs power consumption management by controlling a voltage supply to the power rail, and a frequency of a clock signal provided to the plurality of processor circuits. Status analysis circuitry obtains a status of the individual processing load of each of the processor circuits and restriction circuitry performs high energy event restriction on each of the plurality of processor circuits. The power consumption management and the high energy event restriction are both based on the individual processing load of each of the plurality of processor circuits and each of the processor circuits is restrictable by the restriction circuitry independently of others of the processor circuits.

Abstract: A semiconductor device containing a CPU capable of receiving an interrupt request signal and a task control circuit is provided. The semiconductor device includes a CPU (processor), a save circuit, and a task control circuit. The CPU includes a program counter that is updated when a task is executed. The semiconductor device includes an interrupt-related data save circuit that stores the data of the program counter when the CPU receives a CPU interrupt request signal. The data of the program counter stored in the interrupt-related data save circuit is stored in an save circuit and is used for restoring from the interrupt processing.

Abstract: A system for detecting a false linkup state in an Ethernet communication link includes at least one processor programmed or configured to determine a block type of a block of bits received from a serializer/deserializer (SerDes), increment a first counter based on determining that the block type of the block of bits corresponds to a data block type or an error block type, determine whether the first counter satisfies a first threshold, enable a flag indicating that there is a false linkup state in an Ethernet communication link, and transmit a message indicating that there is a false linkup state for the Ethernet communication link to an Ethernet network device that is a link partner of the Ethernet communication link. A method and a computer program product are also provided.

Abstract: Systems and methods are disclosed for scheduling threads on an asymmetric multiprocessing system having multiple core types. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Metrics for workloads offloaded to co-processors can be tracked and integrated into metrics for the offloading thread group.

Abstract: Apparatus, systems, methods, and articles of manufacture to manage power of deep learning accelerator systems are disclosed. An example apparatus includes a power manager and a power controller. The power manager is to generate a power table to allocate power frequencies between an accelerator and memory based on a ratio of compute tasks and bandwidth tasks in a first workload; update the power table based on a request to at least one of add a second workload or remove the first workload; and determine an index into the power table. The power controller is to determine a power consumption based on the power table; determine whether to update the index based on a power budget and the power consumption; and allocate power to the accelerator and the memory according to the power table.

Abstract: Disclosed are an integrated circuit for controlling function modules to a low-power status depending on an operating status, an electronic device, and a control method thereof. An integrated circuit includes at least one clock generator, a clock distribution circuit that distributes a clock generated by the at least one clock generator, a plurality of function modules that receive the clock distributed by the clock distribution circuit, a monitoring circuit that monitors operating statuses of the at least one clock generator and the clock distribution circuit, a memory, and at least one control circuit.

Abstract: In some examples, a non-transitory machine-readable medium can include instructions executable by a processing resource to: monitor system power for a computing system that includes a first computing component type and a second computing component type, determine a power event type for the computing system based on the monitored system power, and alter a power limit of the second computing component type by a predetermined increment based on the power event type while maintaining a power limit of the first computing component type when the second computing component type is a sub-system of the computing system.

Abstract: A memory sub-system includes a plurality of memory components where at least two of the memory components are configured to operate at different supply voltages. A capacitive voltage divider (CVD) configured to, responsive to a status of use of each of the memory components, select between a plurality of connections of a plurality of capacitors to reduce an input voltage of the memory sub-system. The plurality of connections is configured to provide different voltage magnitudes that correspond to the different supply voltages, and the CVD is further configured to output the different supply voltages to enable the use of each of the memory components.

Abstract: A computing device, a power consumption prediction method thereof, and a non-transitory computer-readable storage medium are provided. In one embodiment, leakage power consumption of a graphics processor is obtained. Switching power consumption data corresponding to the graphics processor running a frame of image is obtained. Switching power consumption is estimated according to the switching power consumption data. Overall power consumption of the graphics processor is obtained according to the leakage power and the switching power consumption. Overall power consumption of the graphics processor processing one frame of image is estimated based on the overall power consumption. Power consumption performance of the graphics processor is therefore predicted in real-time.

Abstract: An information processing apparatus includes a memory; and a processor coupled to the memory and configured to generate a performance model for calculating a performance value of an application program from a power restriction for each set of parameters of the application program, based on data acquired when a computing apparatus executes the application program for each set of parameters of the application program under each of a plurality of power restrictions; calculate, for each set of parameters of the application program, the performance value of the application program from a first power restriction different from any of the plurality of power restrictions, based on the performance model generated for each set of parameters of the application program; and output a set of parameters of the application program corresponding to a highest performance value of the calculated performance values.

Abstract: According to one embodiment, a DP accelerator includes one or more execution units (EUs) configured to perform data processing operations in response to an instruction received from a host system coupled over a bus. The DP accelerator includes a security unit (SU) configured to establish and maintain a secure channel with the host system to exchange commands and data associated with the data processing operations. The DP accelerator includes a time unit (TU) coupled to the security unit to provide timestamp services to the security unit, where the time unit includes a clock generator to generate clock signals locally without having to derive the clock signals from an external source. The TU includes a timestamp generator coupled to the clock generator to generate a timestamp based on the clock signals, and a power supply to provide power to the clock generator and the timestamp generator.

Abstract: A chip includes a receiving, a transmission, a control, and a switch circuit. The receiving circuit is operated at a first voltage and receives a first data. The transmission circuit is operated at the first voltage. Under general mode, the control circuit is operated at a second voltage and generates a second data to the transmission circuit according to the first data. The control circuit includes a first clock source configured to provide a first clock under general mode. The control circuit is operated according to the first clock. Under general mode, the switch circuit is operated at the first voltage, and controls the second voltage to pause the second voltage supplying to the control circuit to enter sleep mode. Under sleep mode, the switch circuit controls the supply of the second voltage to the control circuit according to the first data to return to general mode.

Abstract: A method for storing input data in a flash memory. The method comprising generating a codeword by encoding the input data with an error correcting code and generating a shaped codeword by applying a shaping function to at least a part of the codeword. The shaping function comprising logically inverting every n-th occurrence of a bit associated with a high-charge storage state in the part of the codeword. The method further comprising writing the shaped codeword to the flash memory, generating an estimated shaped codeword by reading the flash memory, generating soft decision information for the estimated shaped codeword, and retrieving the input data by decoding the soft decision information using an error correcting code soft decoder.

Abstract: Embodiments of the invention include a communication interface and protocol for allowing communication between devices, circuits, integrated circuits and similar electronic components having different communication capacities or clock domains. The interface supports communication between any components having any difference in capacity and over any distance. The interface utilizes request and acknowledge phases and signals and an initiator-target relationship between components that allow each side to throttle the communication rate to an accepted level for each component or achieve a desired bit error rate.

Abstract: Techniques are disclosed regulating an amount of power consumed by a server from a set of power supplies in which at least one power supply of the set is inactive. The power to a server, upon detecting that at least one power supply is inactive, is restricted based on a degree to which a power threshold value for the remaining power supplies is exceeded. The applied power reduction may be based on a proportion of a measurement interval during which an alert signal is received. The longer the alert signal is received by the system, the more server power consumption is reduced.

Abstract: A computer-implemented method of controlling communication resources and computation resources of a computerized system includes continually monitoring dual observables. The dual observables include one or more communication observables pertaining to one or more communication channels of the system, and one or more compute observables pertaining to a computational workload execution by a processor of the system. The method also includes jointly adjusting dual resources of the system based on the dual observables monitored, where the dual resources include communication resources for the one or more communication channels, and computation resources for the computational workload execution. Such a method can be used for sprinting both communication and computational resources, in a consistent way, for the system to best cope with temporary situations, in terms of both workload execution and data traffic. The invention is further directed to related systems and computer program products.

Abstract: Systems and methods are disclosed for scheduling threads on an asymmetric multiprocessing system having multiple core types. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Metrics for workloads offloaded to co-processors can be tracked and integrated into metrics for the offloading thread group.

Abstract: Apparatuses comprising data processing circuitry and a wakeup interrupt controller and methods of operating the apparatuses are disclosed. Prior to the processing circuitry entering a low power state, indications of pending interrupts are transferred to the wakeup interrupt controller. Further indications of interrupts received whilst the processing circuitry is in the low power state may be accumulated in the wakeup interrupt controller. When the wakeup interrupt controller receives a wakeup signal, the indications of pending interrupts are transferred to the processing circuitry and the processing circuitry exits the low power state.

Abstract: Methods that can transition between multiple operating states are disclosed. One method includes monitoring an amount of power consumed by an information handling device operating in an idle state after transitioning from an active state to the idle state, transitioning an operating state of the information handling device to the active state in response to detecting that the amount of power consumed by the information handling device in the idle states exceeds a predetermined power consumption threshold value, and causing the operating state of the information handling device to transition back to the idle state subsequent to transitioning to the active state. Apparatuses and computer program products for performing the method are also disclosed.

Abstract: A system for allocating power includes a plurality of receptacles and a power delivery controller communicatively coupled to the plurality of receptacles. The power delivery controller is to: detect a new connection to a first receptacle of the plurality of receptacles; receive a request from the first receptacle which would exceed an amount of uncommitted available power; request a device attached to a second receptacle of the plurality of receptacles reduce an amount of power being received from the second receptacle; and in response to detecting a reduction of power to the second receptacle, provide power to the first receptacle as indicated in the request.

Abstract: An information processing apparatus capable of operating by switching between a first power mode and a second power mode with less power consumption than the first power mode is provided. The apparatus comprises a plurality of processors and a plurality of memories provided in correspondence with the plurality of processors, and controls power supplied to the plurality of processors and the corresponding plurality of memories. When operating in the second power mode, each of the plurality of memories stores a program to be loaded by a corresponding processor of the memory, and when one of the plurality of processors and the corresponding memory operate, power supply to processors and memories other than the one processor and the corresponding memory is limited.

Abstract: In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g. with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.

Abstract: A control device for adjusting the output voltage of a voltage generator, wherein the control device includes a master circuit, a slave circuit, and a power-scaling control circuit, is provided. The master circuit is coupled to a system bus. The slave circuit is coupled to the system bus. The power-scaling control circuit is coupled between the master circuit and the slave circuit. In response to the master circuit sending a voltage-scaling command, the power-scaling control circuit sets a control signal at a suspension level so that the slave circuit sets a specific signal transmitted by the system bus at a wait level. In response to the specific signal being at the wait level, the master circuit stops accessing the first specific device of the slave circuit. In response to the control signal being at the suspension level, the power-scaling control circuit adjusts the output voltage.

Abstract: A method for adjusting a wireless modem includes: a channel parameter of a wireless modem at a present moment is acquired; a target clock frequency and a target working voltage of the wireless modem are generated, according to the channel parameter, with a neural network that is pre-trained; and a working voltage and a clock frequency of the wireless modem are adjusted to the target working voltage and the target clock frequency, respectively.

Abstract: A display device may include a display panel, a sensor unit, and a touch driver. The sensor unit is provided on the display panel and may output a sensing signal corresponding to a touch input. The sensor unit may include a first electrode and may include a conductive layer provided between the display panel and the first electrode and spaced from the first electrode. The touch driver may include a signal receiver. The signal receiver may include a first input terminal electrically coupled to the first electrode, may include a second input terminal electrically coupled to the conductive layer, may receive the sensing signal, and may output a signal corresponding to a voltage difference the first input terminal and the second input terminal.

Abstract: The invention relates to a multicore processor and a method for dynamically adjusting a supply voltage and a clock frequency, with which an individual supply voltage and dock frequency adjustment, which depends on a current computing load, is facilitated for each processor core of a multicore processor. Thus, an assembly is disclosed where a local queue memory unit which is connected to the processor core, the internal memory unit, and the level converter is arranged in a voltage-variable region of the processor element in order to store events to be processed by the processor core. The invention is also directed to a method in that the required supply voltage U and the required clock frequency f are adjusted for each cycle in a controlled manner by the processor core of the respective processor element depending on the detection of a number of events to be processed which are stored in an internal queue memory unit.

Abstract: To accomplish this, this memory access system monitors a use-memory-bandwidth which indicates a total of memory bandwidths used between a memory and a plurality of masters, and determines whether the use-memory-bandwidth is equal to or larger than the first threshold. Based on the above-described determination result, this memory access system also restricts access to the memory by a master of low priority out of the plurality of masters.

Abstract: Embodiments relate to improving user experiences when executing binary code that has been translated from other binary code. Binary code (instructions) for a source instruction set architecture (ISA) cannot natively execute on a processor that implements a target ISA. The instructions in the source ISA are binary-translated to instructions in the target ISA and are executed on the processor. The overhead of performing binary translation and/or the overhead of executing binary-translated code are compensated for by increasing the speed at which the translated code is executed, relative to non-translated code. Translated code may be executed on hardware that has one or more power-performance parameters of the processor set to increase the performance of the processor with respect to the translated code. The increase in power-performance for translated code may be proportional to the degree of translation overhead.

Abstract: It is desirable to reduce power consumption without reducing a function in an electronic apparatus operating in a plurality of modes different in power consumption from one another. A processor operates in a normal mode, in which power consumption is higher, of two modes different in power consumption from each other, and stops operation in a power saving mode, in which the power consumption is lower, of the two modes. A control section outputs a power saving mode control command instructing an increase or decrease of a supply electric power to a digital circuit different from the processor in the power saving mode. A power source managing integrated circuit increases or decreases the supply electric power to the digital circuit in accordance with the power saving mode control command, and outputs the increased or decreased supply electric power.

Abstract: In one embodiment, a processor includes a non-volatile storage to store a plurality of configurations for the processor, the non-volatile storage including a plurality of entries to store configuration information for the processor for one of the plurality of configurations, the configuration information including at least one of a guaranteed operating frequency and a core count, at least one of the entries to store the core count. The processor further includes a power controller to control the processor to operate at one of the plurality of configurations based at least in part on a selected thermal set point of a plurality of thermal set points of the processor, each of the plurality of thermal set points associated with one of the configurations. Other embodiments are described and claimed.

Abstract: In some aspects, the present disclosure provides a method for bandgap voting. In some configurations, the method includes receiving: (i) a first set of votes from a first client of a system, and (ii) a second set of votes from a second client of the system, wherein the first set of votes indicate a first desired set of operational parameters for controlling a plurality of physical resources in the system, wherein the second set of votes indicate a second desired set of operational parameters for controlling the plurality of physical resources, and wherein the plurality of physical resources are shared by the first client and the second client.

Abstract: Techniques and mechanisms for identifying a power state to be provided with an integrated circuit (IC). In an embodiment, evaluator circuitry of a system-on-chip is programmable based on multiple criteria which are each for a different respective power mode. Programming of the evaluator circuitry enables concurrent evaluations each to determine, for a different respective power mode, whether a detected state of the IC is able to accommodate said power mode. Results of the evaluations are communicated, in parallel with each other, to circuitry which selects one such power mode based on relative priorities of the power modes with respect to each other. In another embodiment, the evaluator circuitry comprises an array of circuit cells which are configurable each to perform a different respective evaluation based on a corresponding combination of a test condition and a detected condition of the IC.

Abstract: Methods, systems, and apparatuses are provided for balancing power delivery in a computing component between one or more power providers and power consumers. A power provider and multiple power consumers are identified. Once identified, a power delivery capability of the power provider and the power consumption demands of the power consumers may be determined. Power allocation factors are obtained that provide information regarding allocation of power between the power provider and the power consumers. In some instances, an interactive user interface may be provided that enables a user to configure a power allocation factor, such as a charging parameter for a power consumer. Using this information, a dynamic power allocation may be performed to allocate power from the power provider to the multiple power consumers.

Abstract: In one example, a printer with parallel/serial operational sequencing includes an engine control unit and an image processor unit each coupled to a set of sub-systems. A network unit is coupled to the image processor unit to monitor network packets while the engine control unit, the set of sub-systems, and the image processor unit are in sleep states. When a first predetermined packet is received, the network unit signals with a first modulation signal that the image processor unit is to awaken first before the image processor unit determines whether to awaken the engine control unit and any of the set of sub-systems. When a second predetermined packet is received, the network unit signals with a second modulation signal that the image processor unit, the engine control unit, and a portion of the set of sub-systems are to awaken at the same time.

Abstract: A computer system management method including the following steps is provided. First, a target value and at least one input parameter are set. The target value and the at least one input parameter are related to at least one of a first data type and a second data type, and the first data type is related to the second data type. Then, a first algorithm is determined based on a third data type, and an input value of the third data type is calculated by using the first algorithm. The third data type is related to the first data type and the second data type. Afterward, a second algorithm is determined based on the target value, the at least one input parameter, and the input value, and an estimated value of the second data type is calculated by using the second algorithm. A computer system is also provided.

Abstract: A processor includes processing engines, at least one performance counter, and a power control circuit. The at least one performance counter is to determine at least one interrupt rate metric for a first processing engine. The power control circuit is to determine, using the at least one performance counter, whether the at least one interrupt rate metric has reached a first threshold while the first processing engine is operating at a first frequency level, and in response to a determination that the at least one interrupt rate metric has reached the first threshold while the first processing engine is operating at the first frequency level, increase an operating frequency of the first processing engine from the first frequency level to a second frequency level.