Abstract: A power supply system includes a first energy storage, a second energy storage, a power transmission circuit, and circuitry. The circuitry is configured to acquire a remaining capacity and a temperature of the second energy storage. The circuitry is configured to determine a target remaining capacity range of the second energy storage in accordance with the temperature. The circuitry is configured to control the power transmission circuit to control power transmission among the electric load, the first energy storage, and the second energy storage such that the remaining capacity of the second energy storage is within the target remaining capacity range.

Abstract: Devices, systems and methods are disclosed for limiting a number of hibernations based on a finite lifetime expectancy of nonvolatile memory. As the nonvolatile memory has a finite lifetime expectancy, a device may determine cumulative thresholds and associated session thresholds and may limit a frequency that the device hibernates. For example, the device may determine a cumulative number of hibernations and associate the cumulative number of hibernations with a cumulative threshold. The device may determine a session threshold corresponding to the cumulative threshold and may limit a number of hibernations using the session threshold. For example, the device may enter a hibernation state up to the session threshold and thereafter may enter a suspended state instead.

Abstract: A system includes at least one controlled device that is controlled based on control information output from an external device, and an image forming apparatus that forms an image on a recording material and communicate with the external device and the controlled device, wherein the image forming apparatus includes a transceiver that receives the control information from the external device and transmits the control information to the controlled device, and a transmission controller that stops the transmission of the control information by the transceiver or changes contents of the control information to be transmitted by the transceiver.

Abstract: A multi-core microprocessor is organized into a plurality of resource-associated domains including core domains, group domains, and a global domain. Each domain relates to either local resources, group resources, or global resources that are respectively used by a single core, a group of cores, or all the cores. Each core has its own independently settable target operating state selected from a plurality of possible target operating states that designate configurations for the local resources, group resources, and global resources. Each core is provided with coordination logic configured to implement or request implementation of the core's target operating state, but only to the extent that implementation of the target operating state would not reduce performance of any other core below its own target operating state.

Abstract: A nonvolatile queue manager queues entries of host data from one or more host channels to one or more write buffers for storage in one or more nonvolatile memory devices of a nonvolatile memory array. The nonvolatile queue manager compares a number of the entries queued to one or more nonvolatile memory holdup power write thresholds based on detecting a power loss event. The nonvolatile queue manager tracks one or more locations in the nonvolatile memory array targeted by one or more of the entries extending beyond the one or more nonvolatile memory holdup power write thresholds. The nonvolatile queue manager initiates a mitigation action on a subsequent restoration of power to handle the one or more locations in the nonvolatile memory array targeted by one or more of the entries extending beyond the one or more nonvolatile memory holdup power write thresholds.

Abstract: A DC power supply for preventing output from being misconnected to a power supply and its LED lamp and control system, comprise a DC power supply and an anti-misconnection module. The DC power supply comprises a positive output terminal and a negative output terminal. The anti-misconnection module comprises a positive access terminal and a negative access terminal which are electrically connected to the positive and negative output terminals of the DC power supply respectively, a NMOS transistor controlling on-off of the negative access terminal, a load access unit performing a turn-on operation of the NMOS transistor, a forward-blocking unit performing a turn-off operation of the NMOS transistor, and a backward access unit performing a turn-off operation of the NMOS transistor.

Abstract: As disclosed herein, a method, executed by a computer, includes comparing a current power consumption profile for a computing task with an historical power consumption profile, receiving a request for a computing resource, granting the request if the historical power consumption profile does not suggest a pending peak in the current power consumption profile or the historical power consumption profile indicates persistent consumption at a higher power level, and denying the request for the computing resource if the historical power consumption profile suggests a pending peak in the current power consumption profile and the historical power consumption profile indicates temporary consumption at the higher power level. Denying the request may include initiating an allocation timeout and subsequently ending the allocation timeout in response to a drop in a power consumption below a selected level. A computer system and computer program product corresponding to the method are also disclosed herein.

Abstract: A processor includes logic to generate a wakeup code value for a deep sleep state in which the processor is powered down, store the wakeup code value to a first location in a power domain in which power is maintained in the deep sleep state, store the wakeup code value to a second location in a non-volatile memory device, and initiate entry into the deep sleep state. The processor also includes logic to begin execution of a wakeup sequence upon waking up from the deep sleep state. The wakeup sequence includes a determination of whether a value read from the second location and a value read from the first location match. If they do not match, the processor triggers an exception handling sequence, which may include a secure boot sequence. If they match, the processor continues executing the wakeup sequence without executing a secure boot sequence.

Abstract: According to one embodiment, a memory system is connectable to a host including a first memory. The memory system includes a non-volatile second memory, a volatile third memory, and a controller. The controller uses the third memory as a work memory, and executes data transfer between the host and the second memory. The controller receives a first command to change a power mode from the host. The controller transfers first data to the first memory and transfers second data to the second memory in response to the receipt of the first command. The controller transmits a response of completion of data transfer. The first data and the second data are included in third data. The third data is data in the third memory.

Abstract: In some embodiments, a system includes a memory testing circuit configured to perform a test to determine whether a portion of a memory is operational at a specified amount of time after a power-up request by performing operations. The operations may include sending a power-up request to the portion. The operations may further include sending, at the specified amount of time after the power-up request, a write request for a write operation at the portion. The operations may further include sending a read request that requests a read operation for data written by the write operation. The operations may further include determining, based on data received in response to the read request, whether the portion correctly performed the read operation and the write operation.

Abstract: The present disclosure relates to a method and system for securing a performance state change of one or more processors. A disclosed method includes detecting a request to change a current performance state of a processor to a target performance state, and adjusting an operating level tolerance range of the current performance state to include operating levels associated with a transition from the current performance state to the target performance state. A disclosed system includes an operating system module operative to transmit a request for a performance state change of at least one processing core. The system includes performance state control logic operative to change the performance state of the at least one processing core based on the request.

Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.

Abstract: A serial point-to-point link interface to enable communication between a processor and a device, the high speed serial point-to-point link interface including a transmitter to transmit serial data, a receiver to deserialize serial data, and control logic to implement a protocol stack. The protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is maintained, and a second off state, in which the supply voltage is not to be provided to the device. The protocol stack provides a default recovery time to allow the device to begin a transition from the first off state to the active state prior to accessing the device. The protocol stack further provides for accessing the device prior to expiration of the default recovery time to complete the transition based on a device-advertised recovery time.

Abstract: Described herein are systems and methods that reduce power consumption for an electronics device including a display. The systems and methods alter video information in a display area and reduce power for a display device when a graphics item is enlarged and the enlargement threatens to increase perceived luminance for the graphics item or increase aggregate luminance for the display area. Altering the video information reduces the luminance of video information in at least the graphics item when enlarged. This may offset perceived luminance gained by human visual processing when an item increases in size. If the graphics item is smaller than the display area after enlargement, then other video information in the display area may also be altered to conserve power.

Abstract: A system on a chip (SoC) is provided with a multicore processor, a level-2 (L2) cache controller, an L2 cache, an integrated memory controller, and a serial point-to-point link interface to enable communication between the multicore processor and a device. The interface implements a protocol stack and includes a transmitter to transmit serial data to the device and a receiver to deserialize an incoming serial stream. The protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is to be provided to the device, and a second off state, in which the supply voltage is not to be provided to the device. In response to an indication the device is ready to enter the active state, the protocol stack provides for accessing the device prior to expiration of a default recovery time to complete the transition.

Abstract: A battery monitoring unit includes a control IC, a CPU, and a load circuit. In the inside of the battery monitoring unit, the control IC and the CPU each of which is a control circuit are connected to a unit internal ground that is common thereto. The load circuit is connected to a power ground different from the unit internal ground. In the inside of the battery monitoring unit, the power ground and the unit internal ground are connected with each other via a diode. The unit internal ground and the power ground are connected to an external ground that is common thereto via an electric wire extending from a first ground terminal and an electric wire extending from a second ground terminal, respectively.

Abstract: A method is provided for managing power consumption within a multi-core microprocessor. An operating system issues an operating system instruction to transition a recipient core to a targeted power and/or performance state that is one of many possible states into which a microprocessor can place a core. Each core of the microprocessor has its own target state, and different cores may have different target states. After receiving the instruction, the recipient core implements any settings associated with its target core state that wouldn't affect resources shared with other cores. The recipient core also initiates an inter-core discovery process to determine a target multi-core state of all the cores sharing the resource. The target multi-core state reflects one or more settings that match the settings of the recipient core's target core state as much as possible without lowering a performance of any resource-sharing core below that core's own target core state.

Abstract: An electronic device includes a first processor; and a second processor; and a third processor. The second processor is configured to detect an event, select one of the first and third processors to perform one or more operations associated with the event, and cause the selected processor to perform the one or more operations.

Abstract: A power supply controller system includes a power supply portion, arithmetic processing portions, and first and second monitoring circuits configured to monitor an integrity of power supply of the power supply portion. The first monitoring circuit instructs a second arithmetic processing portion to stop an operation thereof when a first watchdog timer is not reset for a predetermined period of time. The second monitoring circuit instructs a first arithmetic processing portion to stop an operation thereof when a second watchdog timer is not reset for a predetermined period of time. The first monitoring circuit further includes a third watchdog timer periodically reset by any one of the first arithmetic processing portion and the second arithmetic processing portion and instructs another arithmetic processing portion to stop an operation thereof when the third watchdog timer is not reset for a predetermined period of time.

Abstract: In a wearable terminal, a controller determines whether a direction of a display surface detected by a detector is within a first angle range. In a case where a latest direction of the display surface is out of the first angle range, the controller puts the display in a sleep state, but otherwise the controller puts the display in an active state. Furthermore, the controller specifies a second angle range from the second reference direction. The controller switches the display from the sleep state to the active state in a case the controller determines that the plurality of directions of the display surface detected in the first period and that the direction of the display surface newly detected by the detector is out of the second angle range. In the second display control, the display is switched from the sleep state to the active state even when the newly detected direction of the display surface is out of the first angle range.

Abstract: An image forming apparatus includes a fixing portion, a temperature detection portion, a power supply portion, a control portion, a photovoltaic module and a power storage/supply portion which stores power from the photovoltaic module and which performs power supply to the temperature detection portion when power supply from the power supply portion to the temperature detection portion is stopped. The control portion detects, when a return condition is satisfied, the temperature of the fixing portion based on the output of the temperature detection portion, and as a temperature on return is higher, the control portion starts fixing return processing at later timing whereas as the temperature on return is lower, the control portion starts the fixing return processing at earlier timing.

Abstract: Systems and methods for operating based on recovered waste heat are described. In one example, the method includes receiving recovered waste heat power and operating at least one system component of a recovered waste heat based computing device based on the recovered waste heat power, where the at least one system component is coupled to a non-volatile memory of the recovered waste heat based computing device. The method further includes preserving operational states of the at least one system component in the non-volatile memory based on a current power level associated with the recovered waste heat power.

Abstract: A control system includes a housing engaged to a mounting surface, a sensor contained within the housing, a microcontroller unit connected to the sensor, a server in communication with the sensor, and a terminal device in communication with the server. The system starts in an idle mode with the microcontroller having low power consumption. A gesture by a user associated with the mounting surface switches or toggles the operating mode of the control system into a ready mode. In the ready mode, the microcontroller has higher power consumption so as to connect the sensor to the server, and gestures by the user associated with the mounting surface can control the terminal device. The system alerts the switch in operating mode and filters background environment so only gestures are interpreted for switching operation mode or for issuing commands of the terminal device.

Abstract: An apparatus and method for reducing power consumption of a portable terminal are provided. More particularly, an apparatus and method for reducing power consumption generated in an idle state in order to solve a power consumption problem in a portable terminal are provided. The apparatus includes a state determination unit which is configured independently from an application processor for controlling applications and which wakes up when entering an idle mode to allow the application processor to sleep, and thereafter determines a state of the portable terminal, and if it is determined that the portable terminal escapes from the idle mode, allows the application processor to wake up.

Abstract: A data storage system includes a host having a write buffer, a memory region, a submission queue and a driver therein. The driver is configured to: (i) transfer data from the write buffer to the memory region in response to a write command, (ii) generate a write command completion notice; and (iii) send at least an address of the data in the memory region to the submission queue. The host may also be configured to transfer the address to a storage device external to the host, and the storage device may use the address during an operation to transfer the data in the memory region to the storage device.

Abstract: Methods and mechanisms for improved performance in a system with power management are described. A system includes a data storage device configured to store data and a display control unit configured to retrieve data from the data storage device. The data storage device may be placed in a reduced power state that results in increased latencies for accessing data within the device. The display control unit is configured to monitor an amount of data available for processing within the display control unit. In response to determining the amount of data has fallen to a threshold level, and in anticipation of a forthcoming data access request, the display control unit conveys an indication that prevents the data storage device from entering or remaining in the reduced power state. Subsequently, the display control unit conveys a request for data to the data storage device which will not be in the reduced power state.

Abstract: Technology for concurrently powering equipment from multiple power sources, and the control thereof is disclosed. One example implementation of the technology includes a first power supply that powers equipment from a first power source and a second power supply that also powers the equipment from a second power source while the equipment is being powered by the first power supply. A target direct current (DC) output voltage of at least one of the power supplies is changed, thereby changing a ratio of the power being drawn from the first power supply to the power being drawn from the second power supply.

Abstract: The present disclosure provides a technology for suitably generating a post-system-resume screen. An information processor includes: a mode control section adapted to select power saving mode as an operation mode; and a screen control section adapted to generate a display screen, in which when a user logs in after the mode control section switches the mode from power saving mode to normal mode, the screen control section generates a display screen to match the user who has logged in.

Abstract: A remote override system may comprise a remote device and a local device. The remote device may include a remote device computer having a remote device processor and a remote device communication interface, and an outgoing override signal handler capable of sending an override signal by way of the remote device communication interface. The local device may include a local device computer having a local device processor and a local device communication interface, and an incoming override signal handler capable of receiving the override signal by way of the local device communication interface. The override signal may be capable of causing override of a power saving mode at the local device.

Abstract: A method for processing data includes receiving in a peripheral device, which is connected by a bus to a host processor having multiple host resources, information regarding respective power states of the host resources. The data are selectively directed from the peripheral device to the host resources responsively to the respective power states.

Abstract: Embodiments of the present disclosure provide a monitoring report generation method where the method includes: receiving a monitoring parameter broadcast by a base station; monitoring energy of each discovery resource in a resource pool within a discovery time domain; determining a busy resource and an idle resource; and generating a monitoring report when a proportion of the busy resource or the idle resource in a predetermined quantity of consecutive discovery time domains meets a reporting condition corresponding to the busy resource or the idle resource, and sending the monitoring report to the base station. This resolves a problem in the related technology that: because D2D user equipment cannot accurately obtain a quantity of resource collision times in a cell, the base station cannot accurately learn a resource status in the cell, and it is ensured that the base station can accurately learn the resource status in the cell.

Abstract: A processor begins exception processing in response to an exception event. Exception processing by the processor is halted during exception processing to facilitate debugging. The exception event can be a reset exception event or an interrupt exception event. Normal exception processing by the data processor can be resumed after debugging, or exception processing by the data processor can be aborted to allow the normal execution of instructions by the data processor to resume. An exception event can be selectively treated as an interrupt or a reset.

Abstract: A method and apparatus for controlling hard drive power consumption and controlling a hard drive power consumption management service are provided. The method includes detecting whether a fault exists in a hard drive in a node hard drive group. The method further includes, if there is no fault detected in the hard drive in the node hard drive group, controlling the hard drive in the node hard drive group to convert the hard drive between preset modes of power consumption by a hard drive power consumption management service.

Abstract: In one embodiment, a method includes a server receiving activity data from a plurality of computing devices, wherein the activity data is associated with running a particular application; identifying, based on the activity data, a pattern of execution related to executing one or more sequences of instructions associated with running the particular application; determining, based on the pattern of execution, a clocking policy for running the particular application, wherein the clocking policy is configured to modify a clock speed of one or more processors of a particular computing device while running the particular application; and sending the clocking policy to the particular computing device.

Abstract: An access method of a nonvolatile memory device included in a user device includes receiving a write request to write data into the nonvolatile memory device; detecting an application issuing the write request, a user context, a queue size of a write buffer, an attribute of the write-requested data, or an operation mode of the user device; and deciding one of a plurality of write modes to use for writing the write-requested data into the nonvolatile memory device according to the detected information. The write modes have different program voltages and verify voltage sets.

Abstract: An image forming apparatus includes: an accepting unit to accept user operations to transition the apparatus from a standby state to a power save state; a detecting unit to detect objects around the apparatus; and a power control unit to transition the apparatus from the power save state to the standby state according to detection of an object by the detecting unit, and to transition the image forming apparatus from the standby state to the power save state according to user operations accepted at the accepting unit. The power control unit prohibits the apparatus from transitioning from the power save state to the standby state according to the detection of the object, until a user, which performed operations accepted by the accepting unit to transition the apparatus from the standby state to the power save state, thereafter ceases to be detected by the detecting unit.

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract: An intelligent electrical power network control and/or protection device comprises at least one power supply connection for connecting the device to a main power source and an auxiliary power source and at least one unit configured to monitor main power, the unit being configured to activate a signal indicating lack of main power in response to lack of main power. The device further comprises at least one unit configured to provide a state control operation for changing an operating state of at least one unit of the device or an operating state of at least one unit to be connected to the device from an operative mode t a power saving mode in response to the activated signal indicating the detected lack of main power.

Abstract: In one example, a method includes receiving, by a power switching device and via a connector of the power switching device, a signal that causes the power switching device to transition from a first operating mode to a second operating mode in which the power switching device consumes less current than the first operating mode. In this example, the method also includes, responsive to determining, while the power switching device is in the second operating mode, an occurrence of one or more events, outputting, by the power switching device and via the same connector of the power switching device, a signal that indicates the occurrence of the one or more events.

Abstract: Embodiments of processors, methods, and systems for directed wakeup into a secured system environment are disclosed. In one embodiment, a processor includes a decode unit, a control unit, and a messaging unit. The decode unit is to receive a secured system environment wakeup instruction. The control unit is to cause wake-inhibit indicator to be set for each of a plurality of responding logical processor to be kept in a sleep state. The messaging unit is to send a wakeup message to the plurality of responding logical processors, wherein the wakeup message is to be ignored by each of the plurality of responding logical processors for which the wake-inhibit indicator is set.

Abstract: Embodiments of a control device for an electronic fuse and a method for controlling an electronic fuse are described. Embodiments of a control device for an electronic fuse may include an interface configured to receive a current from a transistor device of the electronic fuse. Additionally, the control device may further include a sense-and-control device coupled to the interface and configured to detect an increase in the current received at the interface under a standby mode of the electronic fuse and to output an interrupt signal in response to the increase in the current received at the interface.

Abstract: According to an embodiment, provided is an electronic device that includes: an energy generation unit that generates electrical power; an accumulating unit that accumulates therein the electrical power generated by the energy generation unit; and a network control unit that includes: a first function unit that performs network response processing; a second function unit that performs network response processing with a relatively smaller processing load than the network response processing performed by the first function unit; and a third function unit that controls the electrical power supply to the function units. The third function unit stops the electrical power supply to the first function unit in a predetermined standby operation mode that is standby for a network response request, and supplies the electrical power to the second function unit directly from the energy generation unit bypassing the accumulating unit.

Abstract: The present invention provides a status switching method applied to a slave device. The status switching method includes: receiving a command wrapper from a host device; receiving a status query command corresponding to the command wrapper from the host device; transmitting a status wrapper to the host device in response to the status query command; and refusing to enter a low-power status corresponding to a switch status request when the switch status request is received during a specific period, wherein the specific period starts when the command wrapper is received and ends when the status wrapper is transmitted.

Abstract: A method and apparatus for performing inter-lane power management includes de-energizing one or more execution lanes upon a determination that the one or more execution lanes are to be predicated. Energy from the predicated execution lanes is redistributed to one or more active execution lanes.

Abstract: A method of testing a computer program implementation according to a predefined design model, the program implementation having at least one method under test, employs a computer to generate a post-method corresponding to the method under test. A computer is further used to automatically generate a set of test cases. Then, using the automatically generated set of test cases, the computer explores different execution paths of the computer program implementation, by applying those test cases to both the method under test and the generated post-method, to reveal behavior that is not consistent with the behavior specified by the design model.

Abstract: Methods and systems described herein relate to broadcasting an advertisement event on a wireless channel. An example method includes generating, based on data, a data signal including one or more data packets, where each of the one or more data packets is a non-connectable and non-scannable data packet; generating an RF signal using an oscillator circuit; directly modulating the RF signal, based on the data signal, to generate a modulated RF signal; amplifying the modulated RF signal; broadcasting the amplified modulated RF signal on the wireless channel, where the amplified modulated RF signal is associated with the advertisement event.

Abstract: A control circuit configured to conserve battery in a mobile device is described. The control circuit upon receiving an input signal from an input sensor sends a suspend signal to the power management integrated circuit (PMIC), which may turn off power in the rest of device and keep the processor and PMIC powered on, thereby transitioning the mobile device into a suspend mode. After a predetermined period of time, the mobile device saves all processes running on the processor and registry content of the memory in a non-volatile memory on the device and shuts off the PMIC and the processor to transition into a hibernate mode. The input sensor and control circuit which receive power directly from the battery management can turn on the PMIC and the processor upon receiving an awake signal from the input sensor, thereby transitioning the device back to an awake mode.

Abstract: A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes sideband circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.

Abstract: A communication system and an IoT system are provided. The IoT system is applicable to a wireless network system including an access point. The IoT system includes a WiFi module and a GPIO device. The WiFi module is configured to connect to the access point. The GPIO device is configured to provide a plurality of wake-up signals to the WiFi module through a GPIO pin. A predetermined time period between any two of wake-up signals is greater than an interval between two delivery traffic indication messages from the access point. The WiFi module includes a timer and a power management unit, the power management unit drains power to transfer the WiFi module from a sleep mode to a normal mode after the timer receives the wake-up signal.

Abstract: Certain aspects of the present disclosure generally relate to wireless communications and, more specifically, to power savings based on distributed enhanced machine type communication (eMTC) functions, for example, between an applications processor and a modem of an eMTC device. An example method generally includes entering a power saving mode (PSM), wherein entering the PSM includes performing a first power collapse of an applications processor of the wireless node and a modem of the wireless node into a low power state; exiting the PSM at expiry of a wake-up timer, wherein exiting the PSM includes waking up the applications processor and the modem from the low power state to an active power state; and in response to exiting the PSM, performing a second power collapse of the applications processor into the low power state while the modem operates in the active power state.