Abstract: Techniques for network latency estimation in a computer network are disclosed herein. One example technique includes instructing first and second nodes in the computer network to individually perform traceroute operations along a first round-trip route and a second round-trip route between the first and second nodes. The first round-trip route includes an inbound network path of an existing round-trip route between the first and second nodes and an outbound network path that is a reverse of the inbound network path. The second round-trip route has an outbound network path of the existing round-trip route and an inbound network path that is a reverse of the outbound network path. The example technique further includes upon receiving traceroute information from the additional traceroute operations, determine a latency difference between the inbound and outbound network paths of the existing round-trip route based on the received additional traceroute information.

Abstract: One example includes a clock distribution system. The system includes a resonator feed network comprising a plurality of resonant transmission lines that each propagate a clock signal. The system also includes at least one resonator spine. Each of the at least one resonator spine can be conductively coupled to at least one of the resonant transmission lines, such that each of the at least one resonator spine propagates the clock signal. The system further includes at least one resonator rib conductively coupled to at least one of the at least one resonator spine. Each of the at least one resonator rib can be arranged as a standing wave resonator to propagate the clock signal.

Abstract: Systems, devices, and methods are described herein for aligning a phase of a ring oscillator and removing jitter. An oscillator includes a resistor bank array, an operational amplifier, a first and second transistor, and a realignment circuit. The resistor bank array has a plurality of resistors configured to generate a first signal. The operational amplifier is coupled to a PLL circuit and is configured to compare a voltage of the PLL circuit with a voltage of the resistor bank array. The first transistor is coupled between the operational amplifier and a ring oscillator. The first transistor is configured to generate a second signal to control a frequency of the ring oscillator during a realignment state. The realignment circuit is coupled to the first transistor and the ring oscillator. The realignment circuit is configured to generate a realignment signal to align the ring oscillator with a first clock signal.

Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.

Abstract: According to certain embodiments, a method in a network node for delivering a time synchronization service comprises obtaining a timing accuracy threshold for a time synchronization service provided to a wireless device; determining, based on a first timing accuracy error at the network node and a second timing accuracy error between the network node and the wireless device, that a timing accuracy of the time synchronization service is equal or superior to the timing accuracy threshold, and transmitting the time synchronization service to the wireless device with a timing accuracy equal or superior to the timing accuracy threshold. The method further comprises, in response to determining that the timing accuracy of the time synchronization service is inferior to the timing accuracy threshold, reconfiguring the network node to improve the timing accuracy of the time synchronization service.

Abstract: The disclosure pertains to a method for operating a user equipment in a radio access network. The method includes measuring first synchronisation signaling associated to a first cell of the radio access network, wherein for measuring a set of parametrisations of the first synchronisation signaling is utilised, in which the set of parametrisations is determined based on a signaling parametrisation of second synchronisation signaling associated to a second cell of the radio access network, and further based on a mapping of the signaling parametrization to the first set of parametrisations. The disclosure also pertains to related methods and devices.

Abstract: In one embodiment, a method for managing clock synchronization for a baseboard management controller includes identifying, by a management unit of the information handling system, a real-time clock of the information handling system based on a real-time clock time value; receiving, by the management unit, a request for the real-time clock time value from the baseboard management controller; retrieving, by the management unit, the real-time clock time value from the real-time clock; sending, by the management unit, the real-time clock time value to a logic device of the information handling system; sending, by the logic device, an interrupt signal to the baseboard management controller indicating that the real-time clock time value is stored; retrieving, by the baseboard management controller, the real-time clock time value from the logic device; and updating, by the baseboard management controller, a baseboard management controller time value based on the real-time clock time value.

Abstract: An apparatus, system, and method for detecting compromised firmware in a non-volatile storage device. A control bus of a non-volatile storage device is monitored. The non-volatile storage device includes a processor and electronic components coupled to the control bus. Signal traffic on the control bus is analyzed for events and/or triggers related to storage operations initiated on the control bus by the processor. Storage operations include one or more commands directed to at least one of the electronic components. If the latency for the storage operation satisfies an alert threshold a host is notified of compromised firmware.

Abstract: Certain aspects provide techniques for disambiguating graph data. In one example, a method includes receiving entity data from a data source in a first format; converting the entity data in the first format to a second format, wherein the second format is a standardized input format for a disambiguation pipeline; determining a blocked data set from the entity data in the second format based on a blocking parameter, wherein: the blocked data set comprises data regarding a first plurality of entities, and the first plurality of entities is a subset of a second plurality of entities represented in the entity data from the data source; matching at least two entities in the first plurality of entities in the blocked data set; merging the at least two entities into a single entity; generating a unique ID for the single entity; and importing the single entity into a graph database.

Abstract: An apparatus for generating synchronized clock signals is provided. The apparatus comprises a first circuit comprising a clock divider circuit configured to receive a first clock signal and to generate a second clock signal by frequency dividing the first clock signal. Further, the apparatus comprises a one or more second circuits comprising a respective synchronization circuit configured to receive the first clock signal. The synchronization circuit of one of the one or more second circuits is configured to receive the second clock signal from the first circuit and to resample the second clock signal based on the first clock signal in order to generate a replica of the second clock signal that is in phase with the second clock signal.

Abstract: Creation and use of a digital twin instance (DTI) for a physical instance of the part. The DTI may be created by a model inversion process such that model parameters are iterated until a convergence criterion related to a physical resonance inspection result and a digital resonance inspection result is satisfied. The DTI may then be used in relation to part evaluation including through simulated use of the part. The physical instance of the part may be evaluated by way of the DTI or the DTI may be used to generate maintenance schedules specific to the physical instance of the part.

Abstract: A method of virtualizing a clock is executed by a network controller comprising a processor and computer-readable instructions for creating one or more virtual network elements comprising one or more virtual clocks. The method comprises retrieving, at a first virtual network element of the one or more virtual network elements, a first time of day value and a second time of day value. The method further comprises adjusting the amount of time elapsed based, in part, on a frequency adjustment value and incrementing a clock value based on the amount of time elapsed.

Abstract: The present disclosure relates to systems and methods to maintain clock synchronization of multiple computers, or computer systems, through the exchange of communication messages that include clock and/or timing information.

Abstract: To optimize an operation of a manufacturing facility by presenting a countermeasure for improving quality, even in a manufacturing process where the product quality changes even under constant manufacturing conditions. A countermeasure recommendation device includes a data acquisition unit for collecting a plurality of pieces of facility data, and assigning a label for each process to each piece of the facility data; a countermeasure detection unit for creating countermeasure record data; a countermeasure recommendation unit for calculating the characteristic amount, extracting the characteristic amount, and selecting the countermeasure related to the extracted characteristic amount; and a countermeasure presentation unit for presenting the countermeasure in a visualized state.

Abstract: In some examples, a circuit can include a first buffer circuit that can be configured to receive a first clock signal and a first output voltage. The first buffer circuit can be configured to operate in a first voltage domain based on the first output voltage. The circuit can include a second buffer circuit configured to receive a second clock signal, the second buffer circuit being configured to operate in a second voltage domain based on the second output voltage. The first voltage domain can be different from the second voltage domain. In some examples, one of the first and second buffer circuits can be configured to provide one of the first and second clock signals as a clock output signal at a clock output terminal in response to a clock enable signal.

Abstract: An objective of the present invention is to achieve optimal operating guidance on day-to-day operations in a plant while also achieving, for example, soundness and reduced operating costs for a plant equipment piece without increasing the load on the central operation room, by determining the optimal configuration value for the operating value of the plant equipment piece. To this end, there is provided an equipment state monitoring device 331 for analyzing an operating state of a first plant equipment piece 303 during a prescribed period. The equipment state monitoring device 331 analyzes the operating state of the first plant equipment piece 303, and depending on a result of the analysis, carries out determination of an optimal operating value.

Abstract: Methods, systems, and computer-readable storage media for receiving a query that is coded into a computer-executed application that queries a database system, the query including a first portion that defines a number of groups that data is to be divided into, and a second portion that removes redundant values from a group, if any, processing, within the database system, the query to perform a plurality of computations within the database system, and produce a result set including a plurality of data groups, each data group having a minimum value and associated timestamp, and a maximum value and associated timestamp, and transmitting the result set to the application to provide one or more time series visualizations for display in a user interface.

Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Abstract: A synchronization circuit includes a first synchronizer, a second synchronizer, and selection circuitry. The first synchronizer is configured to synchronize a received signal to a clock signal. The second synchronizer is disposed in parallel with the first synchronizer and configured to synchronize the received signal to the clock signal. The selection circuitry is coupled to the first synchronizer and the second synchronizer. The selection circuitry is configured to provide an output value generated by the first synchronizer at an output terminal of the synchronization circuit based on the output value generated by the first synchronizer being the same as an output value generated by the second synchronizer.

Abstract: The disclosure relates to clock-crossing elements that may be used to transfer data between different clock domains. The embodiments include dual clock first-in first-out (FIFO) buffers that may employ toggle-based protocols to manage the transference of information regarding the state of the FIFO buffer. The toggle-based protocols may include a feedback-based handshake and bit-sliced toggle lines to prevent errors due to differences between the clock signals in the different clock domains.

Abstract: Systems and methods to warehouse, handle, and deliver products are disclosed. The system can comprise a vendor-based virtual network that is associated with a supplier-based physical network. The system can enable vendors with institutional, market, or industry knowledge to manage inventory, logistics, and delivery more efficiently. The system can enable vendors to configure a virtual warehouse and delivery network based on the institutional, market, or industry knowledge. The virtual network can be mapped—behind the scenes—to physical warehouses and delivery networks by warehousing providers (“providers”) based at least in part on the virtual network. The provider can then adjust the physical network based on market knowledge, research, physical sales, warehouse and personnel availability, weather, and other factors. The provider can also offer periodic data to the vendor based on physical sales and delivery information to enable both the virtual and physical networks to converge on an efficient solution.

Abstract: An input/output (I/O) circuit provides a direct current (DC) bias between I/O stages to control duty cycle of the I/O. The I/O circuit can include one or more predriver stages and one or more output stages. The predriver stages can collectively be referred to as a predriver stage, and the output stages can collectively be referred to an output stage. The output stage for a transmitter drives the signal line. The output stage for an input buffer provides a receive signal for processing by the receiver. The I/O circuit includes a control circuit to control the DC bias between the stages to provide trim adjustment of a duty cycle for the output stage.

Abstract: Wireless Electronic Check Deposit Scanning and Cashing Machine (also known and referred to as WEDS) Web-based Online account cash Management computer application System (also known and referred to as OMS virtual/live teller)—collectively invented integrated as “WEDS.OMS” System. Method and Apparatus for Depositing and Cashing Ordinary paper and/or substitute checks and money orders online Wirelessly from home/office computer, laptop, Internet enabled mobile phone, pda (personal digital assistant) and/or any Internet enabled device. WEDS enables verification and transmittal of image, OMS is the navigation tool used to set commands and process requests, integrated with WEDS, working collectively as WEDS.OMS System.

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a clock pin, a clock signal being received from a controller through the clock pin; a first input/output pin; a second input/output pin, data being received from the controller in synchronization with the clock signal through the second input/output pin; a command/address buffer configured to operate at a first operating speed and buffer a command and an address received through the first input/output pin in synchronization with the clock signal; a memory cell array including a plurality of memory cells; and a control logic configured to control operations with respect to the plurality of memory cells, based on the command and the address buffered in the command/address buffer.

Abstract: A method and an apparatus for executing an application are provided. The application execution method of the present disclosure includes connecting a first external device, receiving, from the first external device, connection information for use in connecting to a second external device, connecting to the second external device using the connection information, and transmitting, when a transfer command is received, application execution state information to the second external device. The application execution method of the present disclosure is capable of allowing the user to execute the application conveniently.

Abstract: Electronic devices that detect their position and/or orientation with respect to earth's frame of reference are described. A coupler can removeably maintain the electronic devices in physical proximity of one another. Each electronic device can have a housing and the coupler can be included on the housing and arranged to physically connect the housing of the electronic device to the housing of at least one other electronic device. Alternatively, the coupler can be a packaging that maintains the electronic devices in physical proximity of one another. Each electronic device can be calibrated using the orientation or position information obtained by other electronic devices maintained by the coupler. Further, each electronic device can include a power source that remains inactive until the device is ready for use.

Abstract: Methods and systems for synchronization of multiple processing cores of an electronic control system are disclosed. The electronic control system is configured to monitor and control operation of a multicore architecture employing one or more processing cores to generate a time reference signal and/or to synchronize with the time reference signal. In some examples, the system employs a single master processor to generate the reference synchronization signal (e.g., a master sync signal). In examples, a rising edge of the partition time reference signal is used as the marker of reference time zero (e.g., the start of a new partition frame). If a core is out of sync with the master sync signal, that core adjusts one or more timing characteristics to align the associated signal with the reference signal.

Abstract: A cloud radio access network (C-RAN) includes a baseband controller communicatively coupled to a plurality of radio points (RP) via a fronthaul network. Each of the plurality of RPs are configured to exchange radio frequency (RF) signals with at least one user equipment (UE). At least one of the RPs is configured to determine a timing difference while synchronizing to the baseband controller; and determine a frequency error, between the RP and a neighboring base station, based on a radio environment monitoring (REM) procedure. A phase error is determined, between the baseband controller and the neighboring base station, phase error is determined based on the timing difference for the RP and baseband controller, and the frequency error for the RP and the neighboring base station.

Abstract: Systems, methods, and apparatus for improving bus latency for trigger activation are described. One method includes using configuration information received from a serial bus and stored in a holding register to reconfigure a peripheral device in accordance with timing indicated by at least one edge in clock pulses transmitted on a clock line of the serial bus. A trigger is activated by detection of a first edge in the clock pulses. Bits of the holding register are transferred to a register that controls elements of the peripheral device when the trigger is actuated. The trigger may be activated as indicated by trigger activation information received in a datagram. The trigger may be activated as indicated by a start condition transmitted on the serial bus. The trigger may be enabled or disabled based on signaling state of a data line of the serial bus when the first edge is detected.

Abstract: The described systems, apparatus and methods enable communication between devices that use a single-wire link and devices that use a multi-wire link. One method performed at a master device includes transmitting a sequence start condition over a data wire of a serial bus, the sequence start condition indicating whether clock pulses are to be provided in a clock signal on a clock wire of the serial bus concurrently with a transaction initiated by the sequence start condition, transmitting a first datagram over the serial bus when the sequence start condition indicates that the clock pulses are to be concurrently provided in the clock signal, and transmitting a second datagram over the serial bus when the sequence start condition indicates that no clock pulses are to be concurrently provided in the clock signal. The second datagram may be transmitted in a data signal with embedded timing information.

Abstract: The present disclosure relates to a transmitter and a transmission method and a receiver and a reception method that make it possible to suppress an increase in power consumption. Data in which a clock signal is embedded is transmitted, and a frequency of the clock signal embedded in the data is controlled to reduce the frequency of the clock signal in a predetermined period. Alternatively, data in which a clock signal is embedded and a notification indicating that a frequency of the clock signal is variable are received, and a frequency of the received data is reduced in a predetermined period, on the basis of the received notification. The present disclosure is applicable to, for example, a transmitter, a receiver, a signal processor, a controller, an information transfer system, a transmission method, a reception method, a program, or the like.

Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.

Abstract: A communication unit (700) is described that includes a plurality of cascaded devices that comprise at least one master device (710) and at least one slave device (720, 723) configured in a master-slave arrangement. The at least one master device (710) and at least one slave device (720, 723) each comprise: an analog-to-digital converter, ADC, (741, 742) configured to use a same re-created system clock signal (788, 790) to align respective sampling instants between each ADC (741, 742). The at least one master device (710) comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit (708), configured to output a system clock signal (782, 784); and a modulator circuit (762) coupled to the clock generation circuit and configured to receive and distribute the system clock signal (784).

Abstract: Devices and techniques are disclosed herein for applying an effective sampling delay at a host device to one of an input signal, such as from an embedded MultiMediaCard (eMMC) device, or a clock signal. The host device can apply a configurable delay to one of the input signal or the clock signal with respect to a first edge of the clock signal, sample the input signal using the clock signal according to the configurable delay, and selectively align the sampled input signal to a subsequent, second edge of the clock signal to extend the configurable delay of the host device.

Abstract: A programmable logic circuit (10) for controlling an electrical facility, in particular a nuclear facility, includes an operating unit (14). The operating unit includes a plurality of types of functional blocks (FB1, FBi, FBN), two distinct types of functional blocks being suitable for executing at least one distinct function, at least one processing module suitable for receiving at least one sequence (46) of functional block(s) to be executed, and at least one internal memory (38) configured to store at least said sequence (46). The programmable logic circuit (10) includes a single functional block of each type, a given functional block being suitable for being called several times, and an execution module (22) configured to execute the called functional block(s) in series, according to said sequence (46).

Abstract: A first PHY (121) transmits and receives signals, at a physical layer, to and from a second PHY (142) in a communication device (101) through a communication cable (601). The first PHY (121) is set as a clock master to transmit, to the second PHY (142), a clock signal defining timing for transmitting and receiving signals. A device controller (151), in response to detection of a set event, completes initialization of the first PHY (121) set as the clock master after completion of initialization of the second PHY (142) set as a clock slave.

Abstract: A parallel processing apparatus includes: a memory; and a processor coupled to the memory, the processor is configured to: acquire a first time and a second time; divide a plurality of nodes into a plurality of groups; generate a plurality of schedule candidates each which assigns time zones corresponding to a length of time used to perform a maintenance operation at one or more nodes included in the plurality of groups in a time period from the first time to the second time to the plurality of groups such that no overlap occurs among the plurality of groups; evaluate the plurality of schedule candidates based on one or more process execution schedules of the one or more nodes in the time period; and output one schedule candidate of the plurality of schedule candidates based on a result of the evaluation.

Abstract: Methods, systems, and devices for low power mode for a memory device are described. A memory device may identify a pattern of data configured to be stored in an array of memory cells and determine if the pattern of data satisfies a criterion. The pattern of data may satisfy the criterion if each of the bits of data include a same logic value. If the pattern of data satisfies the criterion, the memory device may disable a driver of an internal bus of the memory device if the data satisfies the criterion, isolate a data line from the internal bus, or couple the data line with a voltage source, or a combination thereof. The memory device may further disable a signal of a clock tree based on identifying that the pattern of data satisfies the criterion.

Abstract: An image capturing device includes an image capturing unit capturing an image at a timing based on a first frame rate and outputs data corresponding to the image after a first period, an image data generation unit generating image data based on the output data and outputting the image data after a second period, a display unit displaying a display image based on the image data after the second period and at a timing based on a second frame rate, and a mode selecting unit selecting a first or second mode. The first mode prioritizes reduction in a display delay time. The second mode prioritizes image quality of the display image over reduction in the display delay time. A total period of the first and second periods is less than or equal to a first vertical synchronization period based on the first frame rate when the first mode is selected.

Abstract: A start-and-stop detecting apparatus for an I3C bus is provided. The start-and-stop detecting apparatus is connected with a serial data line and a serial clock line. The start-and-stop detecting apparatus includes a first start detecting circuit, a second start detecting circuit and a first OR gate. The first start detecting circuit receives a data signal, a clock signal and a reset signal, and generates a first control signal and a first output signal. The second start detecting circuit receives the data signal, the clock signal, the reset signal and the first control signal, and generates a second output signal. A first input terminal of the first OR gate receives the first output signal. A second input terminal of the first OR gate receives the second output signal. An output terminal of the first OR gate generates a start signal.

Abstract: Example implementations relate to balancing a power load among USB ports. For example, an apparatus according to the present disclosure, may include a plurality of USB ports, and an embedded controller coupled to the plurality of USB ports. The embedded controller may determine that a first device is coupled to a USB port of the plurality of USB ports, and determine a power draw of the first device relative to a type of the USB port. The embedded controller may balance a power load among a remainder of the plurality of USB ports based on the power draw of the first device relative to the type of the USB port.

Abstract: Methods, systems, and computer readable media described herein can be operable to facilitate transitioning a device from a first state to a second state. A switch described herein allows for the use of an electronic circuit to perform the toggle and persistence functions while simultaneously giving more flexibility to the industrial design and physical switch implementation. The switch allows this preserving of the state using only a toggle on a voltage and thus allowing for a hardware only solution. The switch described herein allows for the use of smaller and less complicated mechanical switches allowing for more compact industrial designs. The switch uses a programmable voltage reference as a 1 bit non-volatile memory cell that is programmed by means of a logic pulse to the device. This allows a software independent setting of the state of the privacy switch. This state will remain through power cycles.

Abstract: The invention provides a method for providing a synchronization in a computer network for synchronized playback of audio an/or video by a plurality of separate devices. Each separate device generates a virtual clock in response to a timing of the audio codec of a received audio stream. Especially, segmented time is used as reference time. Either the virtual clock is generated directly in response to the tick counter of the audio codec, or by a periodic measurement of the timing of the audio codec extrapolated by a monotonic clock. A sample rate converter may be used to slightly adjust the frequency of the virtual clock.

Abstract: A method for counting a service duration of time measurement on a clock signal including periodic transitions and for determining an actual duration (tmr) of measurement as a function of the service duration, the signal having undergone spectrum spreading according to a periodic variation algorithm causing a frequency modulation of the clock transitions of the signal and creating a difference between actual duration (tmr) and service duration. There are counted during successive time increments at least service times for starting (t_d_s) and stopping (t_a_s) and, on the basis of these times, there are determined actual times for starting and for stopping (t_d, t_a) serving for the calculation of the actual duration of measurement (tmr) as a function of the parameters of the variation algorithm. A method of continuous compensation of the error between actual and service durations is also disclosed.

Abstract: Low noise serial interfaces with gated clock are provided herein. In certain configurations herein, a slave device of a serial interface includes a shift register for serially shifting in an interface data signal based on timing of an interface clock signal, a control circuit (for instance, a finite-state machine) for controlling the slave device, and a register bank for storing data programmed to the slave device via the serial interface. The control circuit cuts off or gates the interface clock signal in response to determining that an interface command received over the serial interface is not intended for the slave device.

Abstract: A storage device includes a data buffer, a device controller, and nonvolatile memories. The data buffer is configured to transact data from an external device. The device controller is configured to receive a command and an address from an external device, to control the data buffers, and to transact data with the data buffers. The nonvolatile memories are configured to perform write, read, and erase operations under control of the device controller. When a first link training between an external device and the data buffers is performed by the external device, the device controller performs a second link training between the device controller and a data buffer internally without control of the external device.

Abstract: Embodiments include apparatuses, systems, and methods associated with modulating a clock signal to encode information. A system may include a plurality of dies including a first die. The first die may include a real time clock (RTC) circuit to receive clock information associated with a shared clock signal that is shared among the plurality of dies, and modulate a RTC signal to encode the clock information. The first die may further include an output terminal coupled to the RTC circuit to pass the modulated RTC signal to one or more other dies of the plurality of dies. A second die of the plurality of dies may include a decoder to receive the modulated RTC signal and extract the clock information. The second die may adjust and/or condition the shared clock signal based on the received clock information. Other embodiments may be described and claimed.

Abstract: Aspects of the invention include a process for receiving data and a first clock signal of a first chip and a second clock signal of a second chip, the data being received on a data path and the first clock signal being received on a clock signal path, and determining that the first clock signal is arriving before the second clock signal by a difference quantity. Also, the process includes adding delay to the data path and the clock signal path according to the difference quantity.

Abstract: A circuit may perform a skew correction process that positions clock pulses of an output clock signal in respective target sampling positions. The circuit may receive an input clock signal and an input data signal and select one of a plurality of predetermined skew cases for the input clock signal and the input data signal. In addition, the circuit may performing timing relationship measurements for transition permutations of the clock signal and the data signal. The circuit may determine which of the input clock signal and the input data signal to delay and an amount of the delay based on the selected skew case and the timing relationship measurements. An output of the circuit may delay the input clock signal or the input data signal according to the determinations, which centers the sampling transitions of the clock signal in target sampling positions.

Abstract: A glitch removal circuit removes glitch noise contained in a Power-good signal and a Power-on Reset signal, and includes: a first glitch removal unit that operates according to a first clock signal, and removes glitch noise from a Power-good signal; and a second glitch removal unit that operates according to a second clock signal, and removes glitch noise from a Power-on Reset signal, in which the first glitch removal unit is configured so as to be initialized according to an output signal of the second glitch removal unit, and the second glitch removal unit is configured so as to be initialized according to an output signal of the first glitch removal unit.