Abstract: A device, system, and method determines a forwarding delay through a networking device. The method is performed at the networking device including a transceiver and an always running timer (ART). The method includes generating a first timestamp using a first clock of the transceiver when a packet to be forwarded has been received. The method includes capturing a first ART time corresponding to the first timestamp. The method includes generating a second timestamp using a second clock of the transceiver when the packet to be forwarded has been transmitted. The method includes capturing a second ART time corresponding to the second timestamp. The method includes determining a forwarding delay based on the first and second timestamps and the first and second ART times.

Abstract: A memory device performs DLL (delay locked loop) calibration in accordance with a DLL calibration mode configured for the memory device. A host controller can configure the calibration mode based on operating conditions for the memory device. The memory device includes an input/output (I/O) interface circuit and a delay locked loop (DLL) circuit coupled to control I/O timing of the I/O interface. A control circuit of the memory device selectively enables and disables DLL calibration in accordance with the DLL calibration mode. When selectively enabled, the DLL calibration is to operate at a time interval identified by the DLL calibration mode, and when selectively disabled, the DLL calibration is to cease or refrain from DLL calibration operations.

Abstract: Computer implemented techniques for the partitioned simulation of parallel architectures are disclosed. A high-level design for simulation is obtained. A graph representation for the high-level design is determined. The graph for the high-level design is partitioned into sub-graphs. A subset of the sub-graphs is selected for simulation based on input-change bits of the sub-graphs. The subset of the sub-graphs is subsequently evaluated on parallel architectures in order to produce a simulation result for the high-level design.

Abstract: Various methods and apparatus for graphics processing are disclosed. In one aspect, a method of graphics processing using a computing system is provided. The method includes booting the computing system. After booting the computing system operating video memory of the computing system at a non-overclocked frequency, and prior to rebooting having the computing system sequentially increment the frequency of video memory by a selected change in frequency through a series of overclocked frequencies, after each frequency incrementing writing data to the video memory and testing the stability of the video memory data writing, and if the stability testing fails then decrementing the frequency of the video memory to a previous overclocked frequency at which the stability testing did not fail.

Abstract: Methods and systems provide control of media synchronization using time stamp pairs. In an embodiment, a first device may request a time stamp from a second device. The first device may determine any de-synchronization between the first and second devices based on the requested time stamp and characteristics of the request. The first device may define a rate scalar based on the determined de-synchronization. A sample rate conversion may be performed for the first device based on the rate scalar such that the outputs of the first device and the second device are synchronized.

Abstract: A method relating to synchronize MIDI file with video includes acquiring a video and a MIDI file, and identifying timing of a video frame. The method also includes converting timing into tick information and editing a tick of the MIDI file. The method further includes detecting the MIDI file corresponding to the video frame, and playing a musical instrument based on the MIDI file corresponding to the video.

Abstract: An electronic device is provided. The electronic device includes a hardware timer, a memory, a communication circuit, and a processor. The processor is configured to measure a first time point of the hardware timer in response to a playback event received via the communication circuit from a master paired with the electronic device, calculate a second time point by adding a predefined first time interval to the first time point, and execute an instruction to play back a sound source at the second time point. A first resolution of the hardware timer is set to be higher than a second resolution of an operating system (OS).

Abstract: A system includes a central processing unit (CPU) and components, a particular one of including logic to participate in a portion of a boot sequence of the system, where the portion of the boot sequence begins prior to activation of the CPU. The particular component is to send one or more signals to interact with another one of the components in the system during the portion of the boot sequence. The particular component includes a timer block to generate a set of timestamps during the portion of the boot sequence, where the set of timestamps indicates an amount of execution time of the particular component. The particular component sends the set of timestamps to the other component in a particular one of the one or more signals, where the set of timestamps are used to determine execution time of system components to complete the boot sequence.

Abstract: Disclosed herein are computer systems, devices, and methods for improving the technology related to asset condition monitoring. In accordance with the present disclosure, an asset data platform may be configured to receive data related to asset operation, ingest, process, and analyze the received data, and then provide a set of advanced tools that enable a user to monitor asset operation and take action based on that asset operation. The set of advanced tools may include (1) an interactive visualization tool, (2) a task creation tool, (3) a rule creation tool, and/or (4) a metadata tool.

Abstract: A control system includes a data access circuit and a control circuit. The system coordinates an asynchronous FIFO process between a write circuit operating according to a first clock and a read circuit operating according to a second clock. The data access circuit controls the write circuit to write data into a memory buffer and controls the read circuit to read the data from the memory buffer. The control circuit generates a write index according to the first clock and a read index according to the second clock. The control circuit calculates multiple water levels according to the write index and the read index and obtains a median water level. The control circuit controls the access circuit to execute the asynchronous FIFO process at a time point corresponding to the median water level, so that a data exchange is performed via the memory buffer.

Abstract: A synchronization protocol is used to transfer information from a remote computing system to a client device. At the remote computing system, synchronization configuration information is retrieved. The synchronization configuration includes a synchronization rule specifying a data object schema to which the synchronization rule will apply, truncation criteria, and a truncation threshold. The truncation threshold specifies a maximum amount of shared data object instances of the data object schema that may be sent to the client device during a synchronization task. The remote computing system analyzes metadata of a plurality of shared data object instances of the data object schema. Relevant shared data object instances of the plurality of shared data object instances meeting the truncation criteria are determined by the remote computing system. The relevant data object instances are sent from the remote computing system to the client device until the truncation threshold is met.

Abstract: An information processing apparatus includes a memory and a processor coupled to the memory and configured to, receive a plurality of pieces of collation information corresponding to respective information items of configuration information representing information apparatus configurations, perform collation processing for collating information acquired from an information system including a plurality of information apparatuses with the plurality of pieces of collation information, and specify pieces of configuration information representing respective configurations of the plurality of information apparatuses based on specific collation information with which the largest number of successes of the collation processing for each type of information item and each model of information apparatus is detected.

Abstract: With a method of connecting SRAMs by daisy chain connection, the power state of all the SRAMs is determined uniquely. Because of this, even in the case of an SRAM of a function module in which SRAM access does not occur, the SRAM returns to the normal mode. The control apparatus includes a plurality of function modules including a memory capable of making a transition between a first power state and a second power state that is more power-saving than the first power state in accordance with a control signal. Then, control is performed so as to output a first signal that gives instructions to make a transition of the power state based on the control signal to a memory of a function module of the plurality of function modules in which processing using a function that the function module has is performed.

Abstract: A node is deployed along a path between a master device and a slave device. In some cases, the path includes additional nodes. The node includes a plurality of queues configured to be associated with a corresponding plurality of flows. A first queue of the plurality of queues is configured to be associated with a first flow that conveys timing messages for synchronizing the master device and the slave device. A scheduler is configured to schedule messages from the first queue during an extended time window that encompasses expected arrival times of a first set of timing messages in the first flow. The node reverts to normal behavior in response to completing processing of the first set of timing messages. During normal operation, the node schedules messages from the first queue during a default time window that is shorter than the extended time window.

Abstract: A frequency divider includes a circuit that receives an input clock signal having a period T on an input port thereof and generates an output clock signal on an output port thereof having a period MT in response to a control signal specifying M is disclosed. Here, M is a positive integer and all transitions between logical one and logical zero in the output clock signal occur at integer multiples of T. In one embodiment, the circuit includes a module string having characterized by N identical modules connected in series to form a string of modules. Each module is configured such that when the clock signal having period T is input to the first module, the output clock signal having a period of MT is output from the last module, where M can have any value between one and a maximum number that depends on N.

Abstract: A memory controller instantiated on a semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The memory controller further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.

Abstract: Systems and methods for providing a connection of a client to an unmanaged service in a client-server remote access system. An unmanaged service may register at a remote access server and open a communication connection there between remote access server may be configured for providing remote access to the unmanaged service by a client. The remote access server receives keep-alive messages from the unmanaged service over the communication connection, which may serve to indicate that the unmanaged service is operational. The remote access server may a request for a client connection to the unmanaged service, after which, a terminate keep-alive message is communicated to the unmanaged service to terminate the sending of keep-alive messages from the unmanaged service in response to the request for the client connection to the unmanaged service.

Abstract: A method of virtualizing a clock is executed by a network controller comprising a processor and computer-readable instructions for creating one or more virtual network elements comprising one or more virtual clocks. The method comprises retrieving, at a first virtual network element of the one or more virtual network elements, a first time of day value and a second time of day value. The method further comprises adjusting the amount of time elapsed based, in part, on a frequency adjustment value and incrementing a clock value based on the amount of time elapsed.

Abstract: Disclosed are methods and apparatus for calculating sensor timing corrections at a sensor device. The methods and apparatus determine a sampling period as a number of cycles of an internal clock counted while a configured number of samples is captured in a slave device, determine a time interval between samples using an offset from a time of an observed occurrence of a hardware event on a communication link, the offset being received in a command from a master device, and adjust the time interval between samples by iterative digital approximation to correct for differences between timing of the slave device and the master device while concurrently calculating a watermark time corresponding to a sample start time configured by the master device for one or more slave devices.

Abstract: A computer-implemented method designs a distributed heterogeneous computing and control system, including both an application and a hardware context and configuring the application in the hardware context. The method is implemented by design software instructions executing in a computer node, associated with an interactive display, to establish an interactive environment utilizing computer processes. The computer processes provide access in the interactive environment to a set of functional modules and a set of primitive modules. The computer processes receive the interactive environment a selection of desired ones of the functional modules and the primitive modules and order them in a manner to characterize the distributed computing and control system as a schematic of a set of devices. The computer processes parse the schematic to produce a set of sub-schematics that each correspond to a distinct device in a set of devices in the distributed computing and control system.

Abstract: Module 1 for a technical facility 90 comprising a technical hardware 10 for the execution of a technical sub-process, a control 20 for a local control of the technical hardware 10, wherein the control 20 is adapted to control the technical hardware 10 autarkical, and an external interface 22 of the control 20, wherein the external interface 22 comprises an administration shell 23, wherein the administration shell 23 publishes at least one service relating to an output product 140 of the module 1 via a network 62, and wherein the external interface 22 is adapted to request at least one service relating to an input product 130 of the module 1 via the network 62. Furthermore, a corresponding system for the execution of a process by means of a technical facility 90 as well as a corresponding method for the execution of a technical process by means of a technical facility 90 is claimed.

Abstract: A waveform simulation system with a waveform database architecture satisfies different requirements of different waveform simulation tools. The waveform simulation system includes a waveform database configured to store one or more mappings that map one or more design objects to one or more memory addresses. The waveform simulation system also includes a packet processing module configured to receive simulation data from a simulation tool. The packet processing module is configured to translate the simulation data into translated simulation data that is independent of implementation details of the one or more design objects, based at least in part on the one or more mappings. In some cases, the translated simulation data may include event data stored in the waveform database.

Abstract: Embodiments of the disclosure provided herein generally include a system and a method of configuring and/or controlling the transfer of information between two or more electronic devices due to the interaction of an electronic device and a host identifier signal generating system. Embodiments of the disclosure may include a system and a method of distributing useful information received by or contained within a memory of the electronic device based on the receipt of a host identifier signal. The electronic device may then perform one or more desirable functions or processes based the portable electronic device's interaction with the host identifier signal generating system.

Abstract: Embodiments included herein may be used for characterizing and analyzing an electronic system design including a parallel interface. Embodiments may include identifying an electronic design including a design of a parallel interface. Embodiments may also include determining a single circuit representation including the design of the parallel interface from the electronic design. Embodiments may further include analyzing the single circuit representation at a channel analysis module stored at least partially in memory and functioning in tandem with a computing system to determine waveform responses of the parallel interface and a remainder of the single circuit representation by using channel analysis techniques. The channel analysis techniques may be based upon a data channel simulation and a strobe channel simulation.

Abstract: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

Abstract: A method of operating a clock frequency detected control-i/o buffer enable circuit in a semiconductor device uses control I/O buffer enable circuitry and/or features of saving power in standby mode. The method may provide low standby power consumption, such as providing low standby power consumption in high-speed synchronous SRAM and RLDRAM devices.

Abstract: One embodiment includes a clock distribution resonator system. The system includes a clock source configured to generate a clock signal having a predefined wavelength, and a main transmission line coupled to the clock source to propagate the clock signal and comprising a first predetermined length defined as a function of the wavelength of the clock signal. The system also includes a plurality of transmission line branches each coupled to the main transmission line to propagate the clock signal. Each of the plurality of transmission line branches includes a second predetermined length different from the first predetermined length. The system further includes a plurality of clock distribution networks coupled to the respective plurality of transmission line branches and being configured to provide the clock signal to each of a plurality of circuits to provide clock synchronization for the associated plurality of circuits.

Abstract: A time synchronization slave apparatus and a method of determining a time synchronization period are disclosed. In the apparatus, a time synchronization processing unit performs a time synchronization operation and determines an offset and a rate used to correct local time error based on a calculated time error, a timer corrects the local time based on the determined offset and rate, a time error estimation unit estimates a time error in the local time during a present time synchronization period, and generates excess error information regarding an excess point at which the estimated time error exceeds a threshold allowable time error range, a time synchronization period determination unit determines a subsequent time synchronization period based on the excess error information, and a synchronization period information transmission unit transmits synchronization period information regarding the subsequent time synchronization period to a time synchronization master apparatus.

Abstract: Synchronization techniques with state transformation are described. The synchronization techniques may include storing a data object and metadata associated with the data object at a computing device. The data object can be stored in a first representative state at the computing device. The techniques may further involve receiving user input to synchronize the data object into a second representative state at a remote computing device, automatically transforming the data object from the first representative state into the second representative state, and synchronizing the data object to a remote data object stored at the remote computing device. The remote data object can be stored in the second representative state at the remote computing device.

Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.

Abstract: An image capturing device includes an image capturing unit capturing an image at a timing based on a first frame rate and outputs data corresponding to the image after a first period, an image data generation unit generating image data based on the output data and outputting the image data after a second period, a display unit displaying a display image based on the image data after the second period and at a timing based on a second frame rate, and a mode selecting unit selecting a first or second mode. The first mode prioritizes reduction in a display delay time. The second mode prioritizes image quality of the display image over reduction in the display delay time. A total period of the first and second periods is less than or equal to a first vertical synchronization period based on the first frame rate when the first mode is selected.

Abstract: Embodiments relate to systems, methods, and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a plurality of receiver arrangements, each receiver arrangement having a sampling circuit and a multi-stage differential amplifier connected to the sampling circuit. Each receiver arrangement is configurable via switches between an amplifying mode and an autozero mode. Control circuitry may select output data from receiver arrangements that are not in autozero mode using multiplexer circuitry. In various embodiments, settings for individual receiver arrangements may be set based on decision feedback equalization (DFE).

Abstract: An approach is provided in which a system selects a first processor as a master Time of Day (TOD) processor in a first TOD topology in response to determining that the first processor is directed connected to an oscillator. The system then assigns a second processor as an alternate master TOD processor to a second TOD topology based upon determining that the second processor is on a different node than the first processor. The system configures to the first TOD topology and, when the system detects a TOD failure, the system re-configures to the second TOD topology.

Abstract: A transmitter circuit including a pre-driver circuit configured to receive a logic signal from a logic circuit and to generate a first signal driven by a first voltage, the pre-driver circuit including a transistor having a threshold voltage equal to or lower than a threshold voltage of a transistor included in the logic circuit, and a main-driver circuit configured to receive the first signal and generate a second signal driven by a second voltage, the main-driver circuit configured to output the second signal to an input/output pad, the main-driver circuit including a transistor having a threshold voltage which is equal to or lower than the threshold voltage of the transistor included in the logic circuit may be provided.

Abstract: Methods, systems, and computer program products are included for migrating a virtual machine. An example method of migrating a virtual machine includes transmitting, from a hypervisor, a migration indicator to a guest. The hypervisor receives a free memory page indicator from the guest that identifies one or one or more free memory pages corresponding to a virtual machine. The hypervisor then places the virtual machine in a suspended state. While the virtual machine is in the suspended state, the hypervisor modifies a dirty status and a migration status corresponding to one or more dirty memory pages. After resuming operation of the virtual machine from the suspended state, the hypervisor modifies a migration status corresponding to the one or more free memory pages to exclude the one or more free memory pages from a migration. The hypervisor migrates the one or more dirty memory pages.

Abstract: One embodiment includes a clock distribution system. The system includes a standing-wave resonator configured to receive and to resonate a sinusoidal clock signal. The standing-wave resonator includes at least one anti-node portion associated with a peak current amplitude of the sinusoidal clock signal. The system also includes at least one clock line interconnecting each of the at least one anti-node portion and an associated circuit. The at least one clock line can be configured to propagate the sinusoidal clock signal for timing functions associated with the associated circuit.

Abstract: An apparatus includes at least one transceiver configured to transmit or receive at least one data signal over a shared physical medium. The physical medium includes a bus configured to be coupled to multiple devices including the apparatus and provides a multi-drop capability. The at least one transceiver is configured to transmit or receive the at least one data signal at a rate of more than 10 Mbps. In some embodiments, the apparatus includes a MAC driver configured to route network layer data over the physical medium. In other embodiments, the apparatus includes a MAC driver configured to control transmissions and receptions of network layer data over the physical medium by the at least one transceiver and a logic device configured to control physical layer signaling, interface with the MAC driver, enable the transmissions and receptions of the network layer data on the physical medium, and implement collision detection and avoidance.

Abstract: An image processing apparatus has a nonvolatile memory including a first region and a second region, a control circuit, and a data input unit. First software is used for updating. Second software is not used for updating. When a starting condition for updating is satisfied, the control circuit overwrites the second region with the first software and makes the second region a new first region. Then, the control circuit overwrites the old first region with the second software and makes the old first region a new second region.

Abstract: Techniques for previewing an operator display of a process section in a process plant include presenting a process section on a user interface device, where the process section includes a user control for presenting and/or displaying another process section on the process plant display. In response to receiving user input indicative of a request to display a preview of the other process section via the user control, the user interface device presents the other process section while simultaneously presenting the process section in a preview mode. The process sections in the preview mode may be presented side-by-side, above and below each other, in separate display windows, etc.

Abstract: Apparatus and methods are disclosed for selecting one or more mobile device applications using context data describing the current environment of a mobile device and application metadata describing environment conditions where applications are more likely to be relevant, in order to improve the experience of discovering, downloading, and installing mobile device applications. According to one embodiment, a method comprises associating metadata with mobile device applications automatically receiving context data representing a current geographical location from a mobile phone, searching the metadata to determine which applications are likely of interest based on the current geographical location, and transmitting notification data to the mobile phone indicating the determined applications.

Abstract: There is provided a technique that makes it possible to ascertain a strobe point for data while a memory is in operation with actual data. A memory controller 1 includes a data skew adjustment part 2 that adjusts a data skew of a read data signal, a strobe adjustment part 3 that adjusts a strobe point, a data change point detection part 4 that detects a data change point, a strobe point detection part 5 that detects a strobe point, a dynamic timing calculation part 6 that calculates dynamic timing information for each read data signal, a dynamic timing information storage part 7 that stores the dynamic timing information, and a dynamic timing information output part 8 that outputs the dynamic timing information.

Abstract: An apparatus includes a clock tree circuit, a first phase interpolator circuit and a second phase interpolator circuit. The clock tree circuit may be configured to generate a first clock delayed from a system clock by a constant time. The first phase interpolator circuit may be in a calibration loop and configured to generate a second clock with a programmable phase delay relative to the first clock. The programmable phase delay may be controlled by a control value. The calibration loop may be configured to determine the control value that results in a given delay between the system clock and the second clock. The second phase interpolator circuit may be in a normal signal path and configured to generate a third clock with the given delay relative to the first clock using the control value such that the third clock is offset from the system clock by the given delay.

Abstract: Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.

Abstract: A semiconductor integrated circuit includes a register, a detection circuit, and a generation circuit. The register stores a detection start timing of a reference delay amount based on a first clock during a first period. The first period is a period in which the first clock starts to be input. The detection circuit has a plurality of delay stages. The detection circuit detects the reference delay amount at the start timing during the first period and obtains the number of delay stages corresponding to the reference delay amount. The generation circuit adjusts a duty ratio of the first clock based on the number of delay stages obtained by the detection circuit and generates a second clock during a second period. The second period is a period continuing from the first period.

Abstract: Provided are systems and methods for garbage collection of objects in storage. An example method may include providing a monotonically increasing logical clock. Each object is associated with a first number and a second number. The second number is a minimum of the first numbers of objects in a subtree to which the object refers. When the logical clock increases, objects with the first number less than the logical clock from the storage are deleted. When a new object is added to the storage, the first number of the new object is set to a new first number. The new first number is equal to or greater than the logical clock. The first number of each object in a subtree to which the new object is referring is updated. The updated first number is a function of a previous first number and a previous logical clock.

Abstract: A storage-media-agnostic chassis apparatus may include a media-agnostic storage bay that (1) is adapted to house media storage devices of a plurality of different media storage device types with different physical dimensions, (2) is reconfigurable via removing at least one media storage device of a media storage device type from the media-agnostic storage bay and inserting at least one media storage device of an additional media storage device type, (3) is dimensioned to simultaneously store a plurality of media storage devices, and (4) comprises a plurality of connectors adapted to simultaneously connect to the media storage devices. The apparatus may also include a storage controller card, a compute module that is separate from but removably attached to the media-agnostic storage bay, and a backplane that facilitates communication between the media storage device and the compute module. Various other methods, systems, and apparatuses are also disclosed.

Abstract: A method at a first device for synchronising a first clock of the first device to a second clock of a second device, includes receiving a first message comprising an identifier from a third device; generating a first timestamp in dependence on the time at which the first message is received at the first device according to the first clock; receiving a second message from the second device comprising the identifier and a second timestamp, the second timestamp having been generated in dependence on the time at which the second device received the first message from the third device according to the second clock; and adjusting the first clock in dependence on a time difference between a time indicated by the first timestamp and a time indicated by the second timestamp.

Abstract: Disclosed herein are systems, methods, and computer-readable media directed to scheduling threads in a multi-processing environment that can resolve a priority inversion. Each thread has a scheduling state and a context. A scheduling state can include attributes such as a processing priority, classification (background, fixed priority, real-time), a quantum, scheduler decay, and a list of threads that may be waiting on the thread to make progress. A thread context can include registers, stack, other variables, and one or more mutex flags. A first thread can hold a resource with a mutex, the first thread having a low priority. A second thread having a scheduling state with a high priority can be waiting on the resource and may be blocked behind the mutex held by the first process. A scheduler can execute the context of the lower priority thread using the scheduler state of the second, higher priority thread. More than one thread can be waiting on the resource held by the first thread.

Abstract: A method of synchronizing clocks of network device, preferably in a non-deterministic network with a channel access method, wherein it is not possible to determine a time needed for a network device to access the non-deterministic network, wherein each network device comprises at least one clock, wherein a first clock of a first network device and a second clock of a second network device differ by an offset and the offset changes over time due to a drift and wherein the second clock of a second network device (200) shall be synchronized with the first clock of the first network device.

Abstract: A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.