Synchronization Of Clock Or Timing Signals, Data, Or Pulses Patents (Class 713/400)
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Publication number: 20140223219Abstract: A clock frequency controller for a processor and a method of operation thereof. The clock frequency controller may be embodied in a processor, including: (1) a processing core operable at a clock frequency to undertake a processing of a graphics application, and (2) a clock frequency controller coupled to the processing core and operable to adjust the clock frequency based on a current frame rate of the processing and a target frame rate for the processing.Type: ApplicationFiled: February 1, 2013Publication date: August 7, 2014Applicant: NVIDIA CORPORATIONInventors: Ilan Aelion, Aleksandr Frid, Satya Popuri
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Patent number: 8799565Abstract: A memory controlling device that includes a request generating section for generating a memory request, a row selecting information retaining section that retains data relative to row address information, a column selecting information retaining section that retains data relative to column address information, a memory bank information for managing section operation states of the memory device, a command generating section for generating operation commands, and a command aligning section that synchronizes the operation commands with the clock.Type: GrantFiled: January 14, 2010Date of Patent: August 5, 2014Assignee: Sony CorporationInventor: Takahiro Ikarashi
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Patent number: 8799545Abstract: A method for restoring stability to an unstable bus includes cycling a clock of the bus a number of times, transmitting a stop bit, cycling a clock line of the bus at least one time and transmitting a stop bit immediately after an acknowledgment bit has been received by a bus master.Type: GrantFiled: February 26, 2010Date of Patent: August 5, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: Mike Erickson, David Maciorowski
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Patent number: 8798222Abstract: Methods and apparatus are provided for digital linearization of an analog phase interpolator. Up to 2N desired phase values are mapped to a corresponding M bit value, where M is greater than N. A corresponding M bit value is applied to the phase interpolator to obtain a desired one of the 2N desired phase values. A linearized phase interpolator is also provided that accounts for process, voltage, temperature or aging (PVTA) variations.Type: GrantFiled: March 31, 2005Date of Patent: August 5, 2014Assignee: Agere Systems LLCInventors: Mohammad S. Mobin, Gregory W. Sheets, Lane A. Smith, Craig B. Ziemer
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Patent number: 8799698Abstract: A clock signal for electronic circuitry is generated by generating, based on which one of a plurality of application use cases is presently active, a first signal that indicates a first selected one of a plurality of clock signal operating points. Based on the electronic circuitry's present speed requirement, a second signal is generated that indicates a second selected one of the clock signal operating points. For any given one of the application use cases, the speed requirement need not remain constant for the duration of the application use case. Based on whichever one of the first and second signals is associated with a higher clock frequency operating point, a third signal is generated that indicates which clock signal operating point (and possibly what voltage level) should be active. The third signal controls generation of a clock (and possibly also voltage level).Type: GrantFiled: May 31, 2011Date of Patent: August 5, 2014Assignee: Ericsson Modems SAInventors: Jakob Singvall, Harald Bauer
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Patent number: 8793525Abstract: Within a system of integrated circuit devices, first and second signals are transmitted intermittently from a first integrated circuit device to a second integrated circuit device. The second integrated circuit device generates a timing signal based on transitions of the second signal and generates samples of the first signal in response to transitions of the timing signal. The second integrated circuit device further generates timing error information based on the samples of the first signal, the timing error information to enable adjustment of the relative phases of the timing signal and the first signal.Type: GrantFiled: July 3, 2008Date of Patent: July 29, 2014Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Frederick A. Ware
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Patent number: 8793524Abstract: A method of determining the downstream propagation time of signals from a USB Host Controller across one or more USB cables and one or more USB Hubs to a SuperSpeed USB device, including locking a clock of the SuperSpeed USB device to information that includes a first timestamp, transmitting a plurality of signals to the USB Host Controller, each of the signals containing a second timestamp indicative of a local time of the SuperSpeed USB device when the respective signal was generated by the SuperSpeed device; the USB Host Controller creating a third timestamp indicative of a time of reception from the SuperSpeed USB device; determining a time period from one or more respective time differences between corresponding second and third timestamps, the time period being indicative of a sum of a downstream propagation time and an upstream propagation time; and determining the downstream propagation time from the time period.Type: GrantFiled: May 20, 2010Date of Patent: July 29, 2014Assignee: Chronologic Pty. Ltd.Inventor: Peter Graham Foster
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Publication number: 20140208146Abstract: One embodiment provides a method for time protocol latency correction based on forward error correction (FEC) status. The method includes determining, by a network node element, if a forward error correction (FEC) decoding mode is enabled or disabled for a packet received from a link partner in communication with the network node element. The method also includes determining, by the network node element, a first time correction factor if an FEC decoding mode is enabled, the first time correction factor includes a time delay associated with the enabled FEC decoding mode and the first time correction factor is applied to a time stamp associated with the packet. The method also includes determining, by the network node element, a second time correction factor if an FEC decoding mode is disabled, the second time correction factor is applied to the time stamp associated with the packet.Type: ApplicationFiled: January 18, 2013Publication date: July 24, 2014Inventor: KENT LUSTED
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Patent number: 8781052Abstract: A system and method are described to provide a next generation cable gateway/modem based on the DOCSIS standard with a scheme to synchronously combine channels in the physical layer to increase overall bit rates for coaxial cable data transmission. The systems and methods synchronize the counters associated with multiple channels, including continuity counters, at the transmitter to zero and then allow the counters on individual channels to increment individually. At the receiver, individual channel delays of individual channels will be thus recognizable based on the information provided by the counters associated with each channel. A buffer at the receiver is informed and used to individually delay one or more of the multiple channels to marry up continuity counter values. In this manner, the buffer acts to essentially equalize delays in individual channels with the continuity counter representing the mechanism for specifying the individual delays for the separate channels.Type: GrantFiled: June 21, 2012Date of Patent: July 15, 2014Assignee: Intel CorporationInventors: Bernard Arambepola, Shaul Shulman, Naor Goldman, Amos Klimker, Noam Tal
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Patent number: 8782459Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network, a core clocks generator, and a synchronous strobe driver. The resistor network is configured to provide a ratio signal that indicates an amount to advance a synchronous data strobe associated with a data group. The core clocks generator is coupled to the ratio signal, and is configured to advance a data strobe clock by the amount. The synchronous strobe driver is configured to receive the data strobe clock, and is configured to employ the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the amount.Type: GrantFiled: June 21, 2011Date of Patent: July 15, 2014Assignee: VIA Technologies, Inc.Inventors: Darius D. Gaskins, James R. Lundberg
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Method and system for precise temperature and timebase PPM error estimation using multiple timebases
Patent number: 8775851Abstract: Methods and systems for precise temperature and timebase ppm error estimation using multiple timebases may comprise measuring a coarse reading of a temperature corresponding to the plurality of timebases. The frequencies of the timebases may be compared to generate a fine reading of the temperature based, at least in part, on the coarse reading and the comparison of the frequencies with respect to models of temperature dependencies for each of the timebases. The timebases may be calibrated utilizing the generated fine reading. The plurality of timebases may comprise different order temperature dependencies. The models of temperature dependencies of each of the plurality of timebases may be updated based, at least in part, on the fine reading of the temperature corresponding to the plurality of timebases. A global navigation satellite system (GNSS) clock signal may be utilized periodically to improve the accuracy of the calibration of the plurality of timebases.Type: GrantFiled: November 15, 2011Date of Patent: July 8, 2014Assignee: Maxlinear, Inc.Inventors: Curtis Ling, Xing Tan, Hyungjin Kim -
Patent number: 8775852Abstract: A method for sensing input signal changes at an input of an input/output module operated in an automation system in which a signal is sampled by an input/output module. A change event and a timestamp associated with the change event are generated when a change in the sampled signal occurs and a value pair comprising the change event and the timestamp is stored in a higher-ranking automation component to the input/output module. The input/output module and the higher-ranking automation component are operated clock-synchronously with respect to one another by a clock pulse, and the timestamp is calculated centrally on the higher-ranking automation component based on the clock-synchronous operation.Type: GrantFiled: November 23, 2011Date of Patent: July 8, 2014Assignee: Siemens AktiengesellschaftInventors: Holger Röhle, Matthias Simon
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Patent number: 8775856Abstract: Various techniques are provided to generate a plurality of reference clock signals using a single reference clock signal generator. In one example, a clock signal generation system includes a reference clock signal generator adapted to provide a reference clock signal. The system also includes a plurality of dividers adapted to divide the reference clock signal using different ratios to provide a plurality of communication port clock signals. The system also includes a plurality of different communication ports adapted to receive the communication port clock signals and adapted to operate in accordance with different communication protocols using the communication port clock signals.Type: GrantFiled: March 10, 2010Date of Patent: July 8, 2014Assignee: SMSC Holdings S.A.R.L.Inventors: Hongming An, Jun Ye, Christopher Thomas, CongQing Xiong
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Patent number: 8775850Abstract: Some embodiments enable a first electronic device (e.g., a notebook computer) to obtain state information directly from another electronic device (e.g., a smartphone) so that the first electronic device may replicate a state of content of the other computing device. This is useful when a user of an electronic device desires to switch between one device and another device such that the user may continue an activity (e.g., playing a video game) on another device without having to restart the activity. This is also useful when a user of a first electronic device attempts to replicate the state of the activity on a second device from another user such that both users may participate in the same activity. In some embodiments, a user of a device may obtain content from a server and state information from another device to replicate the state of content on the other device.Type: GrantFiled: June 28, 2011Date of Patent: July 8, 2014Assignee: Amazon Technologies, Inc.Inventor: Steven Ka Cheung Moy
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Patent number: 8775853Abstract: A method for synchronizing two connection nodes by a reception node of the connection nodes with a clock data recovery circuit that generates a synchronization clock from input data. The method includes performing a synchronization process to establish synchronization between the connection nodes based on the synchronization clock, performing a connection failure process when the synchronization is not established when a first time elapses after receiving the input data, correcting the clock data recovery circuit when the synchronization is not established when a second time elapses after receiving the input data, wherein the second time is shorter than the first time, and performing a resynchronization process to establish synchronization between the connection nodes based on a synchronization clock, which is generated by the clock data recovery circuit that has been corrected, before the first time elapses and after the second time elapses.Type: GrantFiled: April 16, 2013Date of Patent: July 8, 2014Assignee: Spansion LLCInventor: Masato Tomita
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Patent number: 8775849Abstract: Systems and methods for synchronizing a clock at a customer premises equipment (CPE) location with a master clock at a central office (CO) location are described. One embodiment is a method that comprises receiving, by a time-of-day transmission convergence (ToD-TC) module in the CPE, ToD information relating to the master clock. Based on the received information, time stamps are applied to reference data samples. The method further comprises transporting the ToD information by transporting the reference data samples with applied time stamps and utilizing time stamps of the reference data samples to synchronize the CPE clock with the master clock.Type: GrantFiled: May 8, 2011Date of Patent: July 8, 2014Assignee: Ikanos Communications, Inc.Inventors: Massimo Sorbara, Sigurd Schelstraete, Robert A. Day, Peter D. Keller
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Publication number: 20140189414Abstract: A data bus synchronizer includes a plurality of registers arranged in a cascade, configured to generate a synchronized output in response to sampling an asynchronous bus without an enable signal, where the plurality of registers receive a value on the asynchronous bus. A last register of the plurality of registers is configured to generate the synchronized output in response to a load enable signal. The data bus synchronizer further includes a logic block configured to generate the load enable signal on satisfaction of a logic condition.Type: ApplicationFiled: December 15, 2013Publication date: July 3, 2014Inventor: Gopalkrishna Ullal Nayak
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Patent number: 8766667Abstract: Asynchronous digital circuits are described, including arbitration and routing primitives for asynchronous and mixed-timing networks. An asynchronous arbitration primitive has two data inputs and one data output. A mutual exclusion element is used to select the first-arriving data request from one of the two inputs to the output. A asynchronous routing primitive has one data input and two data outputs. The incoming data is routed to one of the two outputs based on a routing bit accompanying the data. The primitives use handshaking with request and acknowledge signals to ensure that data is passed when neighboring circuits are ready to receive or send data.Type: GrantFiled: December 21, 2012Date of Patent: July 1, 2014Assignee: The Trustees of Columbia University in the City of New YorkInventors: Steven M. Nowick, Michael Horak, Matthew Carlberg
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Patent number: 8769067Abstract: Systems and methods for consolidating metrics and statistics used for load balancing by a plurality of cores of a multi-core intermediary are disclosed. A timer operating on each packet engine of each core in a multi-core system may expire. A consolidator may store, responsive to expiration of the timer, a set of counter values from each of the packet engines to a first storage location. The consolidator may send to each packet engine a message to update the set of counter values. The consolidator may, upon completion of updating the set of counter values by the packet engines, send a second message to the packet engines that includes a consolidated set of counter values determined based on the updated set of values from each packet engine. Each packet engine may establish settings and parameters for load balancing based on the consolidated set of counter values.Type: GrantFiled: June 22, 2009Date of Patent: July 1, 2014Assignee: Citrix Systems, Inc.Inventors: Murali Raja, Anil Shetty, Josephine Suganthi, Saravana Annamalaisami
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Patent number: 8769330Abstract: Methods and apparatuses are provided that allow for the synchronization of an operating point transition in an embedded system environment. Identification of an upcoming operating point transition, operating point transition constraints, and maximum parking latency parameters is provided. Then, an ordering of seizing bus activity as well as an ordering of resuming bus activity is determined. The operating point transition is then implemented using the determined ordering. Simulation and determination of change of successfully completing operating point transition prior to initiating and while the transition is pending are also provided.Type: GrantFiled: March 17, 2011Date of Patent: July 1, 2014Inventor: Adam Kaiser
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Publication number: 20140181567Abstract: Exemplary embodiments disclose a command control circuit including a command decoder configured to generate an internal command signal using a chip select (CS) signal and a command signal, and a CS gating logic configured to provide the CS signal to the command decoder, wherein the CS gating logic is further configured to provide the CS signal to the command decoder in response to a clock enable (CKE) signal being at a first level, and block the CS signal from the command decoder in response to the CKE signal being at a second level.Type: ApplicationFiled: December 5, 2013Publication date: June 26, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Hun-Dae CHOI, In-Dal SONG
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Patent number: 8762762Abstract: A method and apparatus for controlling the phase and frequency of the local clock of a USB device, the apparatus comprising circuitry for observing USB traffic and decoding from the USB traffic a periodic data structure containing information about the frequency and phase of a distributed clock frequency, and phase and circuitry for receiving the periodic data structure and generating from at least the periodic data structure a local clock signal locked in both frequency and phase to the periodic data structure. The circuitry for receiving the periodic data structure and generating the local clock signal can generate the local clock signal with a frequency that is a non-integral multiple of a frequency of the periodic data structure.Type: GrantFiled: February 15, 2007Date of Patent: June 24, 2014Assignee: ChronoLogic Pty LtdInventors: Peter Graham Foster, Alex Kouznetsov, Mykola Vlasenko
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Patent number: 8761327Abstract: Systems and methods are described including receiving a clock signal, using rational clock divider (RCD) logic to generate a lower frequency clock signal in response to the received clock signal, and using the second clock signal to drive software timer logic and generate media timestamps.Type: GrantFiled: June 14, 2011Date of Patent: June 24, 2014Assignee: Intel CorporationInventor: Pat Brouillette
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Publication number: 20140173321Abstract: Embodiments of a synchronous digital system are disclosed that may include generation of clock and synchronization signals. Any of a plurality of available clock signals may be selected for use as a primary clock, without causing clock-induced errors in the synchronous digital system. The clock signals may be selected automatically or programmatically. Clock generation circuitry may generate a clock signal that is initially used as the primary clock. The clock generation circuitry may be dynamically reconfigured without interrupting operation of the synchronous digital system, by first selecting another of the available clock signals for use as the primary clock.Type: ApplicationFiled: December 13, 2013Publication date: June 19, 2014Applicant: COHERENT LOGIX, INCORPORATEDInventors: Carl S. Dobbs, Michael R. Trocino, Kenneth R. Faulkner, Christopher L. Schreppel
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Publication number: 20140173322Abstract: Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory devices. The IDs are generated synchronously with clock. Command data and previously generated ID data are synchronously registered. The registered data is synchronously output and provided as parallel data for calculation of a new ID for the neighboring device. The calculation is an addition or subtraction by one. The IDs are generated in a packet basis by interpreting serial packet-basis commands received at the serial input in response to clocks. A clock latency is controlled in response to the interpreted ID and the clock. In accordance with the controlled clock latency, a new ID is provided in a packet basis. In high frequency generation applications (e.g., 1 GHz), two adjacent devices connected in daisy chain fashion are guaranteed enough time margin to perform the interpretation of packet commands.Type: ApplicationFiled: February 20, 2014Publication date: June 19, 2014Applicant: MOSAID TECHNOLOGIES INCORPORATEDInventors: Hong Beom PYEON, HakJune OH
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Patent number: 8755308Abstract: In response to a network topology change, a clock root node calculates a new clock path for each affected node by building a clock source topology tree, and identifying from that tree a path to the network node from a clock source of higher or equal stratum relative to that network node. The root node then sends a network message to each node indicating the new path that the node should use. Each node receives the message and compares the new path with the existing path. If the paths are different then the node acquires the new path just received in the message. If the paths are the same then the node does nothing and discards the message.Type: GrantFiled: January 31, 2012Date of Patent: June 17, 2014Assignee: Rockstar Consortium US LPInventors: Michel Ouellette, James Aweya, Delfin Y. Montuno, Kent Felske, Michael George Mayer
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Patent number: 8756446Abstract: A microprocessor has a low-power mode and a non-low power mode. The microprocessor includes a processor core for executing instructions provided to the microprocessor and a clock providing a clock signal, which in the non-low power mode has a first frequency and in the low power mode has a second frequency lower than the first frequency. A hardware timer is present, for scheduling an execution of an event by the microprocessor at a future point in time. The hardware timer is connected to the clock for determining a period of time between a current point in time and a point in time the event based on a number of clock cycles of the clock signal. A timer controller can determine, when the data processing system switches from the low power mode to the non-low power mode, a number of clock cycles of a clock signal with the first frequency that corresponds to a low-power mode period during which the microprocessor has been in the low power mode and adjusting the hardware timer based on the determined number.Type: GrantFiled: April 11, 2008Date of Patent: June 17, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Vianney Rancurel, Vincent Bufferne, Gregory Meunier
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Patent number: 8756395Abstract: Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.Type: GrantFiled: February 27, 2012Date of Patent: June 17, 2014Assignee: Rambus Inc.Inventors: Richard M. Barth, Ely K. Tsern, Craig E. Hampel, Frederick A. Ware, Todd W. Bystrom, Bradley A. May, Paul G. Davis
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Patent number: 8756452Abstract: Pulses are used to control work ingress. Generally, a variable-speed clock is used for accepting work for lower-priority services. A clock rate is controlled by a load monitor. The load monitor periodically collects sensor measurements of resources available after allocations by higher-priority services. Based on the sensor measurements, the load monitor adjusts the clock speed up or down (i.e., depending on the amount of resources available after allocations by higher-priority services). At the boundary of the lower-priority service (e.g., where work enters the system), work requests are enqueued to be associated with a future pulse of the clock. Work is accepted or rejected based on a determination of whether the work request can be allocated a clock pulse within a defined period of time.Type: GrantFiled: March 1, 2013Date of Patent: June 17, 2014Assignee: Microsoft CorporationInventors: Nicholas A. Allen, Justin D. Brown
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Patent number: 8751852Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, and a delay-locked loop (DLL). The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to delay a data bit signal associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The DLL is coupled to the ratio bus, and is configured generate a delayed data bit signal, where the DLL adds the amount of delay to the data bit signal to generate the delayed data bit signal.Type: GrantFiled: June 21, 2011Date of Patent: June 10, 2014Assignee: Via Technologies, Inc.Inventors: Darius D. Gaskins, James R. Lundberg
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Patent number: 8751853Abstract: A Quad-Data Rate (QDR) controller and an implementation method thereof are disclosed in the present invention. The controller includes: an arbiter, a control state machine, a read data sampling clock generating module, a read data path module and a read data path calibrating module. The arbiter arbitrates commands and data according to the state of the control state machine; the read data sampling clock generating module generates read data sampling clocks with the same source and same frequency and different phases; the read data path calibrating module determines, among the generated read data sampling clocks, sampling clocks of positive edge data and negative edge data for the read data path module to read data by reading training words when the control state machine is in “read data path calibrating state”; the read data path module synchronizes the positive edge read data and negative edge data in a non-system clock domain to the system clock domain according to the determined sampling clocks.Type: GrantFiled: December 22, 2010Date of Patent: June 10, 2014Assignee: ZTE CorporationInventors: Jishan Ding, Wei Huang, Wei Lai, Jianbing Wang, Kedong Yu, Zhiyong Liao
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Patent number: 8751851Abstract: An apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, a core clocks generator, and a synchronous strobe driver. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to advance a synchronous data strobe associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The core clocks generator is coupled to the ratio bus and is configured to advance a data strobe clock by the amount. The synchronous strobe driver is configured to receive the data strobe clock, and is configured to employ the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the amount.Type: GrantFiled: June 21, 2011Date of Patent: June 10, 2014Assignee: VIA Technologies, Inc.Inventors: Darius D. Gaskins, James R. Lundberg
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Patent number: 8751850Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network, a composite delay element, and delay-locked loops (DLLs). The resistor network is configured to provide a ratio signal that indicates an amount to delay data bit signals associated with a data group. The composite delay element is configured to equalize delay paths within a receiving device, where the delay paths correspond to a data strobe signal that is received from a transmitting device. The receiving device and resistor network are coupled to a motherboard. The ratio signal enters said receiving device through an external pin. The DLLs are coupled to the ratio signal and disposed within the receiving device, and are configured to generate delayed data bit signals, where the DLLs add the amount of delay to the data bit signals to generate the delayed data bit signals.Type: GrantFiled: June 21, 2011Date of Patent: June 10, 2014Assignee: VIA Technologies, Inc.Inventors: Darius D. Gaskins, James R. Lundberg
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Patent number: 8745431Abstract: A method of synchronizing a compound Super Speed USB device, comprising: providing data communication between a host computing device and the compound Super Speed USB device across the Super Speed USB communication channel; establishing a Super Speed USB communication channel to a Super Speed USB function of the compound USB device; establishing a non-Super Speed synchronization channel to a non-Super Speed USB function of the compound USB device; and synchronizing a local clock of the compound USB device to a periodic data structure within a data stream in the non-Super Speed synchronization channel so that the local clock can enable synchronous operation of the compound USB device with one or more comparable USB devices.Type: GrantFiled: May 20, 2010Date of Patent: June 3, 2014Assignee: Chronologic Pty. Ltd.Inventor: Peter Graham Foster
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Patent number: 8745430Abstract: The disclosed embodiments provide a system that facilitates synchronization between a first component and a second component connected to the first component via an interface in a computer system. During an active state of the interface, the system uses a local time base in the second component to generate a local clock signal that tracks a host clock signal from the first component. Next, during an inactive state of the interface, the system uses the local time base to maintain the local clock signal at the second component. Finally, during a subsequent active state of the interface after the inactive state, the system adjusts the local clock signal to remove clock drift between the local clock signal and the host clock signal.Type: GrantFiled: April 27, 2011Date of Patent: June 3, 2014Assignee: Apple Inc.Inventors: William P. Cornelius, William O. Ferry, Girault W. Jones
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Patent number: 8743633Abstract: An integrated semiconductor device including: a first semiconductor device having a clock generation section, first data storage sections storing input data as transfer data, data output terminals provided, one for each of the first data storage sections, and a clock output terminal adapted to output a transfer clock; and a second semiconductor device having data input terminals which receive the transfer data, a clock input terminal adapted to receive the transfer clock, second data storage sections associated with the data input terminals respectively to store input data, and selection sections associated with the second data storage sections respectively to select either the transfer data or data shifted and output to the associated second data storage section in a first series circuit which is formed by connecting the second data storage sections in series, the selection sections supplying the selected data to the associated second data storage section.Type: GrantFiled: June 13, 2011Date of Patent: June 3, 2014Assignee: Sony CorporationInventor: Takenori Aoki
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Publication number: 20140143582Abstract: A hearing assistance system including a hearing instrument designated as a master device and at least another hearing instrument designated as a slave device. The master device is communicatively coupled to the slave device via a wireless link. The master device has a master clock and generates master time stamps for specified events timed by the master clock. The master time stamps are sent to the slave device via the wireless link. The slave device has a slave clock and generates slave time stamps for specified events timed by the slave clock. The slave clock is adjusted for synchronization to the master clock using the master time stamps and the slave time stamps.Type: ApplicationFiled: November 21, 2012Publication date: May 22, 2014Applicant: Starkey Laboratories, Inc.Inventors: Jon S. Kindred, Tao Zhang, Ivo Merks, Jeffrey Paul Solum, Mihran H Touriguian
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Publication number: 20140143581Abstract: A system for transferring data between asynchronous domains in an SOC includes a slave request generation and data latch circuit, a busy signal generator, a positive edge detector, and a cascaded synchronizer. A host device transmits a host request signal and host data to the slave request generation and data latch circuit for execution by a slave device, which operates at a different frequency than the host device. The slave request generation and data latch circuit stores the host data and transmits it to the slave device based on a synchronized slave clock signal. The host device can perform other tasks while the slave device executes the host request.Type: ApplicationFiled: November 21, 2012Publication date: May 22, 2014Inventors: Sandeep Garg, Asif Igbal, Rajan Kapoor
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Publication number: 20140143580Abstract: Implementations of the present disclosure involve an apparatus and/or method for synchronizing at least one newly activated processor with at least one previously running processor. Each processor is configured to generate a heartbeat and operate according to a STICK. When a previously deactivated processor is added, the heartbeat of each active processor is reset and the current STICK is transmitted to the newly activated processor on the next heartbeat. The newly activated processor may then add the heartbeat period to the acquired STICK and begin incrementing the STICK and normal operation after the next heartbeat.Type: ApplicationFiled: November 16, 2012Publication date: May 22, 2014Applicant: Oracle International CorporationInventor: Ali Vahidsafa
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Patent number: 8732514Abstract: Clock pulses of a variable speed clock are adjusted relative to system utilization. A load monitor periodically collects sensor measurements of resources and based on the sensor measurements, the load monitor adjusts the clock speed up or down.Type: GrantFiled: March 4, 2013Date of Patent: May 20, 2014Assignee: Microsoft CorporationInventors: Nicholas A. Allen, Justin D. Brown
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Patent number: 8732509Abstract: An apparatus for synchronizing an output clock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter. The first timing synchronization circuit is operable to generate a delay to synchronize a reference clock signal representative of the input clock signal with a feedback clock signal representative of the output clock signal responsive a strobe signal. The control logic is operable to generate an enable signal based on the reference clock signal and generate the strobe signal based on the feedback clock signal. The counter is operable to count cycles of the reference clock signal occurring between the enable signal and the strobe signal to generate a loop count for the first timing synchronization circuit.Type: GrantFiled: April 7, 2010Date of Patent: May 20, 2014Assignee: Micron Technology, Inc.Inventor: Jongtae Kwak
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Patent number: 8726064Abstract: An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths are arranged and operated so as to control the power consumption and data skew properties of the system. A configurable switching element may be used to form the interconnections at nodes, where a control signal and other information is used to manage the power status of other aspects of the configurable switching element. Time delay skew of data being transmitted between nodes of the network may be altered by exchanging the logical and physical line assignments of the data at one or more nodes of the network. A method of laying out an interconnecting motherboard is disclosed which reduces the complexity of the trace routing.Type: GrantFiled: April 17, 2006Date of Patent: May 13, 2014Assignee: Violin Memory Inc.Inventor: Jon C. R. Bennett
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Patent number: 8724663Abstract: An implementation method and system, main control device and smart card for information transmission are provided. The method includes: the smart card notifying the main control device of the operating mode supported thereby; the smart card receiving a clock frequency returned by the main control device, and if the main control device determines that the smart card can support an externally provided clock frequency, the clock frequency is a second clock frequency; judging whether the smart card itself can support the second clock frequency, and if true, the smart card and the main control device carrying out information transmission based on the clock control signal of the second clock frequency; otherwise the smart card carrying out the transmission based on the dock control signal of the first clock frequency, and the main control device carrying out the transmission based on the clock control signal of the second clock frequency.Type: GrantFiled: March 3, 2011Date of Patent: May 13, 2014Assignee: ZTE CorporationInventor: Guohe Liang
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Patent number: 8726062Abstract: The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is entirely digital and usable in any multi-link transceiver implementation that makes use of a separate clock link and requires timing synchronization between the different data links.Type: GrantFiled: December 1, 2011Date of Patent: May 13, 2014Assignee: Synopsys, Inc.Inventor: Jose Angelo Rebelo Sarmento
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Patent number: 8726061Abstract: Multiple media devices are synchronized in a multi-media system having a computer system, a plurality of media devices, and a display system. Each media device to be synchronized receives a front-end synchronization signal that periodically increments a front-end counter. The front-end counter represents an unadjusted system time (UST). The media device obtains a frame of data to be displayed from a computer system. The media device also receives a back-end synchronization signal that periodically increments a back-end counter each time a frame of data is to he displayed. The back-end counter represents a media stream count (MSC). UST and MSC data are periodically transmitted to the computer system for analysis and use by a synchronization algorithm. Specifically, UST is transmitted to the computer system each time a frame of data is obtained, and a UST/MSC pair is transmitted to the computer system each time a frame of data is displayed.Type: GrantFiled: August 8, 2011Date of Patent: May 13, 2014Assignee: RPX CorporationInventors: Michael K. Poimboeuf, Francis S. Bernard, Kevin A. Smith, Parkson Wong, Todd S. Stock, William R. Lawson
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Patent number: 8724320Abstract: A fan system includes a pulse signal generation portion and a plurality of fans. Each of the plurality of fans preferably includes a motor portion; an impeller arranged to be rotated by the motor portion; a drive circuit arranged to drive the motor portion; a rotation detection portion arranged to detect rotation of the motor portion; and a rotation rate control circuit arranged to, based on a reference pulse signal supplied from the pulse signal generation portion and an actual rotation pulse signal supplied from the rotation detection portion, exercise feedback control on a rotation rate of the motor portion in accordance with a period of the reference pulse signal.Type: GrantFiled: January 26, 2011Date of Patent: May 13, 2014Assignee: Nidec CorporationInventors: George Harlan, Masayuki Kato, Hideyuki Takemoto, Masamune Hiraki
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Patent number: 8719616Abstract: A method for encoder frequency-shift compensation includes determining frequency values of an input encoder signal, determining repeatable frequency-shifts of the frequency values and generating a frequency-shift compensated clock using the repeatable frequency-shifts. A frequency-shift compensated clock includes a synthesizer configured to generate a frequency-shift compensated clock signal using repeatable frequency shifts and encoder clock signals.Type: GrantFiled: February 22, 2013Date of Patent: May 6, 2014Assignee: Seagate Technology LLCInventors: Koichi Wago, Sundeep Chauhan, David M. Tung
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Publication number: 20140122915Abstract: Techniques and systems for synchronizing a clock via a backplane. An apparatus includes a backplane, a clock coupled to or included in the backplane, a synchronization interface, and at least one processing element coupled to the clock via the backplane and coupled to or including the synchronization interface. The at least one processing element may be configured to compare first time information received from the clock via the backplane with second time information received from the synchronization interface. The second time information may be associated with an external clock. The at least one processing element may determine adjustment information based on the comparison and synchronize the clock with an external clock using the adjustment information, via the backplane. The apparatus may be a PXIe chassis. The clock output may be sent to modules plugged into the backplane in order to synchronize them with an external chassis clock, for example.Type: ApplicationFiled: October 30, 2012Publication date: May 1, 2014Applicant: NATIONAL INSTRUMENTS CORPORATIONInventors: Jason W. Frels, Rodney D. Greenstreet, Gabriel L. Narus, Mark R. Wetzel
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Patent number: 8713344Abstract: A system includes a system controller and a configuration of series-connected semiconductor devices. Such a device includes an input for receiving a clock signal originating from a previous device, and an output for providing a synchronized clock signal destined for a succeeding device. The device further includes a clock synchronizer for producing the synchronized clock signal by processing the received clock signal and an earlier version of the synchronized clock signal. The device further includes a device controller for adjusting a parameter used by the clock synchronizer in processing the earlier version of the synchronized clock signal. The system controller has an output for providing a first clock signal to a first device, and an input for receiving a second clock signal from a second device. The second clock signal corresponds to a version of the first clock signal that has undergone processing by a clock synchronizer in at least one of the devices.Type: GrantFiled: November 17, 2010Date of Patent: April 29, 2014Assignee: Mosaid Technologies IncorporatedInventor: HakJune Oh
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Publication number: 20140115374Abstract: A reset of a synchronization counter is synchronized to an external deterministic signal. Entry into the link transmitting state is further synchronized with the deterministic signal. A target latency is identified for a serial data link. A data sequence is received synchronized with a synchronization counter associated with the data link. Target latency can be maintained using the data sequence.Type: ApplicationFiled: March 27, 2013Publication date: April 24, 2014Inventors: Venkatraman Iyer, Darren S. Jue, Jeff Willey, Robert G. Blankenship