Abstract: A mechanism to generate a self-clock within a synchronous processing unit of an asynchronous digital device. The self-clock is designed to match the worst-case delay of pipeline processing unit in such a way that the pipeline processing unit is operate at its own natural clock frequency and shutting off when there is no valid data to process. The synchronization logic of the processing unit consists of self-clock that generates output clock to synchronize with the internal clock edge if the processing unit is active or synchronize with the input clock edge if the processing unit is inactive.

Abstract: A non-volatile memory device includes a memory core storing data to be output from the memory core according to an external clock signal, an input buffer receiving the external clock signal and providing an input clock signal, and a synchronization circuit including a delay circuit and configured to receive the input clock signal, provide an output clock signal, and synchronize the output clock signal to the external clock signal. The device further includes a data strobe output buffer receiving the output clock signal and providing a data strobe signal having a signal delay configurable relative to the external clock signal, a clocked circuit element receiving the data and the output clock signal and outputting the data in synchronism with the output clock signal, and a delay control circuit providing a delay control signal to the delay circuit to modify the signal delay of the data strobe signal.

Abstract: A number of switching transitions of flip-flops during testing is kept below a threshold. Scan-in test data is applied to the flip-flops. Testing result data scanned-out from the flip-flops is captured, and a prediction is made of a number of switching transitions of the flip-flops between a current capture clock cycle and a next capture clock cycle—in particular, for the next capture clock cycle—thereby using the scan-in test data for the next capture clock cycle and the testing result data scanned-out of the current capture clock cycle. Furthermore, the testing setup values are modified before the next testing cycle is executed based on the prediction in order to enter a new configuration of a testing circuit such that the predicted number of switching transitions of the flip-flops stays below the threshold. The testing setup values comprise parameters for modifying the capture clock cycle and a seed value for generating test patterns.

Abstract: A number of switching transitions of flip-flops during testing is kept below a threshold. Scan-in test data is applied to the flip-flops. Testing result data scanned-out from the flip-flops is captured, and a prediction is made of a number of switching transitions of the flip-flops between a current capture clock cycle and a next capture clock cycle—in particular, for the next capture clock cycle—thereby using the scan-in test data for the next capture clock cycle and the testing result data scanned-out of the current capture clock cycle. Furthermore, the testing setup values are modified before the next testing cycle is executed based on the prediction in order to enter a new configuration of a testing circuit such that the predicted number of switching transitions of the flip-flops stays below the threshold. The testing setup values comprise parameters for modifying the capture clock cycle and a seed value for generating test patterns.

Abstract: A data reception chip coupled to an external memory comprising a first input-output pin to output first data and including a comparison module and a voltage generation module is provided. The comparison module is coupled to the first input-output pin to receive the first data and compares the first data with a first reference voltage to identify the value of the first data. The voltage generation module is configured to generate the first reference voltage and includes a plurality of first resistors and a first selection unit. The first resistors are connected in series with one another and dividing a first operation voltage to generate a plurality of first divided voltages. The first selection unit selects one of the first divided voltages as the first reference voltage according to a first control signal.

Abstract: A method includes, with a hypervisor, detecting that a virtual processor of a virtual machine has accessed a designated address, the designated address being associated with a time value, causing the virtual processor to enter a halt state for a period of time, and causing the virtual processor to exit the halt state after a period of time has passed, the period of time being based on the time value.

Abstract: A slave node (104) includes N time regeneration units (105 to 107) each of which communicates with each of N master nodes (101 to 103) to compute a propagation delay between each master node (101 to 103) and the slave node (104) and regenerates a time of each master node (101 to 103), a time comparison unit (108) that independently computes each comparison result between the time of each master node (101 to 103), which is regenerated by each of N time regeneration units (105 to 107), and a reference time held by the slave node (104), and a reference time determination unit (109) that computes each correction value by carrying out weighting for each comparison result computed by the time comparison unit (108) based on the propagation delay and determines a reference time of the slave node (104) by carrying out statistical processing by using the correction value. With this configuration, it is possible to improve precision and accuracy of synchronization of the time of the slave node at low cost.

Abstract: A method, an apparatus, and a computer program product for wireless communication are provided in connection with enabling distributed frequency synchronization based on a fastest node clock rate. In one example, a first UE is equipped to determine that a fastest clock rate is faster than an internal clock rate of the first UE by more than a first positive offset, and adjust the internal clock rate based on the determined fastest clock rate. In an aspect, the fastest clock rate is associated with a second UE of one or more other UEs from which synchronization signals may be received. In another example, a UE is equipped to obtain GPS based timing information, adjust an internal clock rate based on the GPS based timing information, and transmit a synchronization signal at an artificially earlier time in comparison to a scheduled time of transmission associated with the adjusted internal clock rate.

Abstract: Embodiments relate to multi-cycle signal identification for static timing analysis. An aspect includes identifying, in a circuit under test, a multi-cycle signal, the multi-cycle signal having a longer period than a main clock signal of the circuit under test. Another aspect includes mapping a plurality of additional signals of the circuit under test onto the multi-cycle signal, the plurality of additional signals each having a shorter period than the multi-cycle signal. Yet another aspect includes performing static timing analysis of the circuit under test based on the multi-cycle signal.

Abstract: A distributable and serializable finite state machine and methods for using the distributable and serializable finite state machine are provided wherein finite state machine instance can be location-shifted, time-shifted or location-shift and time-shifted, for example by serializing and deserializing each instance. Each instance can be located-shifted between agents, and a persistent memory storage location is provided to facilitate both location-shifting and time-shifting. Finite state machine instances and the actions that make up each instance can be run in a distributed fashion among a plurality of agents.

Abstract: Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the dock signals output from the push-pull buffers.

Abstract: Avoiding long access latencies in redundant storage systems is disclosed, including: determining a first device associated with a request is in a slow access period; and reconstructing data associated with the request from one or more other devices comprising a redundant storage system in which the first device and the one or more other devices are included.

Abstract: A physical layer communication device (PHY) transmits and receives signal to and from a communication link using a synchronous protocol. The PHY communicates with a higher-layer device using a packet protocol. Timestamp values contained in timing-related messages in some packets are written or modified by the PHY. Delays incurred in transmitting and receiving the packets are predicted and used in setting the timestamp values.

Abstract: A method, a computer program product, and a carrier for indicating one-way latency in a data network (N) between a first node (A) and a second node (B), wherein the data network (N) lacks continuous clock synchronization, comprising: a pre-synchronization step, a measuring step, a post-synchronization step, an interpolation step, and generating a latency profile. The present invention also relates to a computer program product incorporating the method, a carrier comprising the computer program product, and a method for indicating server functionality based on the first aspect.

Abstract: An apparatus for synchronizing an output clock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter. The first timing synchronization circuit is operable to generate a delay to synchronize a reference clock signal representative of the input clock signal with a feedback clock signal representative of the output clock signal responsive a strobe signal. The control logic is operable to generate an enable signal based on the reference clock signal and generate the strobe signal based on the feedback clock signal. The counter is operable to count cycles of the reference clock signal occurring between the enable signal and the strobe signal to generate a loop count for the first timing synchronization circuit.

Abstract: A memory controller includes a differential receiver circuitry to receive a differential data strobe signal pair and to generate a first data strobe signal based on the differential data strobe signal pair. The differential data strobe signal pair comprises a first signal and a second signal. The memory controller also includes a single ended receiver circuitry to receive the first signal of the differential data strobe signal pair and to generate a second data strobe signal based on the first signal of the differential data strobe signal pair. The memory controller further includes circuitry to generate a gating signal for gating the first data strobe signal, the circuitry generating the gating signal based on the second data strobe signal.

Abstract: An arrangement for transferring a data signal from a first clock domain (bus_slow) to a second clock domain (bus_fast) in a digital system. The first clock domain (bus_slow) has a first clock (ck slow) with a frequency less than a frequency of a second clock (ck fast) in the second clock domain (bus_fast). The arrangement is configured to transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast), detect whether a predetermined transition occurs in the first clock (ck slow) within a predetermined period of time, using detecting means (2) clocked by the second clock (ck fast), and transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast) again if the detecting means (2) detects the predetermined transition in the first clock (ck slow) within the predetermined period of time.

Abstract: Method and apparatus for dynamically changing streaming video quality are described herein. In one embodiment, a network traffic condition of a network and a local processing bandwidth of a client are periodically determined. A data compression method and/or compression rate is dynamically selected that is most appropriate to transmit a video frame to the client over the network in view of the determined network traffic condition and the local processing bandwidth of the client. The video frame is then compressed using the selected compression method and/or compression rate and sent over to a client to be rendered at the client.

Abstract: Some demonstrative embodiments include devices, systems and methods of synchronizing between wireless communication devices. For example, a wireless communication device may include a clock to count a local time; a controller to count a virtual master clock corresponding to a group of wireless communication devices according to master clock information defining the virtual master clock, the controller to determine a time drift between the local clock and the virtual master clock, and to determine the virtual master clock based on the local time and the time drift; and a radio to communicate with one or more devices of the group of wireless communication devices a synchronization frame including a master clock time stamp of the virtual master clock.

Abstract: A method of operating an automation system cyclically communicating with a central unit in accordance with a send clock and a predetermined reduction ratio using a first cycle time, wherein the central unit uses a send clock SCC for its communication, and communicates with the automation device taking into account the send clock and a reduction ratio of the automation device, and wherein the send clock for the automation device is divided by the send clock of the central unit, the largest power-of-2 value smaller than the division result is selected and multiplied with the reduction ratio of the automation device resulting in a reduction ratio of the central unit for communicating with the automation device, and the reduction ratio of the automation device is used to step down the send clock of the central unit for cyclically communicating with the automation device using a second cycle time.

Abstract: A direct-transfer marching memory includes an array of memory units, each of the memory units having a sequence of bit-level cells so as to store information of byte size or word size, the information of byte size or word size is transferred synchronously, step by step, along a direction orthogonal to a direction of the sequence of bit-level cells, each of the bit-level cells encompassing an electron-storage region configured to accumulate cell-electrons. The cell-electrons accumulated in an electron-storage region in a subject memory unit is directly transferred to an adjacent electron-storage region, which is assigned in the next memory unit adjacent to the subject memory unit, the transfer of the cell-electrons is directly controlled by control signals, without using a combinational function of a logic gate circuit.

Abstract: A method for serial interface clock domain crossing includes identifying a data communication command received over a serial interface. An address is decoded to determine whether the address falls within a direct latch address range of a register bank. Data is communicated over the serial interface. A multiplexed output clock is generated, for writing to and reading from the register bank, based on at least one of a current system operating state and a refresh control signal from a host processor.

Abstract: A system includes memory unit having one or more storage arrays, and a memory interface unit that may be coupled between a memory controller and the memory unit. The memory interface unit may include a timing unit that may generate timing signals for controlling read and write access to the memory unit, and a control unit that may calibrate the timing unit at predetermined intervals. However, in response to an occurrence of a given predetermined interval, the memory interface unit may be configured to calibrate the timing unit using a number of partial calibration segments.

Abstract: A method for data synchronization is provided according to certain embodiments. The method comprises receiving data, a data clock signal, and a clean clock signal, sampling the data using the data clock signal, synchronizing the sampled data with the clean clock signal, and outputting the synchronized sampled data. The method also comprises tracking a phase drift between the data clock signal and the clean clock signal, and pulling in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a first value in a first direction.

Abstract: Systems and corresponding methods include a system having an operating system based wholly around a protocol stack, such as a Transmission Control Protocol/Internet Protocol (TCP/IP) stack. The system may include a central processing unit (CPU) including the operating system embedded therein, and a network interface coupled with a network and the CPU. The network may be the Internet. The operating system is fundamentally a state machine. The kernel of the operating system is fundamentally just a protocol stack for communicating with one or more devices of the network via the network interface. The protocol stack may be a TCP/IP protocol stack, UDP/IP stack or combinations thereof. A chip may be provided that includes the TCP/IP stack state machine-based operating system embedded in a CPU. The resultant chip may be ultra low power, miniscule in size, and IP-centric.

Abstract: High frequency current transients, due to logic switching inside the CPU, are reduced by applying clock signals having different relative phases to different parts of the CPU. This reduces the amplitude of current variations, and hence noise induced onto the power supply voltage. In some embodiments, different CPU cores within multi-core CPUs are clocked with a different clock phases. Additionally a method and circuit for low-latency communication in the presence of large OCV effects is provided. The low-latency communication may be based on a FIFO. Strobes are used to indicate safe points in time to update and read signals between transmitter and receiver. The strobes are generated in a central clock generation module. The strobe mechanism is used to transfer the read and write pointers between the transmitter and receiver, while the payload data is transferred using a FIFO data array that allows data writes to be asynchronous to corresponding data reads.

Abstract: Inventive aspects include integrated clock gating logic that can generate an internal glitch-free clock signal. Inventive aspects further include a toggle latch that is coupled to the integrated clock gating logic. The toggle latch can receive the internal clock signal from the integrated clock gating logic. The toggle latch can toggle and latch a data value responsive to the internal clock signal. The integrated clock gating logic can include a latch to latch a clock gating logic signal responsive to a clock signal. The clock gating logic signal can cause the internal clock signal to be quiescent when the input data to the flip-flop remains constant, thereby conserving power consumption.

Abstract: A system for managing a change in a frequency of a clock signal, including a clock generator configured to output the clock signal, a clock divider coupled to the output of the clock generator, a processor configured to select the frequency of the clock signal, and a clock management circuit. The clock management circuit may be configured to set the clock generator to adjust the clock signal to the selected frequency. The clock management circuit may be further configured to adjust a divisor value of the clock divider in a plurality of steps in response to a determination the clock signal stabilized at the selected frequency. A new divisor value may be selected during each step in the plurality of steps and each step may occur after a given time period.

Abstract: A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data. A bus system clock signal is received. The latch signal is evaluated and a wait state for the non-volatile memory device is adjusted based on the evaluation. The wait state represents a number of cycles of the bus system clock used by a central processing unit for an access of the non-volatile memory device. A bus system data ready signal that is triggered based on the adjusted wait state is produced. The bus system data ready signal, when triggered, indicates that data is available responsive to the request.

Abstract: Arrangements and methods for facilitating access to VPN-derived data regardless of computing platform power state.

Abstract: One feature pertains to the synchronization of a serial time-division-multiplexed bus interconnecting an audio processing subsystem (i.e. a local node) with an audio coder-decoder (CODEC) subsystem (i.e. a remote node.) Control signals are transmitted along a bidirectional transmission line of the bus from the audio processing subsystem to the audio CODEC subsystem. The audio processing subsystem tracks an internal state machine phase count as the control signals are transmitted. The audio CODEC subsystem also tracks an internal state machine phase count as the signals are received. Transmission of control signals by the audio processing subsystem is periodically paused or suspended for a fixed interval of time based on the phase count to allow the audio CODEC subsystem to send a synchronization indicator signal back to the audio processing subsystem, which the audio processing subsystem uses to verify synchronization. This may be performed, for example, once every one hundred-twenty phase counts.

Abstract: A clock regenerator includes a pulse generating module, a control logic module, a gating module and an output module. The pulse generating module is configured to receive a global clock signal and produce a periodic pulse signal triggered by a rising edge of the global clock signal. The control logic module is configured to receive a plurality of control signals and produce a pulse-type setting signal and a gating signal according to the periodic pulse signal and the control signals. The gating module is configured to produce an intermediate clock signal according to the pulse-type setting signal and the gating signal. The output module is configured to provide a local clock signal according to the intermediate clock signal.

Abstract: Embodiments of a multi-processor system and method for synchronization and event scheduling of multiple processing elements are generally described herein. In some embodiments, timing marks are provided to the processing elements and a start-timer command is broadcasted to the processing elements after an initial timing mark. The start-timer command instructs the processing elements to initiate an internal time reference after receipt of a next timing mark. Each of the processing elements maintains a copy of the internal time reference which may be used for synchronized event scheduling.

Abstract: An exemplary method of synchronizing a master clock and a slave clock comprises transmitting a plurality of packets between a master device and a slave device, calculating a first skew between a first pair of the plurality of packets at the slave device and a second skew between the first pair at the master device, calculating a ratio between the first skew and the second skew, providing a slave clock frequency correction to the slave device, calculating a first packet trip delay using a time that the master device initiates sending a packet to the slave device, a time the master device receives a response from the slave device, a corrected time the slave device receives the packet, and a corrected time the slave device initiates sending the response, calculating a first offset based on the first packet trip delay, and providing the first offset to the slave device.

Abstract: A circuit for generating a peripheral clock for USB, provided on a USB major structure, comprises an internal oscillator, a receiver, a transmitter, a clock counter, and a clock processor; wherein the internal oscillator generates a clock having a settled frequency; the receiver is connected with the internal oscillator and a system unit, and receives a packet transmitted by the system unit; the transmitter is connected with the internal oscillator and the system unit, and transmits a packet of the USB major structure to the system unit; the clock counter is connected with the receiver and the internal oscillator, and counts a length of the packet received; and the clock processor is connected with the clock counter, the internal oscillator, and the transmitter, and controls and adjusts a length of the packet transmitted by the transmitter according to the length of the packet counted by the clock counter.

Abstract: Techniques and mechanisms implement a sample rate converter for resampling data, such as audio data. The resampling may be based on a resampling clock. As the frequency of the resampling clock varies (e.g., due to jitter, rate adjustment, etc.), a control loop feedback mechanism can detect the variations and gradually correct the sampling rate of the resampled data.

Abstract: A method of determining desynchronization between a first implantable medical device and a second implantable medical device. The method includes receiving a synchronization query from the first device at the second device, that is transmitted in response to the first device detecting a predetermined transition of a first clock of the first device, the first clock having a first pulse rate. The method further includes determining a number of pulses of a second clock of the second device occurring between reception of the synchronization query and a predetermined transition of a third clock of the second device, the third clock having the first pulse rate. The second clock has a second pulse rate higher than the first pulse rate. The method further includes determining the desynchronization between the first device and the second device based on the determined number of pulses of the second clock.

Abstract: Integrated circuits having single-port memory elements may be provided. The single-port memory elements may be controlled using a control circuit to emulate multiport functionality. In one suitable embodiment, the control circuit may be an arbitration circuit configured to execute a memory request as soon as it is received by the arbitration circuit. Requests received while a current memory access is being performed may be put on hold until the current memory access has been completed. In another suitable embodiment, the control circuit may be a sequencing circuit configured to service memory access requests from a synchronous port and an asynchronous port. Memory access requests received at the synchronous port may be serviced immediately, whereas memory access requests received at the asynchronous port may be synchronized to an internal memory clock signal and may be serviced after a preceding memory access request associated with the synchronous port has been serviced.

Abstract: A method and a network node are provided, for distributing timing information in a packet-switched network. The method is characterized in that at least one network node used as a quasi slave node is located at a path extending between a master node and a slave node. The method comprising a step of calculating the timing at that network node, by passively processing packets belonging to a PTP-type packet stream being exchanged between the master node and the slave node and conveyed via that intermediate network node operating as a quasi slave.

Abstract: A nonvolatile memory system can include a nonvolatile memory device that can be configured to store data and a nonvolatile memory buffer circuit that can be configured to store data of a type that is predetermined to be flushed to the nonvolatile memory device in a sudden power off backup operation of the nonvolatile memory system, whereas a volatile memory buffer circuit can be configured to store other data of a type that is not to be flushed to the nonvolatile memory device in the sudden power off backup operation of the nonvolatile memory system.

Abstract: The accuracy of data processing operations in an electronic device is improved through reductions in errors associated with data acquisition, reading, and transmission. In one embodiment, two or more modules of an integrated circuit are operated at different clock speeds and a voting scheme is utilized to obtain a valid data value from one of the modules. The disclosure describes methods, devices and systems that utilize the voting schemes to eliminate errors induced by race conditions in obtaining valid data values during data transfer by obtaining a plurality of data samples while the communicating modules are operating at the different clock speeds and selecting from among the data samples the valid data value.

Abstract: A system is disclosed that may compensate for bus timing that may vary over operating conditions of a bus. The system may include a communication bus, a first functional unit configured to transmit data via the communication bus, and a second functional unit configured to receive data via the bus. The first functional unit may transmit a first value via the communication bus to the second functional unit. The first functional unit may be further configured to assert a data valid signal responsive to a determination that a first time period has elapsed since the transmission of the first data value. The second functional unit may be configured to receive the first data value and sample the first data value dependent upon the data valid signal.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to time stamp based data synchronization and provide a method, system and computer program product for scalable, ranging time stamp based data synchronization. In an embodiment of the invention, a ranging time stamp synchronization method can include computing a time range for a specified time, and producing time stamp synchronization anchors using the time range for each of the anchors. Optionally, a drift value can be computed for the time range and the computing and producing steps can be repeated when the drift value exceeds a threshold. Finally, the anchors can be used to determine whether to update data items in a remote data source in the remote host computing platform with data items from a primary data source in the primary host computing platform.

Abstract: A method and circuit for generating a shifted strobe signal for sampling data read from a memory device includes generating an instantiation of a shifted strobe signal by applying both a coarse adjustment delay value and a fine adjustment delay value to a clock. Data read from a predetermined, programmed memory location or locations of the memory device is sampled using the shifted strobe signal. At least one of the applying steps is repeated and the read data is sampled again using the current instantiation of the shifted strobe signal. The process is repeated until the current instantiation of the shifted strobe signal is aligned with a valid data window of the memory device. The method can be used in both single data rate and double data rate applications.

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

Abstract: An apparatus for detecting tampering with a clock of a state-machine, comprising, a master state-machine having master states and driven by a master clock, the master states being switchable responsive to events, and an auxiliary state-machine having auxiliary states and driven by an auxiliary clock synchronous with the master clock, the auxiliary states being switchable responsive to a signal generated based at least on said events, consequently establishing a correspondence between the master states and the auxiliary states, thus ensuing that subsequent to tampering with the master clock the correspondence between the master states and the auxiliary states become discordant, thereby indicating that the master clock has been tampered with.

Abstract: Approaches for configuring a programmable integrated circuit (IC) are disclosed. Encrypted configuration data is input to the programmable IC, and the encrypted configuration data is stored in configuration memory of the programmable IC. As the encrypted configuration data is input, a determination is made as to whether or not the encrypted configuration data is authentic. In response to the encrypted configuration data being authentic, the encrypted configuration data is read from the configuration memory and decrypted, and the decrypted configuration data is stored back in the configuration memory.

Abstract: Integrated circuits with high-speed communications capabilities are provided. Such types of integrated circuits may include clock data recovery (CDR) circuitry. The CDR circuitry may receive incoming data and may generate a recovered clock that is phase-aligned to the incoming data. The CDR circuitry may also include data latching circuitry for separately latching even and odd data bits in alternating clock cycles. During a first mode, a first portion of the data latching circuitry may be used to latch even data bits while a second portion of the data latching circuitry may be used to latch odd data bits. During a second mode, the second portion of the data latching circuitry may be used to latch the even data bits while the first portion of the data latching circuitry may be used to latch the odd data bits. The mode that yields the better link performance may be selected.

Abstract: Technologies related to secure system time reporting are generally described. In some examples, responses to some system time requests may be manipulated to prevent leaking information that may be of interest for timing attacks, while responses to other system time requests need not be manipulated. In particular, responses to system time requests that are separated from a previous system time request by a predetermined minimum value, or less, may be manipulated. Responses to system time requests that are separated from a previous system time request by more than the predetermined minimum value need not be manipulated. Furthermore, secure system time reporting may be adaptively deployed to servers in a data center on an as-needed basis.

Abstract: A method and a device for synchronizing broadcast of streaming data by a transmitting data processing unit to a plurality of receiving data processing units is provided. After a data word has been sent, a synchronizer in the transmitting data processing unit collects an acknowledge signal from each of the receiving data processing units and then generates an indication that the next data word can be transmitted. This allows to speed-up data delivery to parallel working processing units in a system-on-a-chip since data delivery has no longer to account for a maximum predictable latency of the respective receiving units.