Abstract: A method for synchronizing the operating clock and the timing clock of a subordinate domain of an automation network, wherein sync slaves are synchronized by a clock sync master with respect to an operating clock, a clock sync master forms part of a subordinate domain, a single synchronization message serves to synchronize the sync slaves with respect to their respective operating clock and timing clock, wherein the method comprises providing a notification of the difference between the timing clock and the operating clock using the synchronization message, and accepting this difference into the synchronization message as additional information.

Abstract: A clock synchronization method, customer premises equipment and a clock synchronization system are provided. The customer premises equipment reads a first time stamp when receiving a first specific position of a first DMT signal sent by central office equipment; reads a second time stamp when sending a second specific position of a second DMT signal; receives a third time stamp and a fourth time stamp that are sent by the central office equipment through a data information channel. The third time stamp is read when the central office equipment sends the first specific position of the first DMT signal, and the fourth time stamp is read when the central office equipment receives the second specific position of the second DMT signal. The customer premises equipment adjusts a clock of the customer premises equipment according to the first, second, third and fourth time stamps.

Abstract: A data processing unit has a time information provider for processing a clock or a strobe signal, configured to provide a digitized clock or strobe time information on the basis of the clock or strobe signal and at least one data extraction unit, coupled to the time information provider and configured to select data from a sequence of data samples of a data signal depending on the digitized clock or strobe time information.

Abstract: Integrated circuits having single-port memory elements may be provided. The single-port memory elements may be controlled using a control circuit to emulate multiport functionality. In one suitable embodiment, the control circuit may be an arbitration circuit configured to execute a memory request as soon as it is received by the arbitration circuit. Requests received while a current memory access is being performed may be put on hold until the current memory access has been completed. In another suitable embodiment, the control circuit may be a sequencing circuit configured to service memory access requests from a synchronous port and an asynchronous port. Memory access requests received at the synchronous port may be serviced immediately, whereas memory access requests received at the asynchronous port may be synchronized to an internal memory clock signal and may be serviced after a preceding memory access request associated with the synchronous port has been serviced.

Abstract: Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.

Abstract: A time synchronization method and system for a multi-core system are provided.

Abstract: A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing.

Abstract: A method and apparatus for controlling the phase and frequency of the local clock of a USB device, the apparatus comprising circuitry for observing USB traffic and decoding from the USB traffic a periodic data structure containing information about the frequency and phase of a distributed clock frequency, and phase and circuitry for receiving the periodic data structure and generating from at least the periodic data structure a local clock signal locked in both frequency and phase to the periodic data structure. The circuitry for receiving the periodic data structure and generating the local clock signal can generate the local clock signal with a frequency that is a non-integral multiple of a frequency of the periodic data structure.

Abstract: A phase interpolator for a CDR circuit produces an output clock having level transitions between the level transitions on two input clocks. The input clocks drive cross-coupled differential amplifiers with an output that can be varied in phase by variable current throttling or steering, according to an input control value. The differential amplifiers produce an output signal with a transition spanning a time between the start of a transition on the leading input clock up to the end of the transition on the lagging input clock. The output clock is linear so long as the transitions on the two input clocks overlap. Active integrators each having an amplifier with a series resistance and capacitive feedback path are coupled to each input to the cross-coupled differential amplifiers, which enhances overlap of the input clock rise times and improves the linearity of the interpolated output signal.

Abstract: Methods and systems for precise temperature and timebase PPM error estimation using multiple timebases may comprise in an electronic device comprising a plurality of timebases and measuring a temperature corresponding to the timebases. Frequencies of the timebases at the measured temperature may be compared to determine differential error functions for the timebases. A fine reading of the temperature corresponding to the timebases may be generated based, at least in part, on the measured temperature and the determined differential error functions for the timebases. The timebases may be calibrated utilizing the generated fine reading of the temperature. The timebases may comprise different order temperature dependencies. Models of temperature dependencies of each of the timebases based may be updated, at least in part, on the fine reading of the temperature. A global navigation satellite system (GNSS) clock signal may be periodically utilized to improve the accuracy of the calibration of the timebases.

Abstract: A transmission system which couples a plurality of transmission devices to a control device includes a first transmission device which is one of the plurality of transmission devices; a first calculation circuit which calculates a first difference value indicating a frequency difference value between a common clock supplied from the control device and a first clock as a clock used in the first transmission device; and a transmitter which reports the first difference value to a second transmission device other than the first transmission device, wherein the second transmission device comprises: a second calculation circuit which calculates a second difference value indicating a frequency difference value between the common clock and a second clock used in the second transmission device, and a frequency controller which controls an oscillator generating the second clock so that the second difference value approaches the first difference value reported from the first transmission device.

Abstract: A computer system is provided which includes a plurality of nodes, which include chips of different types. In each node, one of the chips is configured as a master chip, which is connected to one or more slave chips via two or more multi-drop nets (e.g., checkstop, clockrun). The master chip and the slave chips are connected to a reference clock, and event triggering information is transmitted via the multi-drop nets (checkstop, clockrun) to the slave chips. Event trigger commands are submitted by the master chip when it receives a request, and internal offset counters are used to adjust both the receiving cycle and the cycle when the command is propagated to the units on the chips. In operation, the offset counters are synchronized by a reference clock.

Abstract: A device comprises an integrated circuit having first and second domains, the first domain having a first clock boundary module; and the second domain having a second clock boundary module. The first clock boundary module comprises: a buffer, for storing data for transfer to the second domain; and a first controller operable to send a first control signal to the second clock boundary module via a first synchronizer, the first control signal indicating the presence of a packet of data in a first storage location of the buffer. One of the first and second clock boundary modules comprises a multiplexer having an input connected to an output of the buffer and an output connected to circuitry forming part of the second domain.

Abstract: A method, computer readable medium, system and apparatus that acquires data link timing includes sequentially introducing a delay and sampling data on a link after each sequentially introduced delay. A starting edge of a valid data eye and a trailing edge of the valid data eye during the sequentially introducing the delay and the sampling of the data is determined. The sequentially introduced delay when the starting edge of the valid data eye is detected and a subsequently introduced delay when the trailing edge of the valid data eye is detected are recorded. A bit sampling time that provides the timing for the sampling of data in the valid data eye between the sequentially introduced delay and the subsequently introduced delay is determined. By way of example, an optimum bit sampling time is determined as a mean from the transition of the starting edge of the valid data eye to the trailing edge of the valid data eye. The bit sampling time for the sampling of data is applied and the link is established.

Abstract: The present disclosure relates to a method to determine a clock signal when separate clocks are used. In one embodiment, a disciplined clock system comprising an update subsystem and a synthesis subsystem is provided. A first clock phase estimate is provided to the update subsystem and used, along with the update subsystem, to determine a frequency offset estimate and a phase offset estimate. The clock signal is determining using the frequency offset estimate, the phase offset estimate, and the synthesis subsystem. Alternatively, two clocks can be synchronized by generating a signal associated with a first clock; modulating the signal; transmitting the modulated signal; receiving the modulated signal by a receiver associated with a second clock; correlating the received signal; determining the time of arrival of the received signal; determining the time difference between the two clocks; and synchronizing the two clocks.

Abstract: A communication system and method is provided herein for synchronizing a plurality of network nodes after a network lock condition occurs within a network. According to one embodiment, the method may generate a local trigger signal simultaneously at each of the plurality of network nodes by compensating for unique phase delays attributed to each of the plurality of network nodes. As described herein, the local trigger signals may be used for synchronizing devices, such as multimedia devices, which may be coupled to the network nodes. More specifically, the local trigger signals may be used to synchronize events occurring within devices, which are coupled to different nodes of the network.

Abstract: An automated portable call collection unit (APCCU) may gather information used in testing the accuracy of a wireless mobile device locating system. A GPS ground truth detector may detect the location of the APCCU based on GPS signals. A cellular GPS detector may detect GPS signals identified by a signal-identification communication from the locating system. An internal clock may keep time and synchronize its time to GPS time as announced periodically by GPS time signals. A controller may repeatedly cause a cellular network communication system to wirelessly request and receive the signal-identification communication and to send the information about the detected GPS signals, the locations, and the times. All of this may be done in a manner that insures that the accuracy of the locating system is not tested before the internal clock is first synchronized to GPS time following application of operating power to the APCCU.

Abstract: A semiconductor device includes: a DLL circuit that generates an internal clock signal based on an external clock signal; a clock dividing circuit that generates two complementary internal clock signals having different phases based on the internal clock signal; and a multiplexer that outputs two internal data signals in synchronization with the two clock signals based on internal data signals, respectively. An internal power supply voltage supplied to the clock dividing circuit and an internal power supply voltage supplied to the multiplexer are generated by respective different power supply circuits and are separated from each other in the semiconductor device. This prevents interaction among noises.

Abstract: A semiconductor device including an internal command generator and a bias generator is provided. The internal command generator generates first to fourth internal command signals sequentially enabled in synchronization with pulses of an external program signal. The first internal command signal controls a read operation for reading out data stored in memory cells, and the second and third internal command signals control a program operation for programming the memory cells. The bias generator generates a read bias signal for controlling a level of an output voltage signal, which is applied to an internal circuit, in response to the first and fourth internal command signals.

Abstract: A method of determining the downstream propagation time of signals from a USB Host Controller across one or more USB cables and one or more USB Hubs to a SuperSpeed USB device, including locking a clock of the SuperSpeed USB device to information that includes a first timestamp, transmitting a plurality of signals to the USB Host Controller, each of the signals containing a second timestamp indicative of a local time of the SuperSpeed USB device when the respective signal was generated by the SuperSpeed device; the USB Host Controller creating a third timestamp indicative of a time of reception from the SuperSpeed USB device; determining a time period from one or more respective time differences between corresponding second and third timestamps, the time period being indicative of a sum of a downstream propagation time and an upstream propagation time; and determining the downstream propagation time from the time period.

Abstract: A method for relating a data processing system with a power branch circuit is provided in the illustrative embodiments. A second signal is combined with a power signal to form a combination signal, the power signal including a first power usage by the data processing system and a second power usage by a modulating signal. The second signal is synchronized with the modulating signal in the power signal. A determination is made whether an amplitude of a frequency of the second signal is increasing in the combined signal over a period. Responsive to the determining being affirmative, the data processing system is related with the power branch circuit.

Abstract: A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses.

Abstract: Embodiments provide bus synchronization system including a source module, a plurality of destination modules, and a data alignment controller. The source module is configured to synchronize a plurality of data segments of a data bus with a source clock signal, and transmit respective synchronized data segments to individual destination modules. The source module is further configured to transmit the source clock signal to the destination modules contemporaneously with the synchronized data segments. The source module thereafter receives feedback clock signals from the individual destination modules, the feedback clock signals being delayed versions of the source clock signal. The data alignment controller adjusts an output delay time for the individual destination modules, based on the received feedback clock signals, to temporally align output signals of the destination modules.

Abstract: A computer system includes a first on-chip controller and a second on-chip controller, both connected to a control element. In normal operation, the first and second on-chip controllers operate in different clock domains. During testing, the control element causes each on-chip controller to generate a substantially similar clock signal. The substantially similar clock signals are used to test substantially similar test circuitry connected to each on-chip controller, thereby reducing overhead associated with testing. A delay may be incorporated into the path of the clock signal of one of the on-chip controllers to reduce instantaneous power draw during testing.

Abstract: In one example implementation, the present disclosure provides a system that includes circuitry and one or more electronic components for synchronizing data transfer from a core to a physical interface. One example can involve an apparatus for interfacing a digital core with at least one physical interface that includes a macro configured on the digital core, the macro having at least one data output, a first data input, a reset input and a sync reset output, the macro to be clocked by a first clock having a first clock rate. The first clock can be configured to clock in data from the digital core on the first data input; clock in a reset signal from the digital core on the reset input, wherein a synchronized reset signal is output on the sync reset output. The apparatus can also include physical interface circuitry and a reset sampling input.

Abstract: Serial peripheral interfaces and methods of operating the same are provided. An apparatus can have a serial peripheral interface (SPI) including a first command state machine (CSM), and a second CSM.

Abstract: Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving an out-of-synchronization indication associated with at least one of the channels. The memory control unit performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period.

Abstract: A system and apparatus that include a selectable synchronizer circuit for synchronizing data across asynchronous boundaries are disclosed. The apparatus includes a unit associated with a first clock domain and a synchronizer sub-unit (SSU) coupled to the unit and associated with a second clock domain. The synchronizer sub-unit includes two or more synchronizers and selector logic configured to select one output of the two or more synchronizers.

Abstract: An apparatus including a JTAG interface, synchronous bus optimizer, core clocks generator, synchronous strobe driver, and a DLL. The JTAG interface receives control information indicating a first amount to advance a synchronous data strobe associated with a first data group and a second amount to delay a data bit signal associated with a second data group. The synchronous bus optimizer receives the control information, and develops a first value on a first ratio bus that indicates the first amount and a second value on a second ratio bus that indicates the second amount. The core clocks generator advances a data strobe clock by the first amount. The synchronous strobe driver employs the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the first amount. The DLL generates a delayed data bit signal, delayed by the second amount.

Abstract: A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.

Abstract: A Delay-tolerant Asynchronous Interface (DANI) is typically used to make the clock domains for reusable silicon intellectual property (IP) cores completely independent of each other. In fact, a DANI-wrapped IP core usually appears to its environment as if it were clockless. This property is necessary to address the variability in data transmission-time between source and destination. This variability is a result of increased lack of predictability in today's leading-edge manufacturing processes. A DANI wrapper can be applied to the IP core that is the source of data to be transmitted or it can be applied to the IP core that is the destination of that data. The transmission time over the route between source and destination may vary more than a single clock period.

Abstract: A frequency tracking circuit is disclosed. The frequency tracking circuit includes an edge selector, a phase-frequency processor and a digital controlled oscillator. The edge selector receives a data signal and feedback clock signal and sequentially outputs a data edge signal and a feedback-clock-edge signal. The phase-frequency processor receives the data edge signal and the feedback-clock-edge signal and outputs a frequency adjusting digital signal after executing differential operation according to a first phase difference and a second phase difference. The digital controlled oscillator receives the frequency adjusting digital signal so as to adjust frequency of the feedback clock signal. The phase-frequency processor outputs a frequency tracking signal to the edge selector, wherein the edge selector utilizes the frequency tracking signal for acquiring the data edge signal and utilizes the data edge signal for acquiring the feedback-clock-edge signal.

Abstract: A apparatus is provided for buffering data between a memory controller and a DRAM. The apparatus includes a phase locked loop (PLL), a phase interpolator for aligning a phase of an output clock signal in response to a phase aligning control word, and a non-volatile storage location permanently storing the phase aligning control word. The phase aligning control word is determined through an initial training procedure of the device under predetermined training conditions of at least a supply voltage level and a temperature, and the predetermined training conditions are set so as to optimize the phase alignment of an edge of the output clock signal with respect to the buffered data signal.

Abstract: A multiple time domain synchronizer includes a data pipeline containing a plurality of serially-connected delay elements therein. A latency selection circuit is provided, which has a plurality of inputs electrically coupled to outputs of a corresponding plurality of delay elements in the data pipeline. The latency selection circuit is configured to pass a data pipeline signal from an output of a selected one of the plurality of delay elements in response to a latency control signal. A synchronization circuit is provided, which is electrically coupled to an output of the latency selection circuit. This synchronization circuit, which includes first and second unequal timing paths therein, is responsive to a clock that synchronizes capture of the data pipeline signal selected by the latency selection circuit and a destination code that selects one of the first and second unequal timing paths to be traversed by the captured data pipeline signal as active.

Abstract: Embodiments of a multi-processor system and method for synchronization and event scheduling of multiple processing elements are generally described herein. In some embodiments, timing marks are provided to the processing elements and a start-timer command is broadcasted to the processing elements after an initial timing mark. The start-timer command instructs the processing elements to initiate an internal time reference after receipt of a next timing mark. Each of the processing elements maintains a copy of the internal time reference which may be used for synchronized event scheduling.

Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Abstract: Apparatus and method for clock edge synchronization among a plurality of devices. One of the plurality of devices is designated as a master device and one or more remaining devices as slave devices. The master device is configured for providing one or more gated master output clock signals based on a synchronization input signal and an input clock signal. The master device may be further configured to generate one or more gated master clock outputs to drive one or more slave devices, or to provide one or more slave synchronous master clock outputs. The one or more slave devices are configured for producing one or more slave output clock signals, based on the synchronization input signal and corresponding one or more gated master output clock signals. The one or more slave output clock signals are clock edge synchronized.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for the active training of memory command timing. In some embodiments, the CMD/CTL timing is actively trained using active feedback between memory modules and the memory controller. Other embodiments are described and claimed.

Abstract: A method of synchronising a compound SuperSpeed USB device, comprising: providing data communication between a host computing device and the compound SuperSpeed USB device across the SuperSpeed USB communication channel; establishing a SuperSpeed USB communication channel to a SuperSpeed USB function of the compound USB device; establishing a non-SuperSpeed synchronisation channel to a non-SuperSpeed USB function of the compound USB device; and synchronising a local clock of the compound USB device to a periodic data structure within a data stream in the non-SuperSpeed synchronisation channel so that the local clock can enable synchronous operation of the compound USB device with one or more comparable USB devices.

Abstract: A method and a device for generating a clock signal determine a number of pulses to be discarded from each predetermined cycle of a reference clock signal in order to obtain, on average, a target frequency. A masking pattern is created for discarding the number of pulses to be discarded from each predetermined cycle of the reference clock signal. The clock signal, which includes the target frequency, is generated by discarding the number of pulses from the reference clock signal using the masking pattern.

Abstract: A device for controlling a clock signal generator includes a processor (101) for forming at least two mutually different control quantities on the basis of reception moments of timing messages such as time stamps, where the reception moments are expressed as time values based on a first clock signal and the timing messages are transmitted in accordance with a second clock signal. The processor also calculates a weighted sum of the control quantities, and controls the clock signal generator with the weighted sum so as to synchronize the first clock signal and the second clock signal. The control quantities may represent, for example, a filtered value of observed phase-errors, a phase-error corresponding to a minimum observed transfer delay, and phase-errors corresponding to a given portion of the delay distribution. Using the weighted sum of the mutually different control quantities improves the utilization of the information content of the timing messages.

Abstract: Integrated circuits having single-port memory elements may be provided. The single-port memory elements may be controlled using a control circuit to emulate multiport functionality. In one suitable embodiment, the control circuit may be an arbitration circuit configured to execute a memory request as soon as it is received by the arbitration circuit. Requests received while a current memory access is being performed may be put on hold until the current memory access has been completed. In another suitable embodiment, the control circuit may be a sequencing circuit configured to service memory access requests from a synchronous port and an asynchronous port. Memory access requests received at the synchronous port may be serviced immediately, whereas memory access requests received at the asynchronous port may be synchronized to an internal memory clock signal and may be serviced after a preceding memory access request associated with the synchronous port has been serviced.

Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.

Abstract: Disclosed is an image processing apparatus, which can differently set a clock ratio according to a use rate of a CPU, and a control method thereof. The image processing apparatus may include a receiver to receive a print command from a user terminal, and a controller to differently set a clock ratio according to a use rate of the CPU based on the print command.

Abstract: A clock frequency controller for a processor and a method of operation thereof. The clock frequency controller may be embodied in a processor, including: (1) a processing core operable at a clock frequency to undertake a processing of a graphics application, and (2) a clock frequency controller coupled to the processing core and operable to adjust the clock frequency based on a current frame rate of the processing and a target frame rate for the processing.

Abstract: A memory controlling device that includes a request generating section for generating a memory request, a row selecting information retaining section that retains data relative to row address information, a column selecting information retaining section that retains data relative to column address information, a memory bank information for managing section operation states of the memory device, a command generating section for generating operation commands, and a command aligning section that synchronizes the operation commands with the clock.

Abstract: A method for restoring stability to an unstable bus includes cycling a clock of the bus a number of times, transmitting a stop bit, cycling a clock line of the bus at least one time and transmitting a stop bit immediately after an acknowledgment bit has been received by a bus master.

Abstract: Methods and apparatus are provided for digital linearization of an analog phase interpolator. Up to 2N desired phase values are mapped to a corresponding M bit value, where M is greater than N. A corresponding M bit value is applied to the phase interpolator to obtain a desired one of the 2N desired phase values. A linearized phase interpolator is also provided that accounts for process, voltage, temperature or aging (PVTA) variations.

Abstract: A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.), and any configurable element can have access to a configuration register and a status register of the other configurable elements via an interconnection architecture and can thus have an active influence on their function and operation. By making synchronization the responsibility of each element, more synchronization tasks can be performed at the same time because independent elements no longer interfere with each other in accessing a central synchronization instance.

Abstract: A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.), and any configurable element can have access to a configuration register and a status register of the other configurable elements via an interconnection architecture and can thus have an active influence on their function and operation. By making synchronization the responsibility of each element, more synchronization tasks can be performed at the same time because independent elements no longer interfere with each other in accessing a central synchronization instance.