Abstract: Technologies related to secure system time reporting are generally described. In some examples, responses to some system time requests may be manipulated to prevent leaking information that may be of interest for timing attacks, while responses to other system time requests need not be manipulated. In particular, responses to system time requests that are separated from a previous system time request by a predetermined minimum value, or less, may be manipulated. Responses to system time requests that are separated from a previous system time request by more than the predetermined minimum value need not be manipulated. Furthermore, secure system time reporting may be adaptively deployed to servers in a data center on an as-needed basis.

Abstract: A method and a device for synchronizing broadcast of streaming data by a transmitting data processing unit to a plurality of receiving data processing units is provided. After a data word has been sent, a synchronizer in the transmitting data processing unit collects an acknowledge signal from each of the receiving data processing units and then generates an indication that the next data word can be transmitted. This allows to speed-up data delivery to parallel working processing units in a system-on-a-chip since data delivery has no longer to account for a maximum predictable latency of the respective receiving units.

Abstract: A semiconductor apparatus includes a control chip including a first selection unit configured to output one of signals which are inputted through a first normal port and a shared test port, in response to a test mode signal; and a second selection unit configured to output one of signals which are inputted through a second normal port and the shared test port, in response to the test mode signal, wherein the control chip is configured to transmit an output of the first selection unit to a first chip and transmit an output of the second selection unit to a second chip.

Abstract: Preamble release training in a double data-rate dynamic random access memory interface uses feedback from read operations to adjust the preamble release signal so that the preamble release signal continues to be activated close to the middle of the preamble. A first signal, and then a second signal, are generated in response to an initiation of a read operation. The first and second signals are characterized by a delay from the initiation of the read operation of one or more clock cycles plus a fine delay contributed by an adjustable delay circuit. The first signal is provided to a data strobe parking circuit that uses it to release or un-park the data strobe signal lines. The second signal is phase-compared with the data strobe signal associated with incoming data during the read operation. The adjustable delay circuit is adjusted in response to the result of the comparison.

Abstract: The present disclosure relates to a method to determine the phase of a signal when transmitter and receiver circuits use separate clocks. A discrepancy between the separate clocks is determined, as is a correction factor between the separate clocks. The phase is determined using a measured time of arrival of the signal, the determined discrepancy, and the determined correction factor. A drift factor and an expected start time of a pulse sequence may be used to determine the discrepancy. A start time of a pulse within the pulse sequence is determined and used to determine the correction factor. The method works by either absolute synchronization of the separate clocks, or by making the measurements independent of clock synchronization.

Abstract: A circuit and method of analog data acquisition synchronization from an analog sensor in multiple channels associated with a USB hub. An analog to digital converter connected to the sensor that is part of a USB device has a time and phase corrected sampling clock that is referenced to a start-of-frame traffic signal with a preconfigured message indicating a time offset or delay seen upstream through a USB port. A plurality of similar devices are autonomously synchronized by the same message for multi-channel data acquisition by a locally generated trigger signal that allows a preset amount of delay set by the message. An accelerometer is a preferred sensor for such multi-channel data acquisition.

Abstract: Systems and methods for dynamic development and deployment of computing applications including a development framework, a visual design subsystem, and a deployment subsystem, where at runtime the deployment subsystem is operable to dynamically deploy a computing application by sending a request at runtime for graphs and components identified in the computing application.

Abstract: A communications network includes multiple distributed nodes that are coupled by a circuit-switched network. To improve efficiency, a plurality of the nodes are associated with a single source synchronization block that injects timing messages over circuits in the circuit-switched network to the plurality of nodes. Each of the plurality of nodes is associated with a timing extraction and recovery block that extracts information from the timing messages injected by the source synchronization block to synchronize a local clock in each node to the frequency and phase of a clock received by the source synchronization block.

Abstract: A method comprises determining a plurality of time intervals Tp and Tn within a variable bit rate (VBR) representation of an image sequence. The time intervals Tp are those in which a number of blocks of information per unit time is greater than a baseline value. The time intervals Tn are those in which a number of blocks of information per unit time is less than the baseline value. A second representation of the image sequence is created in which some blocks of information Bp are removed from the time intervals Tp and interlaced with blocks of information Bn in the time intervals Tn to reduce a variation in a number of blocks of information per unit time between the time intervals Tp and Tn.

Abstract: Embodiments relate to a dual asynchronous and synchronous memory system. One aspect is a system that includes a memory controller and a memory buffer chip coupled to the memory controller via a synchronous channel. The memory buffer chip includes a memory buffer unit configured to synchronously communicate with the memory controller in a nest domain, and a memory buffer adaptor configured to communicate with at least one memory interface port in a memory domain. The at least one memory interface port is operable to access at least one memory device. A boundary layer is connected to the nest domain and the memory domain, where the boundary layer is configurable to operate in a synchronous transfer mode between the nest and memory domains and to operate in an asynchronous transfer mode between the nest and memory domains.

Abstract: The present invention may provide a system with a fixed clock to provide a fixed clock signal, and a variable clock to provide a variable clock signal. The system may also include a chipset with a chipset time stamp counter (TSC) based on the fixed clock signal. A processor may include a fast counter that may be based on the variable clock signal and generate a fast count value. A slow counter may download a time stamp value based on the chipset TSC at wakeup. The slow counter may be based on the fixed clock signal and may generate a slow count value. A central TSC may combine the fast count and slow count value to generate a central TSC value.

Abstract: Apparatus and methods are provided for the measurement of a power factor at points of interest, such as circuit breakers, machines, and the like. Accordingly, means are provided for measurement of a power factor for each electrical sub-network that is controlled by a circuit breaker. Each apparatus is enabled to communicate its respective data, in an environment of a plurality of such apparatuses, to a management unit which is enabled to provide finer granularity power factor profiles.

Abstract: Avoiding long access latencies in redundant storage systems is disclosed, including: determining a first device associated with a request is in a slow access period; and reconstructing data associated with the request from one or more other devices comprising a redundant storage system in which the first device and the one or more other devices are included.

Abstract: TV software can be updated by receiving updated from a USB drive or wirelessly, in either case preferably over a synchronous bus for speedier data transfer.

Abstract: Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.

Abstract: One or more transactions, and their audited update actions, operating on a database may be identified by a step ID. The step ID may include a first set of bits identifying a time the step was created. The step ID may also include a second set of bits uniquely identifying a step created at a certain time from other step created at the same time. The first set of bits may be generated from a coordinated universal time (UTC) that does not change with local seasons, such as daylight saving time.

Abstract: A system and method for adaptively verifying data in resource constrain systems. The adaptive data verification mechanism employs the proper mode of verification adaptively to balance cost/performance requirements plus security requirements. The algorithm uses a belief level for the validity of a received message, and assigns the belief level to a scale between a bona fide message at one end of the scale and a malicious message at an opposite end of the scale. Depending where on the scale the belief level falls determines which validation mode will be used to authenticate the message. In an alternate embodiment, the belief level relative to a scale and the amount of data waiting to be processed in a buffer are both used to determine which mode will be used to validate the message.

Abstract: A method for compensating a timing signal with which an outputting of data states of at least one data signal is synchronised. The method comprises receiving a current set of data states and a next set of data states, identifying state transitions between the current set of data states and the next set of data states determining an amount of compensation to apply to the timing signal based at least partly on the state transitions identified between the current set of data states and the next set of data states, and applying the determined amount of compensation to the timing signal such that the compensation applies to the outputting of the next set of data states.

Abstract: Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.

Abstract: Disclosed herein is a method, a computer program product, and a carrier for indicating one-way latency in a data network (N) between a first node (A) and a second node (B), wherein the data network (N) lacks continuous clock synchronization, comprising: a pre-synchronisation step, a measuring step, a post-synchronisation step, an interpolation step, and generating a latency profile. The present invention also relates to a computer program product incorporating the method, a carrier comprising the computer program product, and a method for indicating server functionality based on the first aspect.

Abstract: Dual-structure clock tree synthesis (CTS) is described. Some embodiments can construct a set of upper-level clock trees, wherein each leaf of each upper-level clock tree is a root of a lower-level clock tree. Each upper-level clock tree can be optimized to reduce an impact of on-chip-variation and/or cross-corner variation on clock skew. Next, for each leaf of each upper-level clock tree, the embodiments can construct a lower-level clock tree to distribute a clock signal from the leaf of the upper-level clock tree to a set of clock sinks. The lower-level clock tree can be optimized to reduce latency, power consumption, and/or area.

Abstract: Audio and video signals are synchronized for pleasing presentation of content. As content is streamed to a device, an audio portion may lag or lead a video portion. Spoken words, for example, are out of synch with the lip movements. Video time stamps are synchronized to audio time stamps to ensure streaming content is pleasing.

Abstract: A medical information processing and storage system includes a medical images database storing medical images and metadata relevant to the medical images. A processor is configured to perform post-acquisition image processing on medical images. A medical images archiver is configured to store a medical image in the medical images database after the medical image has been processed by the processor. The medical images archiver stores the medical image in the database with processing-descriptive metadata that is descriptive of the post-acquisition image processing performed on the medical image by the processor.

Abstract: An integrated-circuit memory controller outputs to a memory device a first signal in a first state to enable operation of synchronous data transmission and reception circuits within the memory device. A transaction queue within the memory controller stores memory read and write requests that, to be serviced, require operation of the synchronous data transmission and reception circuits, respectively, within the memory device. Power control circuitry within the memory controller determines that the transaction queue has reached a predetermined state and, in response, outputs the first signal to the memory device in a second state to disable operation of the synchronous data transmission and reception circuits within the memory device.

Abstract: In one example implementation, the present disclosure provides a system that includes circuitry and one or more electronic components for synchronizing data transfer from a core to a physical interface. One example can involve an apparatus for interfacing a digital core with at least one physical interface that includes a macro configured on the digital core, the macro having at least one data output, a first data input, a reset input and a sync reset output, the macro to be clocked by a first clock having a first clock rate. The first clock can be configured to clock in data from the digital core on the first data input; clock in a reset signal from the digital core on the reset input, wherein a synchronized reset signal is output on the sync reset output. The apparatus can also include physical interface circuitry and a reset sampling input.

Abstract: An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.

Abstract: Methods and systems for managing data loads on a cluster of processors that implement an iterative procedure through parallel processing of data for the procedure are disclosed. One method includes monitoring, for at least one iteration of the procedure, completion times of a plurality of different processing phases that are undergone by each of the processors in a given iteration. The method further includes determining whether a load imbalance factor threshold is exceeded in the given iteration based on the completion times for the given iteration. In addition, the data is repartitioned by reassigning the data to the processors based on predicted dependencies between assigned data units of the data and completion times of a plurality of the processers for at least two of the phases. Further, the parallel processing is implemented on the cluster of processors in accordance with the reassignment.

Abstract: Network system being configured to execute I/O commands and application commands in parallel and comprising a network and at least one network node, wherein the at least one network node is connected to the network via a network adapter and is configured to run several processes and/or threads in parallel, wherein the at least one network node comprises or is configured to establish a common communication channel (C-channel) to be used by the several processes and/or threads for data communication with the network via the network adapter, wherein the C-channel comprises or is established to comprise a work queue (WQ) for execution of I/O commands and a completion queue (CQ) for indication of a status of I/O commands, and wherein the at least one network node, especially its comprised or to be established C-channel, is configured for an exclusive access of precisely one single process or thread out of the several processes and/or threads to the CQ of the C-channel at a particular time.

Abstract: There is provided an information processing apparatus including a virtual clock controller configured to update a first virtual clock on the basis of a system clock, and a synchronization part configured to perform given data synchronization processing with another information processing apparatus on the basis of the first virtual clock and a second virtual clock that is updated by the another information processing apparatus.

Abstract: A synchronization apparatus between an AVN system and a digital clock of a vehicle may include: a clock driving unit configured to transmit a clock information signal; a microcomputer configured to analyze the clock information signal when the clock information signal is received from the clock driving unit, update clock information according to the analysis result, and transmit the updated clock information to an external clock module; and the external clock module configured to display the clock information transmitted from the microcomputer.

Abstract: Aspects of the invention are related to a method for synchronizing a first sensor clock of a first sensor. The exemplary method comprises: correcting the first sensor clock for a first time, transferring data from the first sensor, and correcting the first sensor clock for a second time, wherein a time interval between two corrections of the first sensor clock is selected such that the first sensor clock is sufficiently aligned with a processor clock of a processor over the time interval.

Abstract: A method for improving accuracy of simple network time protocol. A time inquiry is sent from at least one device in a substation to a time provider. A message including a reference time is received from the time provider. An accuracy of the reference time is evaluated. If the accuracy of the reference time is less than a threshold value the accuracy of the reference time is improved. The reference time is utilized for synchronization.

Abstract: Described are embodiments of methods, apparatuses, and systems for time synchronization of a multi-protocol I/O interconnect of computer apparatus. A method for synchronizing time across the multi-protocol I/O interconnect may include providing a first local time of a first switch of a switching fabric of a multi-protocol interconnect to a second switch of the switching fabric, and adjusting a second local time of the second switch to the first local time. Other embodiments may be described and claimed.

Abstract: By causing information processing apparatuses belonging to a same group to be in a same state and transmitting operation information received from an input unit to the information processing apparatuses belonging to the same group simultaneously or approximately simultaneously, the operations of the information processing apparatuses belonging to the same group are synchronized with each other, and operation results received from the synchronized information processing apparatuses belonging to the same group are output by an output unit. In this way, the plurality of grouped information processing apparatuses can be simultaneously operated.

Abstract: A network node of a synchronous network, wherein said network node comprises a timing circuit which recovers a reference clock from a reception signal received by said network node from an upstream network node of said synchronous network and uses the recovered reference clock for a transmission signal transmitted by said network node to a downstream network node of said synchronous network; and a clock stability monitoring circuit which monitors internal control parameters (CP) of said timing circuit to detect an instability of the reference clock distributed within said synchronous network.

Abstract: A synchronization infrastructure that synchronizes data stored between components in a cloud infrastructure system is described. A first component in the cloud infrastructure system may store subscription information related to a subscription order which may in turn be utilized by a second component in the cloud infrastructure system to orchestrate the provisioning of services and resources for the order placed by the customer. The synchronization architecture utilizes transactionally consistent checkpoints that describe the state of the data stored in the components to synchronize the data between these components.

Abstract: A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin.

Abstract: In an information processing apparatus, a control unit includes a first clock device for providing the time of day. A physical domain includes a second clock device, and implements a logical domain that functions as a virtual information processing apparatus. The control unit controls a first time-of-day difference between the time of day of the first clock device and that of the second clock device. The physical domain controls a second time-of-day difference between the time of day of the second clock device and that of the logical domain. In the information processing apparatus, the time of day on the logical domain is controlled based on the first and second time-of-day differences.

Abstract: A scan driver includes a plurality of stages arranged sequentially and configured to respectively output a scan signal; and a switching unit configured to receive a plurality of clock signals, to select clock signals of the plurality of clock signals according to a selection control signal, and to input the selected clock signals to the plurality of stages.

Abstract: A method for synchronizing a plurality of components that are networked via a plurality of high speed switches, the method includes frequency-locking to a master clock component clocks of the plurality of components, and synchronizing to a master counter, driven by the master clock, component counters of the plurality of components, so that the frequency-locked component clocks drive the component counters in synchrony with the master counter.

Abstract: A semiconductor integrated circuit includes a system bus configured to operate at a first clock, a plurality of arithmetic processing units including a first arithmetic processing unit which is connected to the system bus and operates at a second clock, and a control circuit controlling the system bus and the arithmetic processing units. After checking that an access from the arithmetic processing units to the system bus is not generated, the control circuit changes frequency of the first clock or the second clock.

Abstract: A system and method to synchronize distributed measurements in a borehole are described. The system includes a plurality of wired segments coupled together by couplers and a plurality of nodes configured to measure, process, or relay information obtained in the borehole to a surface processing system, each of the plurality of nodes comprising a local clock and being disposed at one of the couplers or between couplers. The system also includes a surface processing system coupled to a master clock and configured to determine a time offset between the master clock and the local clock of an nth node among the plurality of nodes based on a downhole generated synchronization signal.

Abstract: Devices and methods for synchronizing devices over a switched fabric. A switch receives a request packet from a device, transmits a completion packet to the device, determines an in-switch delay, and stores the in-switch delay. Another switch receives a packet from a first device, forwards the packet to a second device, determines an in-switch delay of the packet, and stores the in-switch delay. Storing of in-switch delays may include adding an in-switch delay to values in one or more transaction delay fields of a packet. Storing of in-switch delays may include storing the delays in a storage element of a switch. In-switch delay may be determined as a difference between a receiving time corresponding to reception of a packet and a forwarding or transmittal time corresponding to forwarding or transmitting of a packet.

Abstract: A reference frequency setting method of a flash memory storage apparatus is provided. The flash memory storage apparatus includes a flash memory module, a storage unit, and an oscillator circuit without a crystal. The reference frequency setting method includes following steps. Whether a setting code is stored in the flash memory module or the storage unit is determined, wherein the setting code includes information of a reference frequency. If the setting code is stored in the flash memory module, the setting code is read to allow the oscillator circuit to generate the reference frequency according to the setting code. A memory controller and a flash memory storage apparatus using the reference frequency setting method are also provided.

Abstract: There are provided methods and apparatus for audio and video synchronization timestamp rollover correction. A synchronization apparatus includes a synchronizer for providing synchronization information for synchronizing a video stream with an audio stream during any point in a broadcast thereof irrespective of whether the video stream and the audio stream have different rollover points for their respective timestamps. The synchronization information is encoded for an out of band transmission with respect to the broadcast of the audio and video streams.

Abstract: A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.

Abstract: An HTTP-based synchronization method includes obtaining a first response sent by a source server or a cache in response to an HTTP request for obtaining a file; determining time when the first response is sent in local time at server, according to a value of a Date field and a value of an Age field in the first response; determining time when the first response is sent in local time at client, according to the client time of an event related to the first response; and determining time offset between the server time and the client time according to the time when the first response is sent in local time at server and the time when the first response is sent in local time at client, and setting up a synchronization relationship between the client time and the server time.

Abstract: A memory device is provided. The memory device includes a preamble disable memory and a memory controller. The preamble disable memory is arranged to store preamble disable data. The preamble disable data includes an indication as to whether a read preamble should be enabled or disabled. In response to a read command, if the preamble disable data includes an indication that the read preamble should be enabled, the memory controller provides the read preamble. Alternatively, in response to the read command, if the preamble disable data includes an indication that the read preamble should be disabled, the memory controller disables the read preamble.

Abstract: A system includes a memory controller and a plurality of memory devices that are connected in-series to the memory controller. The system operation is synchronous with clock that is provided in a fashion of source synchronous clock structure. The source synchronous clock structure includes a PLL (Phase-Locked Loop) that reshapes an incoming clock and a reshaped clock is provided. The PLL provides a shifted clock in phase of 90°. The phase-shifted clock and data are transmitted from the first device to the second device. Clock phase shift provides a center-edge clock with data to be transmitted. The devices are assigned with unique IDs. The least significant bit of the ID number of the last device is used for determination of clock alignment: edge- or center-aligned clock with data produced by the memory controller.

Abstract: Command paths, apparatuses, and methods for providing a command to a data block are described. In an example command path, a command receiver is configured to receive a command and a command buffer is coupled to the command receiver and configured to receive the command and provide a buffered command. A command block is coupled to the command buffer to receive the buffered command. The command block is configured to provide the buffered command responsive to a clock signal and is further configured to add a delay before to the buffered command, the delay based at least in part on a shift count. A command tree is coupled to the command block to receive the buffered command and configured to distribute the buffered command to a data block.