Abstract: A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.

Abstract: An integrated-circuit memory controller outputs to a memory device a first signal in a first state to enable operation of synchronous data transmission and reception circuits within the memory device. A transaction queue within the memory controller stores memory read and write requests that, to be serviced, require operation of the synchronous data transmission and reception circuits, respectively, within the memory device. Power control circuitry within the memory controller determines that the transaction queue has reached a predetermined state and, in response, outputs the first signal to the memory device in a second state to disable operation of the synchronous data transmission and reception circuits within the memory device.

Abstract: A computer-implemented method is presented for synchronizing time between two handheld medical devices that interoperate with each other. The method includes: determining a first time as measured by a first clock residing in the first medical device; determining a second time as measured by a second clock residing in a second medical device; evaluating whether the first clock is synchronized with the second clock; determining whether at least one of the first clock and the second clock was set manually by a user; and setting time of the first clock in accordance with the second time when the second clock was set manually by the user.

Abstract: A system and method for efficiently synchronizing multiple processing cores on a system-on-a-chip (SOC). A SOC includes an interrupt controller and multiple processing cores. The interrupt controller includes a main time base counter. The SOC includes multiple local time base counters, each coupled to a respective one of the processing cores. Synchronization logic blocks are used to update the local counters. These blocks receive a subset of bits from the interrupt controller. The subset of bits represents a number of least significant bits of the main counter less than a total number of bits for the main counter. The logic blocks update an associated local counter according to changes to the received subset of bits. A difference may exist between values of the main counter in the interrupt controller and the local counter in the processing core. However, this difference may be a constant value.

Abstract: A system for transferring data between asynchronous domains in an SOC includes a slave request generation and data latch circuit, a busy signal generator, a positive edge detector, and a cascaded synchronizer. A host device transmits a host request signal and host data to the slave request generation and data latch circuit for execution by a slave device, which operates at a different frequency than the host device. The slave request generation and data latch circuit stores the host data and transmits it to the slave device based on a synchronized slave clock signal. The host device can perform other tasks while the slave device executes the host request.

Abstract: Discrete time compensation mechanisms include a channel component configured for determining which channel of a plurality of channels to process time slots of sampled data that are time stamped in a discrete time and processing the time slots of the sampled data to the plurality of channels. A common channel clock component is configured for time stamping the time slots of the sampled data in the discrete time domain that is faster than a non-discrete reference time stamp of continuous data from which the time slots are sampled from and for processing the sampled data through the plurality of channels faster than the continuous data is being received. Compensations for one or more gaps are generated based on a set of predetermined criteria and a corrected time stamp is applied to the sampled data for processing among different processing channels.

Abstract: An apparatus may include: first circuitry configured to operate at a first frequency; second circuitry configured to operate at a second frequency that is different from the first frequency, where the second circuitry is for receiving input from, and for providing output to, the first circuitry; and logic that bridges the first circuitry and the second circuitry. The logic to enables the second circuitry to appear to run an integer number of cycles of the first frequency, and operates by receiving first signals at the first frequency and generating second signals at the second frequency, where the second signals are for triggering operations performed by the second circuitry. The apparatus may also include an output buffer circuit bridging the first circuitry and the second circuitry.

Abstract: A master device and slave devices are connected with each other through an SDA and an SCL, and at least one of a serial communication data signal communicated through the SDA and a serial communication clock signal communicated through the SCL is latched with use of a noise removal clock signal whose frequency is higher than that of the serial communication clock signal, and is taken in.

Abstract: Implementations of the present disclosure involve an apparatus and/or method for synchronizing at least one newly activated processor with at least one previously running processor. Each processor is configured to generate a heartbeat and operate according to a STICK. When a previously deactivated processor is added, the heartbeat of each active processor is reset and the current STICK is transmitted to the newly activated processor on the next heartbeat. The newly activated processor may then add the heartbeat period to the acquired STICK and begin incrementing the STICK and normal operation after the next heartbeat.

Abstract: Systems, methods, and computer-readable storage media for adding video to an audio only communication session. During a communication session between a first device and a second device, the first device receives an audio portion of the communication session from a user. The first device then receives, via a wireless connection, a video portion of the communication session from a third device. The first device synchronizes the audio portion of the communication session and the video portion of the communication session to yield a synchronized audio and video portion of the communication session. Next, the first device sends the synchronized audio and video portion of the communication session to the second device.

Abstract: A thermal protection method for a computer system including at least a processor includes monitoring the temperature and loading of the processor via a system firmware in the computer system, obtaining the current performance state level and at least an operable performance state levels of the processor when the system firmware determines that the temperature and loading of the processor exceeds a predetermined value respectively, wherein the performance state level is associated to the frequency of the processor, and setting the processor to one of the operable performance state levels, wherein the frequency of the performance state level is lower than the frequency of the current performance state level, according to the current performance state level and the operable performance state levels.

Abstract: The disclosure provides a technique of enabling to appropriately confirm the state of a partner apparatus in high-speed serial communication. An information processing apparatus includes a master and a slave which is connected with the master by a plurality of signal lines. The master and the slave are configured to perform a handshake by changing a signal level of a respective data signal line for a period of time longer than a cycle of a clock each other.

Abstract: Presented herein are systems, methods, and computer-readable media for recording event times in particle detection scenarios. The systems, methods, and computer-readable media involve the identification of one facility device as a grandmaster clock among at least two facility devices of a facility device set, where the respective facility devices are selected from a facility device type set including a beam monitor; a neutron instrument; a neutron chopper; a nuclear reactor; a particle accelerator; a network router; and a user workstation. The system, method, and computer-readable medium also involve configuring the facility devices to synchronize a clock component with the grandmaster clock; and, upon detecting an event, retrieve from the clock component of the selected facility device an absolute event timestamp that is independent of event times of other events, and store a record of the facility event and the absolute event timestamp in the data store.

Abstract: An electronic timekeeping circuit and a method for operating an electronic timekeeping circuit are described. In one embodiment, an electronic timekeeping circuit includes power supplies and timekeeping circuit components that are grouped into power supply domains. Power is supplied to each of the power supply domains by a corresponding one of the power supplies. Timekeeping registers are duplicated for each of the power supply domains. The timekeeping registers are synchronized between the power supply domains if one of the timekeeping registers is modified or if one of the power supplies is turned off and subsequently turned back on. Other embodiments are also described.

Abstract: A data processing unit has a time information provider for processing a clock or a strobe signal, configured to provide a digitized clock or strobe time information on the basis of the clock or strobe signal and at least one data extraction unit, coupled to the time information provider and configured to select data from a sequence of data samples of a data signal depending on the digitized clock or strobe time information.

Abstract: In one embodiment, a microprocessor includes one or more processing cores. At least one processing core includes a clock shaping circuit that is configured to receive a clock input signal. The clock shaping circuit includes rising edge skew logic that is configured to selectively delay a rising edge of the clock input signal and falling edge skew logic that is configured to selectively delay a falling edge of the clock input signal independent of adjustment of the rising edge.

Abstract: A computer system encompasses a processor (11) including a control unit (111) and an ALU (112) configured to execute arithmetic and logic operations synchronized with the clock signal, and a marching main memory (31), which embraces an array of memory units, configured to store information in each of memory units and to transfer synchronously with the clock signal, providing the processor (11) with the stored information actively and sequentially so that the ALU (112) can execute the arithmetic and logic operations with the stored information. The results of the processing in the ALU (112) are sent out to the marching main memory (31), but there is only one way of instructions flow from the marching main memory (31) to the processor.

Abstract: Disclosed herein is a signal processing apparatus including: an input block receiving the predetermined number of items of data and a first enable signal taking an active state in an interval where data is valid in synchronization with a first clock; a count block counting the number of clocks in an interval where the first enable signal is inactive; an enable signal control block putting a second enable signal in an active state for the number of clocks equal to a predetermined number and putting the second enable signal in an inactive state for the number of clocks counted by the count block; an enable signal output block outputting the second enable signal; and a data output block outputting the predetermined number of items of data in synchronization with the second clock in an interval where the second enable signal is active.

Abstract: A system and method for synchronizing clocks across a packet-switched network eliminates wander accumulation to enable precision clock distribution across a large network. In addition to standard Precision Time Protocol (PTP) synchronization messages or similar time synchronization messages, each clock regenerator stage receives a grand clock error message from the previous stage, updates this error message with its own stage clock error, and then transmits the updated grand clock error to the next stage. This enables the synchronization algorithm to compensate for the error of the previous stage, effectively locking each clock regenerator stage to the grand master clock directly.

Abstract: Provided is a clock data recovery circuit including a phase-frequency detector configured to detect a frequency and phase of a reference clock signal and control a frequency and phase of an internal clock signal based on the detected frequency, a frequency detector configured to detect a frequency of a data signal and, based on the detected frequency of the data signal, adjust the frequency of the internal clock signal; and a phase detector configured to detect a phase of the data signal based on the detected frequency of the data signal and adjust the phase of the internal clock signal. Accordingly, a timing controller that includes the clock data recovery circuit is capable of establishing data communication at high speeds when the system is powered on/off to reduce power consumption. Also, the timing controller does not need to include an additional external clock generation device, and is capable of achieving frequency synchronization using a non-precision clock signal generated in the timing controller.

Abstract: Synchronizing time bases in a parallel computer that includes compute nodes organized for data communications in a tree network, where one compute node is designated as a root, and, for each compute node: calculating data transmission latency from the root to the compute node; configuring a thread as a pulse waiter; initializing a wakeup unit; and performing a local barrier operation; upon each node completing the local barrier operation, entering, by all compute nodes, a global barrier operation; upon all nodes entering the global barrier operation, sending, to all the compute nodes, a pulse signal; and for each compute node upon receiving the pulse signal: waking, by the wakeup unit, the pulse waiter; setting a time base for the compute node equal to the data transmission latency between the root node and the compute node; and exiting the global barrier operation.

Abstract: A synchronization apparatus, comprising: a USB device having a USB microcontroller, circuitry for observing USB traffic, and circuitry for decoding from a USB data stream a periodic data structure (such as a clock carrier signal) containing information about a distributed clock frequency and phase and outputting a decoded carrier signal; and circuitry for receiving the decoded carrier signal, for generating a software interrupt upon receipt of a predefined data packet (such as a SOF packet) and for passing the software interrupt to the USB microcontroller; wherein the USB microcontroller is configured to respond to the software interrupt (such as with an interrupt service routine provided therein) by generating an output signal adapted to be used as a synchronization reference signal.

Abstract: Techniques for image copying optimization are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for image copying optimization comprising receiving a request to copy a plurality of images, copying one or more of the plurality of images, deferring synchronization for each of the one or more of the plurality of images, receiving an indication to stop deferring synchronization, and synchronizing the one or more copied images of the plurality of images.

Abstract: According to an embodiment, a storage device includes a storage medium and a controller. The controller manages a local clock, adjusts the local clock in accordance with an order for adjustment of the managed local clock, and executes background processing involving access to the storage medium on the basis of the adjusted local clock.

Abstract: A controller timing system according to an exemplary aspect of the present disclosure includes, among other things, a master controller to generate a timing signal, a first slave controller configured to wake in response to the timing signal, and a second slave controller configured to wake in response to the timing signal. Timing of the first slave controller and timing of the second slave controller is coordinated based on the timing signal.

Abstract: The present technology proposes techniques for generating globally coherent timestamps. This technology may allow distributed systems to causally order transactions without incurring various types of communication delays inherent in explicit synchronization. By globally deploying a number of time masters that are based on various types of time references, the time masters may serve as primary time references. Through an interactive interface, the techniques may track, calculate and record data relative to each time master thus providing the distributed systems with causal timestamps.

Abstract: A data reception apparatus calculates an integrated number of bits by integrating the number of bits in a received bit string; calculates an integrated number of samples by integrating the number of samples obtained by oversampling each bit; obtains a fitting line indicating correspondence between the integrated number of bits and the integrated number of samples based on a plurality of points of which each point corresponds to either only a rise edge or only a fall edge of each bit in the received bit string; and determines a bit length in the received bit string based on the fitting line.

Abstract: In at least some embodiments, an electronic device includes a processor and a memory coupled to the processor. The electronic device also includes a serial communication link controller coupled to the processor, the serial communication link controller supporting dynamic reconfiguration of a plurality of communication link bundles. The serial communication link controller receives an input clock and generates first and second clock signals based on the input clock, the first and second clock signals having different clock rates and being provided to each of a plurality of communication link bundles.

Abstract: A method of performing and correcting a timing analysis performed by a data processing apparatus on a circuit formed of a plurality of cells to account for the reverse Miller effect. The timing analysis steps includes identifying cells on and in parallel with a signal path that are driven by a same signal and determining an output transition time and a delay using the characterization data for the cell. The correcting steps includes providing further characterization data for some of the cells; correcting the output transition time for some of the cells by increasing the output transition time by an amount dependent upon the Miller capacitance for the cell and using the correction to the output transition time to correct an input transition time for a next cell; and calculating a time taken for a data signal to travel along the signal path from the delay times.

Abstract: Method and system for rate matching in networks is provided. The method includes setting a strobe counter of a network device equal to an initial value; and determining whether a current clock phase matches a clock phase during which a first sub-port from among a plurality of sub-ports is designated to read from a memory at a receive segment of the network device. When the current clock phase matches the designated clock phase for the first sub-port, determining if the strobe counter is equal to one of a plurality of mask values; and when the strobe counter is not equal to one of the mask values, reading data out of the memory.

Abstract: Synchronizing time bases in a parallel computer that includes compute nodes organized for data communications in a tree network, where one compute node is designated as a root, and, for each compute node: calculating data transmission latency from the root to the compute node; configuring a thread as a pulse waiter; initializing a wakeup unit; and performing a local barrier operation; upon each node completing the local barrier operation, entering, by all compute nodes, a global barrier operation; upon all nodes entering the global barrier operation, sending, to all the compute nodes, a pulse signal; and for each compute node upon receiving the pulse signal: waking, by the wakeup unit, the pulse waiter; setting a time base for the compute node equal to the data transmission latency between the root node and the compute node; and exiting the global barrier operation.

Abstract: In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.

Abstract: An apparatus for synchronizing a data handover between a first clock domain and a second clock domain includes a calculator, a first-in-first-out storage, a synchronization pulse generator, a fill level information provider and a feedback path. The calculator is configured to provide a synchronization pulse cycle duration information describing a temporal position of synchronization pulses at a clock of the second clock domain. The first-in-first-out storage receives an input data value in synchronization with the first clock domain and provides an output data value in synchronization with the second clock domain in response to a current synchronization pulse. The fill level information provider provides fill level information describing a fill level of the FIFO. The feedback path feeds back the fill level information to the calculator to adjust the synchronization pulse cycle duration information.

Abstract: An interface circuit includes a general-purpose CPU configured to transmit a clock to a serial encoder with which bidirectional serial communication of clock synchronization type is to be performed, the CPU being configured to transmit and receive data to and from the serial encoder; and an additional circuit configured to detect a start bit of reception data transmitted from the serial encoder. The general-purpose CPU starts counting the number of bits of the reception data in response to a detection signal from the additional circuit, the detection signal indicating the detection of the start bit. The CPU stops transmitting the clock to the serial encoder upon completion of counting a predetermined number of bits of the reception data.

Abstract: A mechanism for dynamic skew correction in a multi-lane communication link includes a receiver unit including, for each of the lanes, a first-in first-out (FIFO). The FIFO may store received symbols to locations pointed to by a write pointer and output to downstream logic, symbols stored at locations pointed to by a read pointer. The receiver may also include a symbol drop unit that disables the write pointer in response to receiving a start alignment symbol, and enables the write pointer in response to receiving an end alignment symbol. The receiver also includes an alignment unit that disables the read pointer in response to detecting that the end symbol has been received at least one lane but not all lanes. In addition, the alignment unit may enable the read pointer in response to a determination that the end symbol has been received on all lanes.

Abstract: A communication control unit and a communication control system are provided in which control devices can synchronously operate. In a communication control system in which a communication control unit and multiple control devices having an actuator to operate a control target are connected via a network, the communication control unit provides a control command to the control devices, synchronizes times of the communication control unit and the control devices, obtains communication delays relative to the control devices, collects control start times of the control devices, obtains a time by subtracting the control start time from a predetermined time as a start time of the control device, calculates a time obtained by subtracting the communication delay from the start time for each control device, and transmits the control command to the control devices before the earliest time of the calculated times.

Abstract: An information handling system plays audio provided from a portable audio device at an information handling system audio subsystem in operating and powered down states of the information handling system. In the operating state, digital audio information is communicated from the portable audio device through a serial link for rendering at the information handling system into an analog audio signal presented by the audio subsystem. In the powered down state, digital audio information is rendered at the portable audio device and communicated as an analog audio signal through the serial link to the information handling system. A system module at the information handling system selectively switches the serial link to interface with the audio subsystem and play the analog signal as audible sounds. The system module supplies power to the audio subsystem to support playing the analog signal with the information handling system in the powered down state.

Abstract: Systems and methods that efficiently simulate controlled systems are presented. A simulation management component (SMC) controls simulation of a controlled system by controlling a desired number of nodes, each comprising a controller (e.g., soft controller) and a simulated component or process, which are part of the controlled system. The simulation can be performed in a step-wise manner, wherein the simulation can comprise a desired number of steps of respectively desired lengths of time. For each step, the SMC dynamically selects a desired clock (e.g., currently identified slowest clock) as a master clock for the next step. The SMC predicts a length of time of the next step to facilitate setting a desired length of time for the next step based in part on the predicted length of time. As part of each step, components can synchronously exchange data via intra-node or inter-node connections to facilitate simulation.

Abstract: A method distributing data in a network is provided. The method comprises measuring the path lengths between a reference clock and a plurality of remote destinations and sending a timing signal from the reference clock to the plurality of remote destinations. The method further comprises measuring the phase between the reference clock and a return signal from each of the plurality of remote destinations and adjusting the phase of the data such that each remote destination receives the data within a skew tolerance.

Abstract: Embodiments of the present invention provide a method, an apparatus, and a system for performing time synchronization on PCIE (PCI Express, peripheral component interconnect express) devices. The method mainly includes: a PCIE device receiving, through a hardware interface, a time synchronization signal sent from a clock source device; parsing, by the PCIE device, the time synchronization signal to obtain clock information carried in the time synchronization signal, and using the clock information as a clock of the PCIE device. The PCIE devices are supported to access a synchronous network, and the PCIE devices are supported to be used as a global clock source.

Abstract: If data received by the an information processing apparatus from an external device is delayed by one cycle or more with respect to a clock of the information processing apparatus, the information processing apparatus may require an additional process for adjusting a data latch timing. Delay information indicating a relationship between a calibration pattern to be received and an amount of cycle delay is stored in advance. Thus, the time required for detecting an amount of cycle delay, which is equivalent to the amount by which a signal for controlling a data latch mechanism in the information processing apparatus to stop its operation is delayed, can be reduced.

Abstract: Implementations of the present disclosure involve an apparatus and/or method for communicating between domains of a computing system, where at least one of the domains operates on a skipped clock signal. Communication from a skipped clock domain to a non-skipped clock domain, or free running domain, may include a valid signal component configured to indicate when a new data packet is available and one or more counters associated with the domains to count received data packets for acknowledgement or credit purposes. The free running domain may receive data packets from any number of skipped clock domains through the communication scheme described herein. Communication from a free running domain to a skipped clock domain may include delaying transmitted data packets to correspond with the cycles of the skipped clock signal to ensure that transmitted data packets arrive at the skipped clock domain to be properly read on a skipped clock cycle.

Abstract: A data processing system comprises a processor operating according to a first clock signal and a memory operating according to a second clock signal. The data processing system causes the processor to read data from the memory at least in part in response to a signal from first synchronizing circuitry and a signal from second synchronizing circuitry. The first synchronizing circuitry comprises a first storage element that samples a signal synchronized to the second clock signal in combination with a second storage element that samples an output of the first storage element. The first and second storage elements are triggered by inverse transitions in the first clock signal. The second synchronizing circuitry comprises third and fourth storage elements configured in a similar manner, except that they sample a signal synchronized to the first clock signal and are triggered by inverse transitions in the second clock signal.

Abstract: Mobile computing device power consumption can be reduced by using expiration window timers, state-based timers and/or the coordination of keep-alive timers. Upon detecting a trigger event causing a mobile computing device to transition from a low-power state to an active state, the device can determine whether the trigger event occurs within the expiration window of a timer, and execute tasks associated with the trigger event and the timer. Tasks associated with state-based timers can be executed if the mobile computing device or a component thereof is in (or, alternatively, not in) a specified state. A mobile computing device can execute tasks associated with multiple keep-alive timers used for maintaining communication links between the device and cloud-based service providers in a single active state.

Abstract: A flexible and scalable bi-directional CDC interface is set forth between clock domains in a SoC device. The interface comprises a pulse sync circuit for receiving a pulse synchronized to the source clock domain and in response outputting a busy signal to the source clock domain and outputting the pulse synchronized to said destination clock domain; an input register for latching data from said source clock domain in response to a transition of said source clock in the event said busy signal is not active and preventing said data from being latched in the event said busy signal is active so as not to corrupt previously latched data; and an output register for receiving said pulse from said pulse sync circuit and in response latching said pulse from said input register on a transition of said destination clock.

Abstract: A shift register structure is presented that can be used in fixed or variable rate serial to parallel data conversions. In an 1 to N conversion, data is received off an m-bit serial data bus and loaded into a N by m wide latch, before being transfer out onto an (N×m)-wide parallel data bus. Based on information on how of the N m-bit wide data units are to be ignored, the data will be clocked out at a variable rate. When loading data off the serial bus into the latch, upon refresh the current data is loaded into all N units of the latch, with one less latch being loaded at each subsequent clock. When the content of a unit of latch is to be ignored on the parallel bus, that unit is closed at the same time as the preceding unit so that it is left with redundant data.

Abstract: Deserializers are provided. The deserializer includes a data aligner, a selection signal generator and a selection output unit. The data aligner is configured to align data in response to internal clock signals having different phases from each other to generate higher aligned data and lower aligned data. The selection signal generator is configured to detect a phase of one of the internal clock signals in response to a phase detection signal to generate a selection signal. The phase detection signal includes a pulse generated according to a write command signal and a write latency signal. The selection output unit is configured to output the higher aligned data or the lower aligned data as selected alignment data in response to the selection signal.

Abstract: To provide a semiconductor device including an interface chip and a core chip and a measurement-target signal line and a reference signal line each including a through silicon via provided in the core chip and electrically connecting the interface chip and the core chip. The interface chip outputs a test clock generated by a first signal generation circuit to the core chip. The core chip includes a second signal generation circuit that generates a predetermined measurement signal from the test clock, and outputs the predetermined measurement signal to the measurement-target signal line and the reference signal line in a simultaneous manner. Further, the interface chip detects a phase difference of a plurality of predetermined measurement signals input via the measurement-target signal line and the reference signal line by an operational amplifier, and outputs a test result to a determination circuit. 1.

Abstract: The present invention may provide a system including a controller and a plurality of integrated circuits. The controller may control synchronization operations of the system, the controller may include a master timing counter and a controller data interface. Each integrated circuit may include a timing counter and an IC data interface. Further, each integrated circuit may synchronize its respective timing counter based on synchronization command received from the controller via the data interfaces. Hence, the system may provide synchronization between the controller and the integrated circuits without an extraneous designated pin(s) for a designated common time-based signal.

Abstract: The present image forming apparatus includes a first control unit and a second control unit driven by built-in clock oscillators to realize the distributed control. The first control unit generates, using a first timer driven by the built-in clock oscillator of the first control unit, a pulse signal corresponding to a predetermined clock rate and outputs the pulse signal to the second control unit. The second control unit measures, using a second timer driven by the built-in clock oscillator of the second control unit, a pulse width of the pulse signal outputted from the first control unit, and calculates a correction coefficient using reference pulse width corresponding to the predetermined clock rate and the measured pulse width. The processing unit processes using the calculated correction coefficient.