Abstract: The systems, methods and apparatuses described herein provide a computing environment that includes secure time management. An apparatus according to the present disclosure may comprise a non-volatile storage to store a synchronization time and a processor. The processor may be configured to generate a request for a current time, transmit the request to a trusted timekeeper, receive a digitally signed response containing a current, real-world time from the trusted timekeeper, verify the digital signature of the response, verify that the response is received within a predefined time, compare a nonce in the request to a nonce in the response, determine that the current, real-world time received from the trusted timekeeper is within a range of a current time calculated at the apparatus and update the synchronization time with the current, real-world time in the response.

Abstract: A device may receive information identifying a first set of instructions. The first set of instructions may identify an action to perform to test a first program. The device may identify a second set of instructions, related to testing a second program, that can be used in association with the first set of instructions. The first test may be similar to the second test. The device may identify multiple steps, of the first set of instructions, that can be combined to form a third set of instructions. The third set of instructions may be used to test the first program or a third program. The device may generate program code in a first programming language to perform the action. The first programming language may be different than a second programming language used to write the first set of instructions. The device may perform the action.

Abstract: An electronic device test system and method detects a memory serial number of an electronic device. The electronic device test system includes a Macintosh system computer, configured to execute a serial number detection program to detect the memory serial number of the electronic device; and a Windows system computer, configured to execute a serial number comparison program to compare whether the memory serial number of the electronic device satisfies a coding rule. The Macintosh system computer transmits the memory serial number to the Windows system computer by means of an RS232 interface for printing.

Abstract: An apparatus may include detection circuitry configured to detect a presence of a host clock signal on a host clock line, and detect a level of a host supply voltage upon detection of the host clock signal. The detection circuitry may configure a core regulator in a regulation mode or in a bypass mode based on the detected level of the host supply voltage. Additionally, components of analog circuitry of a non-volatile memory system may be partitioned into different supply voltage domains, with those components active during a sleep state receiving one supply voltage and those components inactive during the sleep state receiving a different supply voltage.

Abstract: Disclosed herein is a computing device configured to implement thermal throttling of a component of the computing device. The computing device includes an electronic component and a temperature sensor thermally coupled to the electronic component. The computing device also includes a thermal management controller to receive a temperature measurement from the temperature sensor and generate a throttling factor for the electronic component. If the temperature measurement is greater than a specified threshold, the throttling factor is to reduce performance of the electronic component to be at least the performance guarantee for the electronic component.

Abstract: A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.

Abstract: Apparatuses and methods for providing multiphase clock signals are described. An example apparatus includes first, second, third and fourth clocked inverters, first and second clock terminals, and first and second latch circuits. An input node and an output node of the first clocked inverter is coupled respectively to an output node of the fourth clocked inverter and an input node of the second clocked inverter. An input node and an output node of the third clocked inverter is coupled to an output node of the second clocked inverter and an input node of the fourth clocked inverter. The first and second clock terminals are supplied respectively with first and second clock signals. The first latch is coupled between the output nodes of the first and third clocked inverters, and the second latch circuit is coupled between the output nodes of the second and fourth clocked inverters.

Abstract: An image capturing apparatus is configured to have an interchangeable lens detachably mounted thereto, and is provided with an image capturing unit configured to obtain a captured image, a synchronous signal generation unit configured to generate a synchronous signal for reading out the captured image continuously from the image capturing unit, a communication unit configured to transmit the synchronous signal to the interchangeable lens, and a measurement unit configured to measure a delay time from a timing at which the synchronous signal is generated until a timing at which the communication unit transmits the synchronous signal to the interchangeable lens, the delay time being transmitted to the interchangeable lens by the communication unit together with the synchronous signal.

Abstract: An electronic apparatus includes a motherboard, a random access memory, a motherboard battery and a processing unit. The random access memory is disposed on the motherboard. The motherboard battery is disposed on the motherboard and electrically coupled to the random access memory to supply electrical power to the random access memory. The processing unit is disposed on the motherboard and electrically coupled to the random access memory. The processing unit is configured to write a test value into an idle address register of the random access memory and further to check whether the idle address register maintains the test value. When the idle address register maintains the test value, the processing unit determines that the motherboard battery functions normally. When the idle address register reverts to an initial value, the processing unit determines that the motherboard battery malfunctions.

Abstract: A test circuit receives LBIST and ATPG mode signals, and generates a first output as high when in ATPG or LBIST, and a second output as low when in ATPG or LBIST. A multiplexing circuit receives an ATPG clock and functional clock, and outputs one. A clock gate circuit includes a first latch receiving the second output, and an enable input receiving an inverse of the ATPG clock or functional clock. A second latch receives the first output, and has an enable input receiving the inverse of the ATPG clock or functional clock. The clock gate circuit includes a first AND gate receiving output of the first latch and ATPG clock or functional clock, a second AND gate receiving output of the second latch and the ATPG clock or LBIST clock, and an OR gate receiving outputs of the first and second AND gates, and generating a test clock.

Abstract: A circuit includes a reference clock terminal configured to receive a signal indicative of a reference clock, multiple low power oscillators (LPOs) and a controller. Each LPO is operable in at least one of three states including a sleep state in which the LPO is powered off, a calibration state in which the LPO undergoes calibration and an active mode in which the LPO is configured to provide a real-time clock based on the reference clock. The controller controls operation of the LPOs such that at most a single LPO is in the active state at any given time.

Abstract: A memory device is provided. The memory device includes one or more memories and a connector operably coupled to the one or more memories and configured to receive signals including a first reference clock signal from a connected host. The memory device further includes circuitry configured to determine a frequency of the first reference clock signal. The circuitry can be configured to generate a second reference clock signal and to compare the first and second reference clock signals to determine the frequency of the first reference clock signal. The memory devices can further include circuitry configured to adjust one or more operating characteristics of the memory device in response to the determined frequency of the first reference clock signal.

Abstract: A falling edge controller includes a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output, an update register control output, and a shift output; a shift register having a TDI (Test Data In) input, a shift register control input coupled to the shift register control output, address inputs, a select input, address and select outputs, and a TDO (Test Data Out) output; an update register having address and select inputs coupled to the address and select outputs, an update register control input coupled to the update register control output, address outputs coupled to the address inputs, and a select output coupled to the select input; and address circuitry having address inputs coupled to the address outputs, and having an enable output.

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Abstract: Systems and techniques are described for optimizing an integrated circuit (IC) design. Some embodiments can select a wide-bus in the IC design. Next, the embodiments can divide the wide-bus into one or more subsets of bus-wires, wherein each subset of bus-wires corresponds to a unit of information. The embodiments can then optimize clock gating for each subset of bus-wires.

Abstract: The estimation of a computing capacity of a machine. The computing capacity is estimated by iteratively adding and removing calibrated computer processes on the machine, and performing a sum of computing loads of processes that execute on the machine. In order to characterize the ability of a machine to run in parallel a number of processes having a defined computing load, the processes are associated to a condition of success.

Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series.

Abstract: Disclosed approaches for probing signals in a plurality of clock domains include inputting unsynchronized trigger signals from the plurality of clock domains to a plurality of instances of a multi-synchronizer circuit, respectively. Each instance of the multi-synchronizer circuit includes a plurality of synchronizer circuits. One or more of the plurality of synchronizer circuits synchronizes the respective unsynchronized trigger signal with one clock signal from the plurality of clock domains. Output of one of the one or more synchronizer circuits in each instance of the multi-synchronizer circuit is selected as a respective synchronized trigger signal. A trigger equation is evaluated based on a state of each respective synchronized trigger signal. A final trigger signal is generated based the evaluating of the trigger equation, a trigger marker is stored in a memory in response to a state of the final trigger signal, and states of probed signals are stored in the memory.

Abstract: A method, system and apparatus, for bootstrapping an autonegotiation signal in an intermediate device. The intermediate device initializes using a referenceless clock circuit. The intermediate device then recovers a more accurate clock sourced from a second device via a clock data recovery circuit in the intermediate device. The second device has a physical medium attachment interface within the intermediate device that does not require autonegotiation. The autonegotiation signal is communicated to a first device having a physical medium dependent interface to the intermediate device, thus requiring autonegotiation.

Abstract: A clock generator for generating a target clock with a frequency equal to the frequency of an input clock divided by a non-integer ratio is disclosed. The clock generator comprises a clock divider. The clock divider is configured to divide the input clock by a first dividing ratio during a first portion of a frame period to generate a first clock slower than the target clock, and divide the input clock by a second dividing ratio during a second portion of the frame period to generate a second clock faster than the target clock. A difference between the first dividing ratio and the second dividing ratio is 0.5 or 1. In some embodiments, the first dividing ratio and the second dividing ration are integers closest to the non-integer ratio.

Abstract: Skew of a multi-context PLD in context switch is reduced to achieve low power consumption. The frequency of a clock signal is switched in context switch operation in accordance with circuit operation to secure time required for context switch. By returning the frequency of the clock signal to the original frequency after executing the context switch, the PLD can maintain high-speed processing and perform the context switch accurately and safely. The time required for the context switch mainly depends on a hardware structure (circuit layout including a parasitic component). Thus, the reliability in the context switch can be improved when time that is equal to or longer than the longest time required for circuit change is secured.

Abstract: The subject matter described herein relates to methods, systems, and computer readable media for emulating network devices with different clocks. One method includes steps occurring in a network equipment test device. The steps include generating or obtaining timing information. The steps further include obtaining clock modification information. The steps further include emulating a plurality of different clocks using the timing information and the clock modification information. The method further includes emulating at least one network device that transmits test packets to a device under test using the different clocks.

Abstract: A slave device for exchanging data with a master device over a serial interface sends data to the master device upon receipt of a command from the master device. A controller responsive to a command byte in a receive register commences transmission of data in the transmit register under the control of a clock signal prior to reception of a complete command.

Abstract: A method relating generally to simulation is disclosed. In such a method, a first signal input and a second signal input are provided to a multiple clock domain object. The first signal input is for a first clock domain. The second signal input is for a second clock domain. The first clock domain is associated with a first frequency, and the second clock domain is associated with a second frequency different from the first frequency. The first signal input and the second signal input are converted to a common multiple clock frequency. A signal output is obtained from the multiple clock domain object responsive to the common multiple clock frequency. Switching activity is estimated for the multiple clock domain object. An output estimate associated with the switching activity estimated is output.

Abstract: An application processor includes a main central processing device that operates based on an external main clock signal received from at least one external clock source when the application processor is in an active mode, at least one internal clock source that generates an internal clock signal, and a sensor sub-system that processes sensing-data received from at least one sensor module on a predetermined cycle when the application processor is in the active mode or a sleep mode, and that operates based on the internal clock signal or an external sub clock signal received from the external clock source depending on an operating speed required for processing the sensing-data.

Abstract: A method, system, and computer program product to characterize and adaptively instantiate timing abstracts to perform timing analysis of an integrated circuit include generating an adaptable timing abstract for one or more macro models of a macro, the macro including two or more primitives of a component of the integrated circuit, the adaptable timing abstract being a parameterized timing model with at least one aspect represented by two or more models, and estimating requirements for the timing analysis, the requirements including accuracy, runtime, or memory requirements. Selecting a specific timing abstract, obtained by setting parameters of the adaptable timing abstract, is to perform the timing analysis based on the requirements.

Abstract: A method for clocking a physical layer (“PHY”) and a controller of a computing device, comprises the steps of: generating a reference clock signal; synchronizing a plurality of clock signals as a function of the reference clock signal; and clocking the controller and the PHY using the plurality of synchronized clock signals.

Abstract: A method, system, and computer program product to integrate functional analysis and common path pessimism removal (CPPR) in static timing analysis include determining initial path slack for a path for a given timing analysis test. The method also includes comparing the initial path slack with a threshold value to determine if the path passes or fails the given timing analysis test, and based on the path failing the given timing analysis test, performing the functional analysis on the path only based on performing the CPPR on the path, or performing the CPPR on the path only based on a result of performing the functional analysis on the path.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A method performed by a slave device coupled to a serial bus includes detecting an event related to a function of the slave device, initiating a first counter in the slave device, asserting an in-band interrupt request by driving at least one signal on the serial bus, and transmitting content of the first counter to a bus master coupled to the serial bus during an interrupt handling procedure. The first counter may count cycles of a clock used by the slave device or occurrences of a signaling state or condition on the serial bus. The content of the first counter may be used to determine a time stamp for the event.

Abstract: An electronic device and method in which a tuning process is performed during memory initialization, so as to reduce the occurrence of data read errors. The device may include a clock generator that generates a clock signal transmitted to a memory device, and a host control module that transmits to the memory device a change signal changing at least a portion of the clock signal, and/or a tuning related command. The host control module may receive setting data from the memory device, corresponding to at least one of the change signal and the tuning related command.

Abstract: A method of processing force signals from plural force platforms includes, in a computer, in an initialization process, receiving data distinguishing the plural platforms, monitoring force data signals from each of the plural platforms, and identifying each of the plural platforms to a force platform data process application by a sequence of received above-threshold force data signals. The method further includes, subsequent to the initialization process, processing subsequent force data signals according to the identification of each of the plural force platforms. The distinguishing data can include data retrieved from nonvolatile memory of each of the plural force platforms, such as a platform serial number, calibration data, and force platform capacity. A force platform system includes one or more force platforms and force platform signal conditioning circuitry connected to the one or more force platforms.

Abstract: An image processor adjusts luminance values of pixels in a captured image to compensate for effects on focal quality due to thermal expansion or contraction. Responsivity values for different colors are characterized and a table is generated mapping temperature values to weights for each pixel color based on the relationship between temperature and focal length and the relationship between focal length and focal quality in each different color. Luminance values for one color may be compensated based on the measured luminance values for other colors, the relative responsivity values, and the weights.

Abstract: An integration circuit may include a plurality of switches, at least one operational amplifier, and at least one feedback capacitor, sequentially transfers electrical charges charged in a node capacitor to the feedback capacitor, and integrates the electrical charges. The operational amplifier may be synchronized with a clock signal applied to at least one of the plurality of switches to thereby be operated in one of a normal mode and a low power mode.

Abstract: A circuit includes a time delta detector configured to receive an input clock signal and a reference clock signal and generate a delta pulse signal and a reference pulse signal. A comparison circuit is configured to receive the delta pulse signal and the reference pulse signal. The comparison circuit generates an output indicative of a bit of a time difference between the input clock signal and the reference clock signal. A control circuit is configured to receive the output from the comparison circuit. The control circuit maintains a count of the time difference between the input clock signal and the reference clock signal.

Abstract: Apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation are described herein. An example includes determining soft data for a group of memory cells each programmed to one of a number of data states, wherein the soft data comprises a number of different soft data values, determining a quantity of memory cells associated with each of the different soft data values, and inferring at least a portion of a threshold voltage distribution associated with the group of memory cells via an interpolation process using the determined quantities of memory cells associated with each of the different soft data values.

Abstract: An apparatus, comprising a clock adapted to provide a clock signal alternating with a cycle between a first level and a second level if a timing violation is not detected; a first latch adapted to be clocked such that it passes a first signal when the clock signal is at the first level; a second combinational logic adapted to output a second signal based on the first signal passed through the first latch; a second latch adapted to be clocked such that it passes the second signal when the clock signal is at the second level; a detecting means adapted to detect the timing violation of at least one of the first signal and of the second signal; a time stretching means adapted to stretch, if the timing violation is detected, the clock such that the clock alternates between the first level and the second level with a delay.

Abstract: A clock circuit for generating a clock signal includes a first clock generator configured to generate a first clock signal, a second clock generator configured to generate a second clock signal, and a selector connected to the first clock generator and the second clock generator. The selector is configured to select one of the first and second clock signals as a selected clock signal based on a selection signal. The selector is configured to transmit, if a selection of the selector changes from the second clock signal to the first clock signal, a turn-on request signal to at least one first component to enable the at least one first component. The at least one first component is configured to send a turn-on acknowledgement signal to the selector in response to the turn-on request signal. The first clock generator includes the at least one first component.

Abstract: A phase locked loop has an integer phase detector to detect an integer phase by measuring a cycle number, a fractional phase detector to detect a fractional phase of smaller than one cycle between a reference signal and the oscillation signal, a frequency error generator to generate a frequency error signal between the reference signal and the oscillation signal, a glitch corrector to correct the frequency error signal to generate and output a glitch-corrected signal and the frequency error signal, a phase error generator to generate a phase error by integrating an output signal of the glitch corrector, an oscillator controller to control an oscillation frequency of the oscillation signal, and a synchronous detector to detect whether a phase of the reference signal and a phase of the oscillation signal are in an phase-lock state, and to stop detection of the integer phase when the phase-lock state is detected.

Abstract: Systems and methods for dynamic clock and voltage scaling can switch integrated circuits between frequency-voltage modes with low latency. These systems include a resource power manager that can control a power management integrated circuit (PMIC), phase locked loops (PLLs), and clock dividers. The resource power manager controls transitions between frequency-voltage modes. The systems and methods provide dynamic clock and voltage scaling where the transitions between frequency-voltage modes are an atomic operation. Additionally, the resource power manager can control many modules, for example, clock dividers, in parallel. The invention can, due to lower latency between frequency-voltage modes, can provide improved system performance and reduced system power.

Abstract: Methods, apparatuses, and computer program products for adaptive clock throttling for event processing are provided. Embodiments include an event processing system receiving a plurality of events from one or more components of the distributed processing system. Embodiments also include the event processing system determining that an arrival attribute of the plurality of events exceeds an arrival threshold. Embodiments also include the event processing system, adjusting, in response to determining that the arrival attribute of the plurality of events exceeds the arrival threshold, a clock speed of at least one of the event processing system and a component of the distributed processing system.

Abstract: A high performance computing system and methods are disclosed. The system includes logical partitions with physically removable nodes that each have at least one processor, and memory that can be shared with other nodes. Node hardware may be removed or allocated to another partition without a reboot or power cycle. Memory sharing is tracked using a memory directory. Cache coherence operations on the memory directory include a test to determine whether a given remote node has been removed. If the remote node is not present, system hardware simulates a valid response from the missing node.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a plurality of information handling resources having shared heat-rejecting media for transferring heat from the plurality of information handling resources and a thermal management driver. The thermal management driver may comprise a program of instructions embodied in computer-readable media and executable by a processor, the thermal management driver configured to determine a respective workload associated with each of the plurality of information handling resources and control individual operating frequencies of the plurality of information handling resources based on the respective workloads and a temperature associated with the heat-rejecting media.

Abstract: Embodiments including systems, methods, and apparatuses associated providing an interface between a north complex and a south complex of a system on a chip (SoC). In embodiments, the north complex may include a microcontroller in an input signal requirement. A power-on control block may be coupled with the microcontroller, and the power-on control block may be configured to receive a control signal from a component of the south complex, and alter the control signal based at least in part on the input signal requirement of the microcontroller.

Abstract: The present disclosure describes a serial control channel processor. In some aspects, a time-based instruction corresponding to a command is executed and a signaling event based on the time-based instruction is generated at a communication port. In other aspects a signal containing data is received at a communication port and a time-based instruction is executed to read data of the received signal.

Abstract: Systems and methods for controlling a frequency of a clock signal by selectively swallowing pulses in the clock signal are described herein. In one embodiment, a method for adjusting a frequency of a clock signal comprises receiving the clock signal, and swallowing pulses in the clock signal according to a repeating clock-swallowing pattern, wherein the pattern is defined by a sequence of numbers.

Abstract: A communications system receiver is described providing automatic timing adjustment of receive data sampling. A concurrently received clock signal is used as both a reference for generation of internal receiver timing signals, and as an exemplar for adjustment of those timing signals to optimize received data sample timing.

Abstract: A delay measurement technique using a tapped delay line edge capture circuit that captures tap position of edges within the delay line provides accuracy of measurement to one pico-second and below. A control circuit causes latches to capture an edge of a signal delayed through the delay line at taps of the delay line. The frequency of a clock from which the signal is derived is adjusted and tap outputs are captured by latches and averaged. A first frequency is found at which the average edge position is midway between two adjacent tap positions. A second signal, which may be the reference signal that clocks the latches, is propagated through the delay line and a second frequency is found for which the average edge position lies at the boundary between the two tap positions. The delay is determined from the difference between the periods of the first frequency and the second frequency.

Abstract: A delay measurement technique using a tapped delay line edge capture circuit that captures tap position of edges within the delay line provides accuracy of measurement to one pico-second and below. A control circuit causes latches to capture an edge of a signal delayed through the delay line at taps of the delay line. The frequency of a clock from which the signal is derived is adjusted and tap outputs are captured by latches and averaged. A first frequency is found at which the average edge position is midway between two adjacent tap positions. A second signal, which may be the reference signal that clocks the latches, is propagated through the delay line and a second frequency is found for which the average edge position lies at the boundary between the two tap positions. The delay is determined from the difference between the periods of the first frequency and the second frequency.

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.