Abstract: A circuit receives an input clock pulse signal characterized by a first frequency and a first pulse width, and produces an output pulse signal characterized by a second frequency that is half of the first frequency and a second pulse width that is equal to the first pulse width. The circuit also includes a first D-flipflop, a first inverter, a first Schmitt trigger, and a first AND gate. The first D-flipflop includes a clock input terminal for receiving the input clock pulse signal and an output terminal for producing a first data output. The first inverter couples the output terminal and a data input terminal of the first D-flipflop. A first Schmitt trigger receives the input clock pulse signal and provides a first delayed input clock signal. The first AND gate receives the first data output and the first delayed input clock signal, and provides the output pulse signal.

Abstract: Clocks of two semiconductor circuit are set to a common clock source when both the first and second semiconductor circuits are in a slow clock speed at which an input/output (IO) at an interface between the first and second semiconductor circuit is capable of operating. Division counters of the two clocks are synchronized at the slow clock speed. The two semiconductor circuits are switched to a fast clock speed that is a multiple of the slow speed, wherein the IO is not capable of operating at the fast clock speed. Pulses from a division counter of the first circuit are sent to a spare division counter of the second circuit, and then a primary division counter of the second counter is aligned to this spare division counter to keep the two circuits synchronized at the fast clock speed.

Abstract: A system includes a first device and a second device coupled to a link having one or more lanes. The first device is to transmit two or more frames to synchronize the one or more data lanes, where each frame comprises a quantity of bits. The second device is to receive a first set of bits from each data lane corresponding to the quantity of bits in each frame of the two or more frames. The second device is to determine that the first set of bits received from a data lane of the one or more data lanes does not correspond to a frame boundary of the two or more frames. The second device is further to synchronize each data lane of the one or more data lanes with respect to the frame boundary, responsive to determining that the first set of bits does not correspond to the frame boundary.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as long term evolution (LTE). According to various embodiments of the disclosure, a method for operating a base station in a wireless communication system includes receiving, from a terminal, information on a residence time of the terminal and a transmission time of an uplink frame, determining a radio access network residence time based on the transmission time of the uplink frame, and transmitting the radio access network residence time and the residence time of the terminal to a user plane function (UPF).

Abstract: A serial bus re-driver circuit includes an edge detector circuit and a booster circuit. The edge detector circuit is configured to detect a transition of serial bus signal. The booster circuit is coupled to the edge detector circuit, and is configured to switch current to the serial bus signal. The booster circuit includes a leading edge boost pulse generation circuit and a trailing edge boost pulse generation circuit. The leading edge boost pulse generation circuit is configured to switch a first current pulse to the serial bus signal at the transition of the serial bus signal. The trailing edge boost pulse generation circuit is configured to switch a second current pulse to the serial bus signal. The second current pulse is shorter than the first current pulse.

Abstract: A utility meter includes a consumption measurement unit for generating consumption data, a meter processor, and a RTC for time stamping the consumption data to provide interval meter data during interval meter operation. A memory stores the interval meter data. The meter processor implements/initiates responsive to a power loss that suspends RTC operation, switching from interval to relative time operation where consumption data is stored as relative consumption data together with a relative time as relative meter data. Responsive power restoration and receiving a current time, the meter switches from relative time to interval meter operation. The restoration time is calculated using the current and an elapsed time since the restoration. The time of restoration and current time is used to generate calculated times. The consumption data from relative time operation is time stamped with the calculated times to provide time-corrected relative meter data that is stored to the memory.

Abstract: An application processor includes a main central processing device that operates based on an external main clock signal received from at least one external clock source when the application processor is in an active mode, at least one internal clock source that generates an internal clock signal, and a sensor sub-system that processes sensing-data received from at least one sensor module on a predetermined cycle when the application processor is in the active mode or a sleep mode, and that operates based on the internal clock signal or an external sub clock signal received from the external clock source depending on an operating speed required for processing the sensing-data.

Abstract: Various embodiments include methods and devices for timer failure detection and recovery. The embodiments may include running a plurality of timers in parallel, including a first operation timer, a first monitor timer, and a second monitor timer each having an independent time base, determining whether a first timer of the plurality of timers fails, removing the first timer from use in response to determining that the first timer fails, determining whether the first timer has a consistent difference in independent time base with a second timer of the plurality of timers, and returning the timer to use with a time adjustment in response to determining that the first timer has a consistent difference in independent time base with the second timer.

Abstract: A method and device for determining a constant parameter of an inhibition value for adjusting the device operating frequency of a watch equipped with a quartz oscillator. The following steps are performed by a self-calibration circuit of the electronic watch device: from a first external pulse and a second external pulse received from a system external to the watch and separated by a measurement time, corresponding to a reference number of reference periods for a periodic calibration signal derived from the time-measurement signal and having a calibration frequency derived from the natural frequency of the quartz oscillator, determining a calibration parameter representative of a ratio between a calibration period and a reference period for the periodic calibration signal, and determining a constant inhibition parameter as a function of the calibration parameter.

Abstract: Techniques are disclosed for performing time synchronization for a plurality of computing devices without relying upon a minimum measured delay. In one example, processing circuitry obtains time stamp data in accordance with an iteration of a synchronization operation for a timing protocol, wherein the time stamp data describes one or more measured delays for a path between a first computing device and a second computing device, computes a skewness estimate from the time stamp data using a regression analysis, the skewness estimate comprising a frequency difference between a first clock at the first computing device and a second clock at the second computing device, computes an offset estimate between the first clock and the second clock by applying a prediction model to the skewness estimate; and corrects at least one of the first clock or the second clock based at least on the offset estimate.

Abstract: Various techniques are provided to implement programmable linear-feedback shift register (LFSR) circuits. In one example, the LFSR circuit includes state storage elements. Each state storage element is configured to store a state signal. The LFSR circuit further includes programmable logic stage circuits each configured to selectively receive an input signal and a set of state signals, determine an output signal based at least on the set of state signals, and provide the output signal. Each programmable logic stage circuit is connected to at least one other programmable logic stage circuit. The LFSR circuit further includes pipeline elements. Each pipeline element is configured to selectively connect at least two programmable logic stage circuits. The LFSR circuit further includes sets of latency balance elements. Related systems and methods are provided.

Abstract: A method includes requesting, by a component of a memory sub-system controller, control of a data path associated with a memory device coupleable to the controller. The method can include generating, by the component, data corresponding to an operation to test the memory device and causing, by the component, the data to be injected to the data path such that the data is written to the memory device. The method can further include reading, by the component, the data written to the memory device and determining, by the component, whether the data read by the component from the memory device matches the data written to the memory device.

Abstract: Methods and systems are described for generating early and late votes for a clock recovery system, each early or late vote associated with a detected transitional data pattern in a data stream, generating a first early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a first time interval, generating a second early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a second time interval, comparing the first and the second early-late vote measurements, and outputting a CDR-lock signal at least in part responsive to determining that the first and the second early-late vote measurements are within a predetermined threshold.

Abstract: A detection circuit is configured to detect phase information between two clock signals of different frequencies, and the two clock signals include a low frequency clock signal and a high frequency clock signal. The detection circuit includes: a signal generation module, configured to detect the low frequency clock signal at an edge of the high frequency clock signal to generate a to-be-sampled signal, and generate a target sampling signal when the high frequency clock signal is kept at a preset level and the low frequency clock signal meets a preset condition; and a sampling module, connected with the signal generation module and configured to detect the to-be-sampled signal at an edge of the target sampling signal to generate a detection result signal.

Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

Abstract: A generic physical layer providing a unified architecture for interfacing with an external memory device. The physical layer comprises a transmit data path for transmitting a parallel data to the external memory device and a receive data path for receiving a serial data from the external memory device. The generic physical layer is characterized by a receive enable logic for masking strobe of the serial data, wherein the transmit data path and the receive data path each comprising a FIFO circuit, a data rotator and an adjustable-delay logic for delay tuning and a per-bit-deskew for multi-lane support.

Abstract: A source driver adapted to drive a display panel is provided. The source driver includes an output buffer and a slew rate adjustment circuit. An input terminal of the output buffer receives a driving voltage. An output terminal of the output buffer outputs an output signal adapted to drive the display panel. The slew rate adjustment circuit dynamically adjusts a slew rate of a rising edge of the output signal according to a first setting and dynamically adjusts a slew rate of a falling edge of the output signal according to a second setting independent of the first setting, such that the adjustment to the slew rate of the rising edge of the output signal is independent of the adjustment to the slew rate of the falling edge of the output signal.

Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.

Abstract: Measuring a control system response time of a second clock tree is provided, comprising measuring a skew between the second clock signal and the first clock signal and storing the skew, initiating a delay change of a delay induced by the programmable delay line and starting a time measurement. At least one iteration is performed of measuring the skew between the second clock signal and the first clock signal and comparing the measured skew with the stored skew. Based on the result of the comparison, stopping after a current iteration and stopping the time measurement. A result of the time measurement is the control system response time.

Abstract: A receiving system includes a controller that selectively activates one or more of a plurality of paths between an input of a first multiplexer and an output of a second multiplexer. The receiving system includes a plurality of bandpass filters, each one of the bandpass filters being disposed along a corresponding one of the plurality of paths and configured to filter a signal received at the bandpass filter to a respective frequency band. The receiving system also includes a plurality of variable-gain amplifiers (VGAs), each one of the plurality of VGAs disposed along a corresponding one of the plurality of paths and configured to amplify a signal received at the VGA with a gain controlled by an amplifier control signal received from the controller. At least one, but not all, of the VGAs is a fixed-gain amplifier with a bypass switch to selectively bypass the fixed-gain amplifier.

Abstract: Provided are a touchscreen display device, a touch driving circuit, and a driving method. Image display and touch sensing are simultaneously performed and the interference between display driving and touch driving are minimized or removed, so that excellent image display and touch sensing performance is obtained. Poor touch sensitivity occurring in a specific area (e.g. an edge area) is reduced by using differential sensing sequence control, internal correction resistors of the touch driving circuit, and signal characteristics control.

Abstract: A phase-locked loop circuit is provided, including: a phase frequency comparing unit to compare phase of an external reference clock signal and phase of a comparing clock signal, and generate an error signal corresponding to the comparing result; an oscillation unit to generate an internal clock signal having oscillation frequency corresponding to the error signal; a frequency dividing unit to divide frequency of the internal clock signal according to a pre-set dividing ratio, to generate the comparing clock signal; a control unit to generate a control signal to respectively change connection of the oscillation unit and connection of the frequency dividing unit after phase comparing. The phase-locked loop circuit can detect and correct mistaken locking and harmonic locking. There is no need to reset the circuit when mistakenly locked, sudden output phase change and additional spike signal that affecting the integrity of the clock signal are prevented.

Abstract: A clock and data recovery circuit, a memory storage device and a signal adjustment method are disclosed. The method includes: detecting a phase difference between a first signal and a clock signal; generating a vote signal according to the phase difference and a first clock frequency; sequentially outputting a plurality of adjustment signals according to the vote signal and a second clock frequency, wherein the first clock frequency is different from the second clock frequency; and generating the clock signal according to the sequentially output adjustment signals.

Abstract: Each of a plurality of control devices includes: an upper communication part which transmits/receives first data to/from other control devices via a first network; and a lower communication part which transmits/receives second data to/from one or more equipment via a second network. The upper communication part has a first timer time-synchronized with each other among the plurality of control devices. The lower communication part determines, based on the time of the first timer, a timing to start processing for transmitting the second data to the one or more equipment.

Abstract: Presented herein are methodologies for generating clock signals for transceivers that rely on frequency and phase error correction functions. The methodology includes generating a differential clock signal at a fundamental frequency, generating, based on the differential clock signal and using a multiphase generator, four quadrature signals at the fundamental frequency, supplying the four quadrature signals to an injection-locked phase rotator, and outputting, from the injection-locked phase rotator, a phase adjusted multiphase clock signal based on the four quadrature signals.

Abstract: A method includes requesting, by a component of a memory sub-system controller, control of a data path associated with a memory device coupleable to the controller. The method can include generating, by the component, data corresponding to an operation to test the memory device and causing, by the component, the data to be injected to the data path such that the data is written to the memory device. The method can further include reading, by the component, the data written to the memory device and determining, by the component, whether the data read by the component from the memory device matches the data written to the memory device.

Abstract: This invention relates to peer-to-peer transparent clocks and methods of estimating skew in peer-to-peer transparent clocks. Embodiments of the invention relate to techniques for estimating clock skew between a free-running clock in a transparent clock and a master clock, in particular by using the timing information embedded in timing messages passing through the transparent clock. Further embodiments of the invention set out uses of these estimates to modify the residence times computed by the transparent clock and a synchronization network including such transparent clocks.

Abstract: Embodiments described herein provide a system having phase synchronized local oscillator paths. The system includes a first circuit, which in turn includes a first counter configured to generate a first counter output signal in response to a first clock signal controlling the first counter. The first circuit also includes a first phase-locked loop coupled to the first counter. The first phase-locked loop is configured to receive the first counter output signal as a first synchronization clock for the first phase-locked loop and to generate a first output signal having rising edges aligned according to the first counter output signal.

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

Abstract: In some embodiments, a system includes a memory system, a real-time computing device, and a controller. The real-time computing device stores data within a local buffer having a corresponding storage threshold, where the data satisfies the storage threshold, and where the storage threshold is based on a latency of the memory system and an expected rate of utilization of the data of the local buffer. The controller detects that the memory system should perform an operation, where the memory system is unavailable to the real-time computing device during the operation. In response to detecting that an amount of time for the operation exceeds an amount of time corresponding to the storage threshold, the controller overrides the storage threshold. The controller may override the storage threshold by modifying the storage threshold and by overriding a default priority for access requests of the real-time computing device to the memory system.

Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

Abstract: Methods, systems, and programs provide for executing distributed transactions in a cloud storage system with a hierarchical namespace. One method includes receiving a request with operations to be executed atomically. Further, nodes are identified for executing the operations, each node having a respective clock and having at least part of a transactions table for controlling updates to entities. Each clock is one of a loosely-synchronized, a strictly-synchronized clock, a logical, or a physical clock. Additionally, the nodes process the operations, which includes setting a commit timestamp (CS) to a value of the clock in the node if the node is a first node in the processing. One node coordinates the transactions, and may be one of the nodes executing transactions. If the clock in the node is less than a current value of the CS, the node waits for the clock to reach the current value of the CS and the CS is updated.

Abstract: Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.

Abstract: A bi-sided pattern processor comprises a plurality of storage-processing units (SPU's). Each of the SPU's comprises at least a memory array and a pattern-processing circuit. The preferred pattern processor further comprises a semiconductor substrate with opposing first and second surfaces. The memory array is disposed on the first surface, whereas the pattern-processing circuit is disposed on the second surface. The memory array stores patterns; the pattern-processing circuit processes these patterns; and, they are communicatively coupled by a plurality of inter-surface connections.

Abstract: Described is a low latency re-timer for systems supporting spread spectrum clocking. The re-timer comprises: a first clock frequency estimator to estimate a frequency of a receive clock (RX CLK) and to provide a first timestamp associated with a first clock that underwent spread spectrum; a second clock frequency estimator to estimate a frequency of a transmit clock (TX CLK) and to provide a second timestamp associated with a second clock that underwent spread spectrum; and a comparator to compare the first timestamp with the second timestamp.

Abstract: Techniques and mechanisms for an integrated circuit (IC) chip to generate a clock signal for use by one or more resources of the IC chip. In an embodiment, a clock signal is generated with phase-locked loop (PLL) circuitry of an IC chip based on a cyclical signal which is provided to the IC chip by an external source. A supply voltage provided to the PLL circuitry is automatically updated based on one of a requested frequency for the clock signal, a frequency of the received cyclical signal, or a voltage of a control signal used by a voltage controlled oscillator of the PLL circuitry. In another embodiment, a series of incremental changes to a frequency of the clock signal is automatically performed according to a predefined overclocking scheme or underclocking scheme.

Abstract: A system is provided that controls the clocking of a processor depending upon its usage of execution units. As the processor transitions from a default mode of operation using a default number of the execution units to an increased load mode of operation using an increased number of the execution units, a current drawn by the processor from a power rail remains substantially unchanged.

Abstract: Disclosed aspects relate to a clock distribution network of a synchronous logic device. The synchronous logic device has sub-circuits having different clock domains. The clock domains form a hierarchical structure. The clock distribution network has a clock source to provide a global clock signal. A programmable delay line associated with a sub-circuit generates a local clock signal for the sub-circuit by delaying the signal. A global skew control circuit can manage clock skew between the local clock signals. The global skew control circuit may adjust a delay, determine initial operations for the delay lines, verify whether it is possible to perform the initial operations, and perform a correction operation. The correction operation can include correcting the control commands such that the corrected commands lead to the same change of skew adjustment between the local clocks.

Abstract: A memory device includes an internal storage unit configured to store mode data specifying an operating speed of the memory device; a control decoder coupled to the internal storage unit, the control decoder configured to generate a delay control signal based on the mode data; and an input buffer coupled to the control decoder, the input buffer configured to adjust a delay of an input signal based on the delay control signal.

Abstract: A non-volatile memory module includes an input/output buffer coupled to first and second signal transmission paths, and control circuitry coupled to the input/output buffer, the control circuitry being configured to receive a first signal on the first signal transmission path, receive a second signal on the second signal transmission path, determine a delay between the first signal and the second signal, generate a delay mismatch value based on the determined delay, and transmit the delay mismatch value on one or more signal transmission paths coupled to the input/output buffer.

Abstract: An electronic circuit includes: an arithmetic processing part executing given arithmetic processing; and a capacitor supplying accumulated electric charge when the arithmetic processing part executes arithmetic processing. The arithmetic processing part operates by using the electric charge supplied from the capacitor.

Abstract: A method for correlating first and second local time counts in first and second integrated circuits is provided. The first and second integrated circuits communicate via a communication network. A separate time control signal path is also provided between the integrated circuits. The method comprises determining a signal propagation latency associated with propagation of a latency determining signal between the integrated circuits on the time control signal path, and correlating the first and second local time counts in dependence on the signal propagation latency and a time correlating signal transmitted on the time control signal path.

Abstract: A clock distribution component may include a plurality of electrically connected buffer pair triads arranged in a plurality of levels. A buffer pair triad, of the plurality of buffer pair triads, may include three buffer pairs that are connected via wire. Each buffer pair triad may share at least one buffer pair with one or more buffer triads of the plurality of buffer pair triads. Buffer pairs, of the plurality of buffer pair triads, may be arranged in buffer rows and buffer columns. The plurality of levels may include a first level associated with a first buffer pair triad and one or more additional levels. Each level of the one or more additional levels may include at least three buffer pair triads and at least two more buffer pair triads and/or at least two less buffer pair triads than an adjacent level of the one or more additional levels.

Abstract: A transceiver and a clock generation module are provided. The transceiver includes a receiver and the clock generation module. The receiver receives a receiving-input-data and a receiving-input-strobe. The receiver includes a data-receiving circuit for delaying the receiving-input-data and a strobe-receiving circuit for delaying the receiving-input-strobe. The clock generation module includes a calibration circuit, a phase-compensation module, and a multi-phase signal generator. The phase-compensation module compensates one of the data-receiving circuit and the strobe-receiving circuit according to a data-phase-compensation signal and a strobe-phase-compensation signal generated by the calibration circuit. The multi-phase signal generator generates shifted system-clock signals. A phase difference between the first and the second shifted system-clock signals is equivalent to a phase difference between the receiving-path-data and the receiving-path-strobe.

Abstract: A memory device includes an internal storage unit configured to store mode data specifying an operating speed of the memory device; a control decoder coupled to the internal storage unit, the control decoder configured to generate a delay control signal based on the mode data; and an input buffer coupled to the control decoder, the input buffer configured to adjust a delay of an input signal based on the delay control signal.

Abstract: A signal receiving apparatus includes a clock and data recovery (CDR) circuit, a first sampler, and at least one deskew circuit. The CDR circuit receives a first signal through a first lane of the signal receiving apparatus and decodes the first signal to extract a first clock signal from the first signal. The CDR circuit provides the first clock signal to the first sampler and the least one deskew circuit. The first sampler receives the first signal through the first lane of the signal receiving apparatus. The first sampler samples the first signal based on the first clock signal to generate a first output signal. The at least one deskew circuit receives a second signal through at least one second lane of the signal receiving apparatus and adjusts a phase skew between the first clock signal and the second signal so as to generate a second output signal.

Abstract: A configuration for realizing time synchronization between different protocols is provided. There is provided a control device that constitutes a control system for controlling machines or facilities. The control device includes first communication means configured to transmit and receive data in accordance with a first protocol. The first communication means includes a first timer that defines a time of data transmission and is time-synchronized with an entity to and from which data is transmitted and received. The control device includes second communication means configured to transmit and receive data in accordance with a second protocol different from the first protocol. The second communication means includes a second timer that defines a time of data transmission and is time-synchronized with an entity to and from which data is transmitted and received. The control device includes synchronization means configured to time-synchronize the first timer and the second timer.

Abstract: A device and a method for supporting clock transfer of multiple clock domains, where the device includes N phase frequency detectors, N filters, N clock reconstructors, and N clock domain interfaces, where N is an integer greater than or equal to two, the N clock domain interfaces are in a one-to-one correspondence with the N phase frequency detectors, the N filters, and the N clock reconstructors, the N phase frequency detectors are respectively connected to N clock sources, and at least two clock sources of the N clock sources are different. The foregoing device flexibly adapt to multiple different clock domains, implement that a single device simultaneously supports clock transfer of multiple clock domains, and flexibly satisfy user demands without adding or replacing devices.

Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.

Abstract: A method for providing a logic synthesis of a pipeline circuit is disclosed. The method includes: providing a circuit design of the pipeline circuit, wherein the circuit design includes a first logic module as a current stage, and based on an operation of the first logic module, generating a first time marked graph (TMG) that corresponds to a plurality of behavioral phases of the first logic module, wherein the first TMG includes a plurality of vertexes and a plurality of edges, wherein each vertex corresponds to one of the plurality of behavioral phases that occur in sequence and each edge is coupled between two respective vertexes thereby corresponding to a transition from one behavioral phase to another subsequently occurring behavioral phase.