Abstract: An apparatus comprising an analog-to-digital converter (ADC); a frequency-domain equalizer (FDEQ); a time-domain interpolator positioned between the ADC and the FDEQ, wherein the time domain interpolator is coupled to the ADC and the FDEQ and configured to perform a time-domain interpolation to compensate a signal sample for a plurality of ADC induced changes.

Abstract: This invention includes a clock tree to which clock signals are distributed, and a phase comparison circuit configured to detect the phase difference between a plurality of feedback clock signals upon receiving the plurality of feedback clock signals output from different branching points of the clock tree. The invention includes a feedback clock signal generation circuit configured to generate a variation-corrected feedback clock signal for correcting a manufacture variation in the semiconductor integrated circuit based on the phase difference detected by the phase comparison circuit. The invention includes a phase regulation circuit configured to delay the clock signal so as to reduce the phase difference between a reference clock signal and the variation-corrected feedback clock signal generated by the feedback clock signal generation circuit.

Abstract: Various methods and apparatus for managing signals between a processor and a memory device are disclosed. In one aspect, a method of managing signals between a processor and a memory device wherein the processor and the memory device are operatively coupled by a data signal path and a clock signal path is provided. The method includes setting the skew between the data signal path and the clock signal path away from a spectral peak of a phase jitter transfer function.

Abstract: An apparatus for synchronizing an output clock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter. The first timing synchronization circuit is operable to generate a delay to synchronize a reference clock signal representative of the input clock signal with a feedback clock signal representative of the output clock signal responsive a strobe signal. The control logic is operable to generate an enable signal based on the reference clock signal and generate the strobe signal based on the feedback clock signal. The counter is operable to count cycles of the reference clock signal occurring between the enable signal and the strobe signal to generate a loop count for the first timing synchronization circuit.

Abstract: An apparatus comprising a reference circuit, a resistor ladder, and an output circuit. The reference circuit may be configured to generate a reference signal in response to (i) a clock signal, (ii) a first phase signal and (iii) a second phase signal. The resistor ladder circuit may be configured to generate a tap voltage in response to the reference signal. The tap voltage may be generated by enabling one or more of a plurality of tap resistors. The output circuit may be configured to generate an adjusted clock signal in response to (i) the tap voltage, (ii) the clock signal, (iii) the first phase signal, (iv) the second phase signal, and (v) a reset signal. The adjusted clock signal may have an adjusted phase with respect to the clock signal.

Abstract: A semiconductor device with a clock control circuit that outputs an internal clock signal configured by delaying external clock signals based on at least a feedback clock signal; a plurality of output buffers that output data in synchronization with the internal clock signal; an output replica that is a replica of the output buffers and that generates the feedback clock signal in synchronization with the internal clock signal and supplies the feedback clock signal to the clock control circuit; and a clock tree that receives the internal clock signal from the clock control circuit and transmits the internal clock signal to the plurality of output buffers and the output replica such that signal line are substantially equal to one another.

Abstract: Methods, systems, and apparatuses are described for aligning lanes of low speed serial links coupled to a transceiver. The transceiver cooperatively performs lane alignment operations with a low speed device during initialization of the transceiver and the low speed device. The lane alignment operations are performed in-band using the low speed serial links, and therefore, do not require additional out-of-band-signaling wires between the transceiver and the low speed device to perform the lane alignment operations. The lane alignment operations may be performed by a handshaking process performed by the transceiver and the low speed device, where the transceiver and the low speed device provide training pattern(s) of data that are used to align the low speed serial links. The low speed serial links are continuously monitored after initialization is complete to detect various transient impairments and to re-initiate lane alignment operations in response to detecting such impairments.

Abstract: Multiple media devices are synchronized in a multi-media system having a computer system, a plurality of media devices, and a display system. Each media device to be synchronized receives a front-end synchronization signal that periodically increments a front-end counter. The front-end counter represents an unadjusted system time (UST). The media device obtains a frame of data to be displayed from a computer system. The media device also receives a back-end synchronization signal that periodically increments a back-end counter each time a frame of data is to he displayed. The back-end counter represents a media stream count (MSC). UST and MSC data are periodically transmitted to the computer system for analysis and use by a synchronization algorithm. Specifically, UST is transmitted to the computer system each time a frame of data is obtained, and a UST/MSC pair is transmitted to the computer system each time a frame of data is displayed.

Abstract: The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is entirely digital and usable in any multi-link transceiver implementation that makes use of a separate clock link and requires timing synchronization between the different data links.

Abstract: An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths are arranged and operated so as to control the power consumption and data skew properties of the system. A configurable switching element may be used to form the interconnections at nodes, where a control signal and other information is used to manage the power status of other aspects of the configurable switching element. Time delay skew of data being transmitted between nodes of the network may be altered by exchanging the logical and physical line assignments of the data at one or more nodes of the network. A method of laying out an interconnecting motherboard is disclosed which reduces the complexity of the trace routing.

Abstract: Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for such skew, an on-chip delay is added to the data out paths of those bits in the byte lane with otherwise would arrive early to their destinations. Such on-chip delay is provided delay circuits preferably positioned directly before the output buffers/bond pads of the integrated circuit or module. By intentionally delaying some of the outputs from the integrated circuit or module, external skew is compensated for so that all data in the byte lane arrives at the destination at substantially the same time. In a preferred embodiment, the delay circuits are programmable to allow the integrated circuit or module to be freely tailored to environments having different skew considerations, such as different styles of connectors.

Abstract: A semiconductor device performs operation in synchronization with a certain clock signal. The semiconductor device includes a control unit for outputting operation control information, a storage unit for storing data, a first operation unit for performing operation on first data in accordance with first operation control information, and a second operation unit for performing operation on second data in accordance with second operation control information. The first operation unit includes a plurality of operation circuits. The number of logic gates constituting the entire operation circuits is m. The second operation unit includes at least one operation circuit in which the number of logic gates is n (n>m). Each of the total delay of the operation unit or the total delay of the operation unit is set at a value equal to or less than the cycle of the clock signal.

Abstract: A method for encoder frequency-shift compensation includes determining frequency values of an input encoder signal, determining repeatable frequency-shifts of the frequency values and generating a frequency-shift compensated clock using the repeatable frequency-shifts. A frequency-shift compensated clock includes a synthesizer configured to generate a frequency-shift compensated clock signal using repeatable frequency shifts and encoder clock signals.

Abstract: An apparatus is provided for generating a timing signal having an input for receiving a first signal indicating successive time intervals, means for receiving a second signal indicating successive time intervals, and a generator adapted to generate a timing signal based on the second signal and on a relationship between one or more time intervals of the first signal and one or more time intervals of the second signal. This arrangement enables a timing signal to be generated using a time signal produced by a source or device and to be based on a time signal produced by another source or device.

Abstract: In many cases, processors may change frequency sufficiently often to result in significant performance and power consumption losses. These performance and power consumption losses may be mitigated by changing the frequency using a squashing technique rather than using a phase locked loop technique. The squashing technique involves simply eliminated clock pulses to reduce the frequency. This can be done more quickly, resulting in less overhead in some cases.

Abstract: A processor based system with at least one processor, at least one memory controller and optionally other devices having bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch.

Abstract: Methods and systems for determining a memory access time are provided. A first phase skew is measured between a first clock signal used by a memory and a second clock signal used as a reference clock signal. Then, a second phase skew is measured between a delayed version of the first clock signal output by the memory when the memory completes a given read operation and the second clock signal. The memory access time is determined based on the first and second phase skews.

Abstract: Techniques are described for synchronizing multiple time-based data streams with independent clocks wherein relationships between clock rates of timing devices associated with the time-based data streams are determined, and based on these relationships, times in at least one of the time-based data streams may be translated to times in any of the other time-based data streams despite the data streams having independent clocks.

Abstract: Example systems, apparatus, and methods receive audio information including a plurality of frames from a source device, wherein each frame of the plurality of frames includes one or more audio samples and a time stamp indicating when to play the one or more audio samples of the respective frame. In an example, the time stamp is updated for each of the plurality of frames using a time differential value determined between clock information received from the source device and clock information associated with the device. The updated time stamp is stored for each of the plurality of frames, and the audio information is output based on the plurality of frames and associated updated time stamps. A number of samples per frame to be output is adjusted based on a comparison between the updated time stamp for the frame and a predicted time value for play back of the frame.

Abstract: An apparatus that compensates for misalignment on a synchronous data bus, including a resistor network, a transmitting device, and a receiving device. The resistor network indicates an amount to advance a synchronous data strobe associated with a data group. The transmitting device has a core clocks generator and a synchronous strobe driver. The core clocks generator advances a data strobe clock by the amount. The synchronous strobe driver employs the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe is advanced also by the amount. The receiving device has a composite delay element and delay-locked loops (DLLs). The composite delay element equalizes delay paths within the receiving device, where the delay paths correspond to the synchronous data strobe that is received from the transmitting device.

Abstract: An embedded multimedia card (eMMC) communicating with a host includes; a latch circuit that receives and latches a data signal according to either a first edge or a second edge of a clock to thereby generate a latched data signal, and a start bit detector that detects in the latched data signal a start bit and provides a valid data signal from a portion of the latched data signal following the start bit.

Abstract: An apparatus for generating a delayed clock signal. The apparatus is a computer system with a processor to which a memory device is coupled. The memory device has a delay clock generator that has a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.

Abstract: A method of determining a timing relationship between modules on a chip, each module being timed by an initiator. The timing relationship being determined on the basis of the power consumptions over time of the initiators and may be determined on the basis of e.g. a sum of the power consumptions or more complex calculations also incorporating the signal path or power delivery network, whereby a voltage drop or current drawn at a position in the chip may be determined. In addition, a parameter, which may be the sum or voltage drop, current or e.g. an energy content within a frequency range, may be determined. This parameter may be varied by e.g. providing different timing relations of initiators, in order to minimize the parameter or adapt it to a requirement as a maximum peak value, maximum difference between max and min peaks, a flatness criteria or the like.

Abstract: A circuit for trimming an internal oscillator of a USB device that generates a clock signal as a frequency source of the USB device includes a counter, a first detector for detecting an end of packet from an input data stream to initialize a counter, a second detector for detecting a synchronization sequence, a token packet or a handshake packet in the data stream for the counter to carry out clock counting on the clock signal, and a trimming code controller for comparing the count value with a reference value to determine a trimming code for trimming a clock frequency of the internal oscillator.

Abstract: A circuit includes a phase detector circuit, a phase frequency detector circuit, a data detection circuit, a multiplexer circuit, and a clock signal generation circuit. The phase detector circuit is operable to generate a first phase detection signal based on a data signal and a first periodic signal. The phase frequency detector circuit is operable to generate a second phase detection signal based on second and third periodic signals. The data detection circuit is operable to generate a data detection signal based on the first phase detection signal. A multiplexer circuit is operable to provide one of the first and the second phase detection signals as a selected signal based on the data detection signal. The periodic signal generation circuit is operable to cause adjustments to phases of the first and the second periodic signals based on the selected signal.

Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a training signal. For instance, the method can include configuring the memory device in a training mode of operation. The method can also include determining a write timing window between a signal on a data bus and a write clock signal based on the training signal. Further, the method includes adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.

Abstract: This invention relates to methods and devices for clock offset and skew estimation. The invention has particular application in the alignment of slave clocks to a master clock. In embodiments of the invention, the slave clock employs an independent free running clock and a recursive estimation technique to estimate the clock offset and clock skew between the slave and master clocks. The slave can then use the offset and skew to correct the free running clock to reflect an accurate image of the master clock.

Abstract: A method of providing a synchronization channel to a SuperSpeed USB device is provided. The method including a SuperSpeed communication channel connection to the SuperSpeed USB device with a USB cable that has USB 2.0 D+ and D? data signalling lines disabled or disconnected at an upstream connection point; multiplexing synchronization information onto the D+/D? data signalling lines at the upstream connection point; and demultiplexing the synchronization information from the D+/D? signalling lines at a downstream connection point of the cable; whereby the synchronization channel is maintained across the D+/D? data signalling lines.

Abstract: A method performs statistical static timing analysis of a network that includes a phase-locked loop and a feedback path. The feedback path comprises a set of delays operatively connected from the output of the phase-locked loop back to the input of the phase-locked loop. One embodiment herein computes a statistical feedback path delay for the feedback path. The method can use a separate statistical parameter to represent random uncorrelated delay variation for each delay in the feedback path. The method also computes an output arrival time for the phase-locked loop based on the negative of the statistical feedback path delay.

Abstract: A method of tuning a phase of a clock signal includes performing data training on a plurality of data pins through which data are input and output, in synchronization with a data clock signal; determining one of the data pins to be a representative pin; performing clock and data recovery (CDR) on read data of the representative pin; and adjusting a phase of the data clock signal based on the CDR.

Abstract: Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for such skew, an on-chip delay is added to the data out paths of those bits in the byte lane with otherwise would arrive early to their destinations. Such on-chip delay is provided delay circuits preferably positioned directly before the output buffers/bond pads of the integrated circuit or module. By intentionally delaying some of the outputs from the integrated circuit or module, external skew is compensated for so that all data in the byte lane arrives at the destination at substantially the same time. In a preferred embodiment, the delay circuits are programmable to allow the integrated circuit or module to be freely tailored to environments having different skew considerations, such as different styles of connectors.

Abstract: A slave device communicating with a master device includes a transmission unit configured to transmit a signal to the master device through a communication channel, a calibration unit configured to measure a flight time of a calibration signal which is transmitted to the master device and fed back through a calibration channel coupled to the master device, and a transmission delay unit configured to delay the signal transmitted from an internal circuit of the slave device to the transmission unit by a delay value determined according to the measurement result of the calibration unit.

Abstract: Methods and structure for on-chip self-test of clock jitter for an application clock signal generated within an integrated circuit (IC). Features and aspects hereof provide for acquisition of samples of an application clock signal within the IC and counting the number of samples having a predetermined value. The count is compared to acceptable limits range values to generate a pass/fail signal of the IC use by external automated. A sample clock is generated based on the reference clock used by a Phase Locked Loop (PLL) circuit. An incremental delay is added to the sample clock pulse such that the sequence of samples “walk” through an application clock pulse waveform to sense clock jitter at various points of the waveform based on the counts. Acceptable limits range for the count at each sampled point, the incremental delay, and the number of samples at each delayed value may be user programmed.

Abstract: Synchronization of two or more items can be optimized through the use of parallel execution of synchronization tasks and adaptable processing that monitors and adjusts for system loading. Two or more synchronization tasks required to be performed for an item can, if not inherently serial in nature, be performed in parallel, optimizing synchronization of the item. Even if multiple synchronization tasks required for one item must be serially executed, e.g., download the item prior to translating the item, these synchronization tasks can be executed in parallel for different items, optimizing a download request involving two or more items. Moreover, multiple threads for one or more synchronization tasks can be concurrently executed when supportable by the current operating system resources. Rules can be established to ensure synchronization activity is not degraded by the overextension of system resources.

Abstract: This invention provides an image forming apparatus that suppresses a control error between CPUs when the CPUs operate in cooperation with each other in distributed control by the CPUs. To accomplish this, the image forming apparatus utilizes a distributed control system. Respective CPUs measure time interval concerning image formation processing using their built-in clock oscillators, and perform operations in cooperation with each other. Correction coefficients are calculated based on the time interval measured by the respective CPUs to correct a measurement error generated by the operation an error of the respective clock oscillators. Clock count values each indicating a timing to drive a load is corrected based on the correction coefficients.

Abstract: Systems, methods, and other embodiments associated with selective shorting are described. According to one embodiment, an apparatus includes a selective shorting device connected between clock branches. The selective shorting device is configured to selectively electrically connect the clock branches to one another and to selectively electrically disconnect the clock branches from one another. The apparatus also includes a selective shorting control mechanism that controls the selective shorting device to electrically connect the clock branches during a controlling portion of a clock signal. The selective shorting control mechanism is configured to electrically disconnect the clock branches in the absence of the controlling portion.

Abstract: Methods and apparatus are provided for burst transfers of data between DDR memories and embedded processors during training of the PHY interface in an embedded system. An embedded system comprises an embedded processor having at least one cache controller; a memory, wherein the memory has an atomic memory access that comprises a plurality of clock edges; and a memory controller having a physical interface to convert digital signals between the embedded processor and the memory, wherein the cache controller executes a training process to determine a delay through the physical interface for each of the plurality of clock edges using a burst transfer of data. The burst transfer comprises reading a data pattern from the memory and storing the data pattern in one or more registers in the embedded processor.

Abstract: For predicting timing violations, a prediction module predicts a timing violation for a first instruction in a semiconductor device in response to use by the first instruction of a specified sensitized path. The prediction module further mitigates the predicted timing violation.

Abstract: A system and method for synchronizing multiple backplanes within an information handling system are disclosed. An information handling system includes a first controller that may be operable to generate a time command at a predetermined time interval. A backplane including a second controller is communicatively coupled to the first controller. The second controller may be operable to receive the time command from the first controller and calculate a skew for the time command based at least on a location of the backplane. The second controller may further be operable to adjust a time domain of the backplane based on the calculated skew for the time command to synchronize the backplane.

Abstract: A method is described for performing an automatic internal trimming operation that can compensate process variation and supply voltage variation in an integrated circuit. A reference signal is applied when the integrated circuit is in an automatic internal trimming mode, and integrated circuit timing is trimmed into a predetermined target range after applying predefined reference cycles.

Abstract: A circuit and method for trimming an internal oscillator of a USB device that generates a clock signal as a frequency source of the USB device detect an end of packet from an input data stream to initialize a counter, identify a token packet in the data stream to detect a start of frame token packet for the counter to carry out clock counting on the clock signal to thereby obtain a count value, and compare the count value with a reference value to determine a trimming code for trimming a clock frequency of the internal oscillator.

Abstract: The rate at which data is provided by one device and the rate at which that data is processed by another device may differ. For example, a transmitting device may transmit data according to a transmit clock while a receiving device that receives the transmitted data may process the data according to a receive clock. If there is a timing mismatch between the transmit and receive clocks, the receiving device may receive data faster or slower than it processes the data. In such a case, there may be errors relating to the processing of the received data. To address timing mismatches such as this, the receiving device may delete data from or insert data into the received data. In conjunction with these operations, the receiving device may modify the received data at or near the insertion point or the deletion point in a manner that mitigates any adverse effect the insertion or deletion may have on a resulting output signal.

Abstract: A performance scaling device, a processor having the same, and a performance scaling method thereof are provided. The performance scaling device includes an adaptive voltage scaling unit, a latency prediction unit, and a variable-latency datapath. The adaptive voltage scaling unit generates a plurality of operation voltages and transmits the operation voltages to the variable-latency datapath. The variable-latency datapath operates with different latencies according to the operation voltages and generates an operation latency. The latency prediction unit receives the operation latency and a system latency tolerance and generates a voltage scaling signal for the adaptive voltage scaling unit according to the operation latency and the system latency tolerance. The adaptive voltage scaling unit outputs and scales the operation voltages thereof according to the voltage scaling signal.

Abstract: A timing recovery controller capable of performing timing recovery for a data sequence at twice a symbol rate includes a sampler, a timing base device, a timing error detector and a timing lock detector. The timing error detector includes a first delay unit and a second delay unit, for delaying a data sequence to output a first delay data sequence and a second delay data sequence, respectively, and a timing error calculating module, for generating a timing error value, to adjust a time base. The timing lock detector includes a third delay unit, for delaying the data sequence to output a third delay data sequence, and a timing lock determination module, for generating a timing lock determination result.

Abstract: A memory component has a signaling interface, data input/output (I/O) circuitry and command/address (CA) circuitry. The signaling interface includes an on-die terminated data I/O and an unterminated CA input. The data I/O circuitry is dedicated to sampling write data bits at the data I/O timed by a strobe signal and to transmitting read data bits timed by a first clock signal, each of the write and read data bits being valid for a bit time at the data I/O. The CA circuitry samples CA signals at the CA input in response to both rising-edge and falling-edge transitions of a second clock signal, the CA signals indicating read and write operations to be performed within the memory component.

Abstract: Method is described for converting received timestamps to a time-recording standard recognized by the receiving computing system. Embodiments of the invention generally include receiving data from an external device that includes a timestamp. If the received data is the first communication from the external device, creating a time base used for converting subsequently received timestamps to a recognized standard. Moreover, the system updates the time base if a counter failure at the external device is detected. When the external device transmits subsequent data, the time base is added to the subsequently received timestamps to convert the subsequent timestamps to a time-recording standard recognized by the computing system.

Abstract: A clock circuit is suitable for use in a timing circuit which provides time information according to a reference clock. The clock circuit includes a clock detector to detect whether or not an interruption of the reference clock occurs. When the interruption of the reference clock occurs, a clock interruption signal is issued as a reference whether or not to reset the timing circuit.

Abstract: Method, apparatus and system are described for converting received timestamps to a time-recording standard recognized by the receiving computing system. Embodiments of the invention generally include receiving data from an external device that includes a timestamp. If the received data is the first communication from the external device, creating a time base used for converting subsequently received timestamps to a recognized standard. Moreover, the system updates the time base if a counter failure at the external device is detected. When the external device transmits subsequent data, the time base is added to the subsequently received timestamps to convert the subsequent timestamps to a time-recording standard recognized by the computing system.

Abstract: An arithmetic processing device includes: a communicating unit that communicates with another arithmetic processing device; a clock controller that requests a change in the frequency of a clock signal; a sequence controller that instructs the other arithmetic processing device to change the amount of data to be transmitted by the other arithmetic processing device to the arithmetic processing device per unit time when the sequence controller is requested by the clock controller to change the frequency of the clock signal; and a control circuit that changes the amount of data to be transmitted by the communicating unit to the other arithmetic processing device per unit time when the other arithmetic processing device instructs the arithmetic processing device to change the amount of data to be transmitted by the arithmetic processing device to the other arithmetic processing device per unit time.

Abstract: A dynamic clock frequency module includes a request evaluation module configured to generate a sum of requests to utilize a system bus from a plurality of modules. A frequency assignment module is configured to calculate a clock frequency for the system bus in response to the requests and adjust the clock frequency between at least two non-zero frequency values. A pulse stretch module is configured to increase a period of time that at least one of the requests is asserted in response to the sum.