Abstract: A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section formed by connecting logic devices in series corresponding to a number of logic devices included in a clock signal path between a clock signal source and the latch circuit data input. The delay circuit also includes a second delay section having a delay time equal to an interconnect delay time corresponding to a wiring length of the clock signal path.

Abstract: A system and method is disclosed for managing power consumption in a computing device. A policy controller determines whether an aggregated power consumption of a plurality of external interface controllers in a computing device is greater than a policy power limit. On determining that the aggregated power consumption is greater than the policy power limit, the policy controller may set a first external interface controller at a negotiated power level, and set a second external interface controller at an adjusted power level, wherein the first external interface controller and the second external interface controller are set based on the policy power limit and the aggregated power consumption.

Abstract: The present image forming apparatus includes a first control unit and a second control unit driven by built-in clock oscillators to realize the distributed control. The first control unit generates, using a first timer driven by the built-in clock oscillator of the first control unit, a pulse signal corresponding to a predetermined clock rate and outputs the pulse signal to the second control unit. The second control unit measures, using a second timer driven by the built-in clock oscillator of the second control unit, a pulse width of the pulse signal outputted from the first control unit, and calculates a correction coefficient using reference pulse width corresponding to the predetermined clock rate and the measured pulse width. The processing unit processes using the calculated correction coefficient.

Abstract: A data processing unit has a time information provider for processing a clock or a strobe signal, configured to provide a digitized clock or strobe time information on the basis of the clock or strobe signal and at least one data extraction unit, coupled to the time information provider and configured to select data from a sequence of data samples of a data signal depending on the digitized clock or strobe time information.

Abstract: In calibration mode, a clock signal and a data signal are respectively transmitted via a clock lane and a data lane of an MIPI. A test clock signal is provided by adjusting the phase of the clock signal, and a test data signal is provided by adjusting the phase of the data signal. By latching the test data signal according to the test clock signal, a latched data may be acquired for determining an optimized phase relationship corresponding to the clock lane and the data lane. When transmitting the clock signal and the data signal in normal mode, the signal delays of the clock lane and the data lane may be adjusted according to the optimized phase relationship.

Abstract: A system for compensating for periodic noise in a time interleaved system having multiple phases of interest includes a master clock path, a detection circuit and an actuator circuit. The master clock path is configured to receive an input clock and to output an output clock, each of the input and output clocks having periodically occurring interleaving periods. Each interleaving period includes timeslots corresponding to the phases of interest of the time interleaved system. The detection circuit is configured to receive the input and output clocks for each timeslot, and to detect periodic noise in the output clock introduced by the master clock path by comparing the received input and output clocks. The actuator circuit includes a controllable delay element configured to adjust a delay of the input clock through the master clock path to compensate for the periodic noise detected by the detection circuit for each timeslot.

Abstract: Systems and methods for providing resource management in a distributed network are disclosed. A loose collection of devices in a network may not be aware of the power restrictions for other devices. Wall powered devices will generally have drastically different power settings than battery powered mobile devices. The invention provides a federation policy for time that can be used to slave to a local service responsible for understanding the local resource requirements of each device (or node) on the network. In such a distributed time system, all services in a particular time domain may be sped up, slowed down, or completely halted.

Abstract: Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.

Abstract: A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section formed by connecting logic devices in series corresponding to a number of logic devices included in a clock signal path between a clock signal source and the latch circuit data input. The delay circuit also includes a second delay section having a delay time equal to an interconnect delay time corresponding to a wiring length of the clock signal path.

Abstract: A device comprises an integrated circuit having first and second domains, the first domain having a first clock boundary module; and the second domain having a second clock boundary module. The first clock boundary module comprises: a buffer, for storing data for transfer to the second domain; and a first controller operable to send a first control signal to the second clock boundary module via a first synchronizer, the first control signal indicating the presence of a packet of data in a first storage location of the buffer. One of the first and second clock boundary modules comprises a multiplexer having an input connected to an output of the buffer and an output connected to circuitry forming part of the second domain.

Abstract: A monitoring circuit for an integrated circuit comprises a non-temperature-inverted circuit and a temperature-inverted circuit. Operating parameters of the two circuits are measured, representing the propagation speed of signals in the respective circuits. In response to a change in temperature, the non-temperature-inverted circuit slows down and the temperature-inverted circuit speeds up. In contrast, in response to a change in operating voltage both circuits either speed up or slow down. This divergence in response to temperature and similar response to voltage enables the monitoring circuit to distinguish between changes in operating voltage and changes in operating temperature.

Abstract: A skew adjustment circuit, provided in an integrated circuit device having a plurality of signal lines transmitting a plurality of signals respectively, and a plurality of buffer circuits to which a plurality of signals transmitted through the signal lines are respectively input, has: a plurality of delay circuits, respectively provided in stages preceding the buffer circuits; a monitoring circuit monitoring changes in the signals of the plurality of signal lines; and a delay adjustment circuit, which decides delay amounts for the plurality of delay circuits based on a monitoring result output of the monitoring circuit, and sets the delay amounts in the plurality of delay circuits. The monitoring circuit detects, as the monitoring result, a number of signal changes in the signal lines in which a signal change occurs in a monitoring period, and the delay adjustment circuit decides the delay amounts based on the number of signal changes.

Abstract: Systems and methods are disclosed for precise generation of phase variation in digital signals. The disclosed signal generation embodiments generate a pattern of information bits that represents a digital signal with desired phase variations and transmit this digital pattern at high speed utilizing a serializer to generate a high speed bit stream. The high speed bit stream can be used to generate one or more digital signals, such as clock signals, having desired rates and desired phase variations. In certain embodiments, the desired phase variation can be introduced into the resulting digital signal by removing and/or inserting bits in a digital pattern thereby moving logic transitions (e.g., rising edge transitions, falling edge transitions) as desired within the resulting digital signal. In addition to clock signals, the resulting digital signals generated can be control signals, data signals and/or any other desired digital signal.

Abstract: A method for calibrating a DDR memory controller is described. The method provides an optimum delay for a core clock delay element to produce an optimum capture clock signal. The method issues a sequence of read commands so that a delayed version of a dqs signal toggles continuously. The method delays a core clock signal to sample the delayed dqs signal at different delay increments until a 1 to 0 transition is detected on the delayed dqs signal. This core clock delay is recorded as “A.” The method delays the core clock signal to sample the core clock signal at different delay increments until a 0 to 1 transition is detected on the core clock signal. This core clock delay is recorded as “B.” The optimum delay value is computed from the A and B delay values.

Abstract: One embodiment provides an information processing device which includes a clock unit, a file access unit and a setting unit. The clock unit is configured to count up an elapsed time from a prescribed reference time if an origin time has not been set, and to count up an elapsed time from the origin time if the origin time has been set. The file access unit is configured to access a file which has time information given by an external device or the information processing device. The file is stored in a storage device. The setting unit is configured to acquire the time information from the file via the file access unit, and to set the acquired time information into the clock unit as the origin time.

Abstract: A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.

Abstract: A circuit and method of analog data acquisition synchronization from an analog sensor in multiple channels associated with a USB hub. An analog to digital converter connected to the sensor that is part of a USB device has a time and phase corrected sampling clock that is referenced to a start-of-frame traffic signal with a preconfigured message indicating a time offset or delay seen upstream through a USB port. A plurality of similar devices are autonomously synchronized by the same message for multi-channel data acquisition by a locally generated trigger signal that allows a preset amount of delay set by the message. An accelerometer is a preferred sensor for such multi-channel data acquisition.

Abstract: A memory card includes a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a clock signal, and a memory-side pattern signal storage unit configured to store a tuning pattern signal to be sent to a host device. The tuning pattern signal is used by the host device to adjust the phase of the clock signal for use as a sampling clock signal. The memory card sends a first tuning pattern signal through a command line and a second tuning pattern signal through a data line concurrently.

Abstract: An apparatus including a JTAG interface, synchronous bus optimizer, core clocks generator, synchronous strobe driver, and a DLL. The JTAG interface receives control information indicating a first amount to advance a synchronous data strobe associated with a first data group and a second amount to delay a data bit signal associated with a second data group. The synchronous bus optimizer receives the control information, and develops a first value on a first ratio bus that indicates the first amount and a second value on a second ratio bus that indicates the second amount. The core clocks generator advances a data strobe clock by the first amount. The synchronous strobe driver employs the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the first amount. The DLL generates a delayed data bit signal, delayed by the second amount.

Abstract: A semiconductor device includes an internal circuit configured to perform a specified operation in response to a predetermined command; a normal data input/output section configured to input/output a normal data synchronized with a center of a source clock, in response to data input/output commands; and a data recovery information signal input/output block configured to receive and store a data recovery information signal synchronized with an edge of the source clock and having a predetermined pattern, in response to either a command of the data input/output commands or the predetermined command upon entry to a data recovery operating mode, and to output the data recovery information signal after the passage of a predetermined time period.

Abstract: A frequency tracking circuit is disclosed. The frequency tracking circuit includes an edge selector, a phase-frequency processor and a digital controlled oscillator. The edge selector receives a data signal and feedback clock signal and sequentially outputs a data edge signal and a feedback-clock-edge signal. The phase-frequency processor receives the data edge signal and the feedback-clock-edge signal and outputs a frequency adjusting digital signal after executing differential operation according to a first phase difference and a second phase difference. The digital controlled oscillator receives the frequency adjusting digital signal so as to adjust frequency of the feedback clock signal. The phase-frequency processor outputs a frequency tracking signal to the edge selector, wherein the edge selector utilizes the frequency tracking signal for acquiring the data edge signal and utilizes the data edge signal for acquiring the feedback-clock-edge signal.

Abstract: A apparatus is provided for buffering data between a memory controller and a DRAM. The apparatus includes a phase locked loop (PLL), a phase interpolator for aligning a phase of an output clock signal in response to a phase aligning control word, and a non-volatile storage location permanently storing the phase aligning control word. The phase aligning control word is determined through an initial training procedure of the device under predetermined training conditions of at least a supply voltage level and a temperature, and the predetermined training conditions are set so as to optimize the phase alignment of an edge of the output clock signal with respect to the buffered data signal.

Abstract: An apparatus for synchronizing a data handover is disclosed. The calculator is clocked with a clock of a first clock domain and configured to provide synchronization pulse cycle duration information describing a temporal position of a synchronization pulse at a clock of the second clock domain. The synchronization pulse generator is clocked with the clock of the second clock domain and configured to generate the synchronization pulse such that the synchronization pulse is located at the temporal position described by the synchronization pulse cycle duration information. The phase information provider is clocked with the clock of the second clock domain and configured to provide a phase information describing a phase relation between the synchronization pulse and the clock of the first clock domain. The feedback path is configured for feeding back the phase information to the calculator and to adjust the synchronization pulse cycle duration information based on the phase information.

Abstract: A clock signal is transmitted to first and second integrated circuit (IC) components via a clock signal line, the clock signal having a first arrival time at the first IC component and a second, later arrival time at the second IC component. A write command is transmitted to the first and second IC components to be sampled by those components at respective times corresponding to transitions of the clock signal, and write data is transmitted to the first and second IC components in association with the write command. First and second strobe signals are transmitted to the first and second IC components, respectively, to time reception of the first and second write data in those components. The first and second strobe signals are selected from a plurality of phase-offset timing signals to compensate for respective timing skews between the clock signal and the first and second strobe signals.

Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Abstract: According to one embodiment, a memory access circuit includes a PLL, a phy-clock tree, first, second, and master DLLs, and first and second PDs. The PLL generates a PLL output locked to a reference frequency. The phy-clock tree delays the PLL output and generates a reference clock signal. The first DLL corrects a clock skew between reference and system clock signals, and generates a source of the system clock signal. The second DLL corrects a clock skew between reference clock and phy-clock signals, and generates a source of the phy-clock signal. The first and second PDs detect a phase difference, and generate first and second detection signals. The master DLL counts the reference clock signal and generates a delay correction signal. The first and second DLLs determine a correction direction and a correction amount based on first and second detection and delay correction signals, respectively.

Abstract: One embodiment relates an apparatus which includes a plurality of local synchronous divider circuits, each local synchronous divider circuit being configured to receive a serial clock signal and a reset signal and generate a local clock signal. The apparatus further includes a clock distribution network configured to distribute the serial clock signal to the plurality of local synchronous divider circuits and a signal distribution network configured to distribute the reset signal to the plurality of local synchronous divider circuits. Another embodiment relates to a method of distributing a serial clock signal and a reset signal to a plurality of local synchronous divider circuits and generating a local clock signal at each of the plurality of local synchronous divider circuits. Other embodiments, aspects, and features are also disclosed.

Abstract: One embodiment of the present invention sets forth a technique for performing high-performance clock training. One clock training sweep operation is performed to determine phase relationships for two write clocks with respect to a command clock. The phase relationships are generated to satisfy timing requirements for two different client devices, such as GDDR5 DRAM components. A second clock training sweep operation is performed to better align local clocks operating on the client devices. A voting tally is maintained during the second clock training sweep to record phase agreement at each step in the clock training sweep. The voting tally then determines whether one of the local clocks should be inverted to better align the two local clocks.

Abstract: An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.

Abstract: A modulated clock device is provided that includes an update device for updating a phase of the modulated clock device. In one example, the update device includes an update phase multiplexer coupled to an output phase multiplexer of an output clock generator and configured to receive an input clock signal and one or more phases of the input clock signal; an output phase fractional counter coupled to the update phase multiplexer and configured to receive an update clock signal and to generate an output phase; and an update phase device coupled to the output phase fractional counter and to the update phase multiplexer. The output phase fractional counter is further configured to send the output phase to the output phase multiplexer and to the update phase device. The update phase device is configured to generate an update phase and to send the update phase to the update phase multiplexer.

Abstract: A method for restoring stability to an unstable bus includes cycling a clock of the bus a number of times, transmitting a stop bit, cycling a clock line of the bus at least one time and transmitting a stop bit immediately after an acknowledgment bit has been received by a bus master.

Abstract: Methods of operating timers include generating a periodic timing signal having a first frequency that differs from a desired timer frequency (1 KHz) by a first amount. This periodic timing signal having the first frequency can be generated by dividing a frequency of an input clock signal (e.g., 32.768 KHz) by N, where N is a positive integer greater than one. A typical value of N may be 32. The methods also include techniques to inhibit timing error accumulation by switching a frequency of the periodic timing signal from the first frequency to a second frequency that differs from the desired timer frequency by a second amount. This periodic timing signal having the second frequency can be generated by dividing the frequency of the input clock signal by M, where M is a positive integer unequal to N (e.g., M?N equals ±1).

Abstract: A network device of a communication network is configured to implement coordinated scheduling and processor rate control. In one aspect, packets are received in the network device and scheduled for processing from one or more queues of that device. An operating rate of a processor of the network device is controlled based at least in part on an optimal operating rate of the processor that is determined using a non-zero base power of the processor. For example, the operating rate of the processor may be controlled such that the processor either operates at or above the optimal operating rate, or is substantially turned off. The optimal operating rate of the processor may be selected so as to fall on a tangent line of a power-rate curve of the processor that also passes through an origin point of a coordinate system of the power-rate curve.

Abstract: Within a system of integrated circuit devices, first and second signals are transmitted intermittently from a first integrated circuit device to a second integrated circuit device. The second integrated circuit device generates a timing signal based on transitions of the second signal and generates samples of the first signal in response to transitions of the timing signal. The second integrated circuit device further generates timing error information based on the samples of the first signal, the timing error information to enable adjustment of the relative phases of the timing signal and the first signal.

Abstract: A method for adjusting clock skew in a network is disclosed. A model is fit to a first clock input signal received at a first receiver of the network and to a second clock input signal received at a second receiver of the network to obtain a fitted model. A first response signal is simulated using the fitted model and the first clock input signal and a second response signal is simulated using the fitted model and the second clock input signal. A time difference is determined between the simulated first response signal and the simulated second response signal. A parameter of at least one of the network clock network, the first receiver and the second receiver is altered to adjust the determined time difference.

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network, a core clocks generator, and a synchronous strobe driver. The resistor network is configured to provide a ratio signal that indicates an amount to advance a synchronous data strobe associated with a data group. The core clocks generator is coupled to the ratio signal, and is configured to advance a data strobe clock by the amount. The synchronous strobe driver is configured to receive the data strobe clock, and is configured to employ the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the amount.

Abstract: An apparatus that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network and a synchronous receiver disposed within a receiving device. The resistor network is configured to provide a ratio signal that indicates an amount to delay a data bit signal associated with a data group, where the data bit signal is transmitted by a transmitting device along with a data strobe signal. The synchronous receiver receives the data bit and the data strobe signals, and includes a delay-locked loop (DLL). The DLL is coupled to the ratio signal, and is configured generate a delayed data bit signal, where the DLL adds the amount of delay to the data bit signal to generate the delayed data bit signal, and where the delayed bit signal is delayed relative to the data strobe signal by the amount, thus allowing for proper reception of the data bit signal.

Abstract: A skew adjusting apparatus includes: latching circuits that latch other signals in synchronism with transition timing of the signal level of a reference signal among signals transmitted with a plurality of communication cables; delay elements that are provided on the plurality of communication cables, and delay the signals transmitted with the plurality of communication cables, respectively; and a controller that controls the delay elements based on the outputs of the latching circuits to adjust skews between the signals.

Abstract: A method for synchronizing two connection nodes by a reception node of the connection nodes with a clock data recovery circuit that generates a synchronization clock from input data. The method includes performing a synchronization process to establish synchronization between the connection nodes based on the synchronization clock, performing a connection failure process when the synchronization is not established when a first time elapses after receiving the input data, correcting the clock data recovery circuit when the synchronization is not established when a second time elapses after receiving the input data, wherein the second time is shorter than the first time, and performing a resynchronization process to establish synchronization between the connection nodes based on a synchronization clock, which is generated by the clock data recovery circuit that has been corrected, before the first time elapses and after the second time elapses.

Abstract: Asynchronous digital circuits are described, including arbitration and routing primitives for asynchronous and mixed-timing networks. An asynchronous arbitration primitive has two data inputs and one data output. A mutual exclusion element is used to select the first-arriving data request from one of the two inputs to the output. A asynchronous routing primitive has one data input and two data outputs. The incoming data is routed to one of the two outputs based on a routing bit accompanying the data. The primitives use handshaking with request and acknowledge signals to ensure that data is passed when neighboring circuits are ready to receive or send data.

Abstract: An improved approach is described for implementing a clock management system. A multi-part phase locked loop circuit is provided to handle the different clock needs of the circuit, where each of the phase locked loops within the multi-part phase locked loop circuit may feed a clock output to one or more divider circuits. The divider circuits may be dedicated to specific components. For example, a SoC PLL may generate a clock output to a SoC divider that is dedicated to providing a clock to content address memory (CAM) components. This approach allows the clock management system to efficiently generate clock signals with variable levels of frequencies, even for complicated circuits having many different functional portions and components.

Abstract: A memory module may have a redrive circuit having a plurality of redrive paths, a memory device, and a deskew circuit. The deskew circuit may be separate from the plurality of redrive paths. The deskew circuit may be coupled between the plurality of redrive paths and the memory device to selectively deskew data received in the redrive circuit.

Abstract: An apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, a core clocks generator, and a synchronous strobe driver. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to advance a synchronous data strobe associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The core clocks generator is coupled to the ratio bus and is configured to advance a data strobe clock by the amount. The synchronous strobe driver is configured to receive the data strobe clock, and is configured to employ the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the amount.

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network, a composite delay element, and delay-locked loops (DLLs). The resistor network is configured to provide a ratio signal that indicates an amount to delay data bit signals associated with a data group. The composite delay element is configured to equalize delay paths within a receiving device, where the delay paths correspond to a data strobe signal that is received from a transmitting device. The receiving device and resistor network are coupled to a motherboard. The ratio signal enters said receiving device through an external pin. The DLLs are coupled to the ratio signal and disposed within the receiving device, and are configured to generate delayed data bit signals, where the DLLs add the amount of delay to the data bit signals to generate the delayed data bit signals.

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, and a delay-locked loop (DLL). The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to delay a data bit signal associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The DLL is coupled to the ratio bus, and is configured generate a delayed data bit signal, where the DLL adds the amount of delay to the data bit signal to generate the delayed data bit signal.

Abstract: A delay controller includes an acquiring section that acquires synchronization timings indicating timings when a plurality of controllers, which control via a line a plurality of transmitters that transmit data, synchronously control the transmitters, a determining section that determines a reference synchronization timing serving as a reference for synchronization between the controllers, on the basis of the synchronization timings acquired by the acquiring section, and a synchronization information transmitting section that transmits synchronization information to the controllers, the synchronization information being used when the controllers receive data from each of the transmitters at the reference synchronization timing determined by the determining section.

Abstract: The disclosed embodiments provide a system that facilitates synchronization between a first component and a second component connected to the first component via an interface in a computer system. During an active state of the interface, the system uses a local time base in the second component to generate a local clock signal that tracks a host clock signal from the first component. Next, during an inactive state of the interface, the system uses the local time base to maintain the local clock signal at the second component. Finally, during a subsequent active state of the interface after the inactive state, the system adjusts the local clock signal to remove clock drift between the local clock signal and the host clock signal.

Abstract: A data transmission system includes a plurality of signal lines, a signal line determination unit, and a data transmission unit. The plurality of signal lines transmit data transmitted from a transmission-side device to a reception-side device. The signal line determination unit determines which signal line among the signal lines is used to transmit reception adjustment data to the reception-side device. The data transmission unit uses the signal line determined by the signal line determination unit to transmit the reception adjustment data to the reception-side device and uses another signal line to transmit transmission data to the reception-side device.

Abstract: A method and a system are provided for speculative periodic synchronization. A phase value representing a measured phase of the second clock signal relative to the first clock signal measured at least one cycle earlier is received. A period value representing a period of the second clock signal relative to the first clock signal measured at least one cycle earlier is also received. A reduced timing margin is determined based on the phase value and the period value. A speculatively synchronized output signal is generated based on the reduced timing margin.

Abstract: A semiconductor device includes an internal circuit configured to perform a specified operation in response to a predetermined command; a normal data input/output section configured to input/output a normal data synchronized with a center of a source clock, in response to data input/output commands; and a data recovery information signal input/output block configured to receive and store a data recovery information signal synchronized with an edge of the source clock and having a predetermined pattern, in response to either a command of the data input/output commands or the predetermined command upon entry to a data recovery operating mode, and to output the data recovery information signal after the passage of a predetermined time period.