Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.

Abstract: A method for providing a logic synthesis of a pipeline circuit is disclosed. The method includes: providing a circuit design of the pipeline circuit, wherein the circuit design includes a first logic module as a current stage, and based on an operation of the first logic module, generating a first time marked graph (TMG) that corresponds to a plurality of behavioral phases of the first logic module, wherein the first TMG includes a plurality of vertexes and a plurality of edges, wherein each vertex corresponds to one of the plurality of behavioral phases that occur in sequence and each edge is coupled between two respective vertexes thereby corresponding to a transition from one behavioral phase to another subsequently occurring behavioral phase.

Abstract: A disclosed delay circuit includes a plurality of Schmitt triggers that are serially coupled. A first Schmitt trigger of the plurality of Schmitt triggers is configured to receive an input signal. An output control circuit is coupled to receive output signals of two or more Schmitt triggers of the plurality of Schmitt triggers, the output control circuit configured to select a signal from one of the one or more Schmitt triggers as an output signal. The output signal is a delayed version of the input signal.

Abstract: A system on chip is provided. The system on chip includes a delay control circuit configured to generate delayed clock signals having different delays, based on each of a first rising edge and a first falling edge of an input clock signal, and generate delayed data signals having different delays, based on each of a second rising edge and a second falling edge of an input data signal. The system on chip further includes a de-skew control circuit configured to control the delay control circuit to adjust a delay of each of the first rising edge, the first falling edge, the second rising edge, and the second falling edge.

Abstract: Provided is a periodic signal generation circuit including: a clock generation unit suitable for generating first to Nth clocks which have a basic period and have a phase increasing sequentially by a time interval obtained by dividing the basic period by “N”; a pulse generation unit suitable for generating first to Nth periodic pulses having an equal pulse width and having a phase increasing sequentially by a time interval obtained by dividing the basic period by “N” by combining two or more clocks among the first to Nth clocks; and a periodic signal generation unit suitable for generating a periodic signal by combining one or more periodic pulses among the first to Nth periodic pulses depending on combination information.

Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.

Abstract: Optimizing an I2C bus frequency, the bus including signal lines coupling a master and slave nodes, a signal line coupled to a rise time detection circuit monitoring a voltage of the signal line, the voltage alternating between a logic low and logic high, where optimizing the frequency includes: detecting, during a rise in the signal line, a first voltage, the first voltage being greater than the logic low voltage; starting a counter to increment once for each clock period of the circuit; detecting a second voltage on the signal line, the second voltage greater than the first and less than the logic high; stopping the counter; calculating, in dependence upon the clock period and the counter value, a rise time; determining whether the rise time is greater than a maximum threshold; and increasing the I2C bus frequency if the calculated rise time is greater than the maximum threshold.

Abstract: Implementations of the present disclosure involve an apparatus and/or method for adjusting a counter in a computing system to account for drift of the counter value over time compared to another counter of the system. In particular, a processor of the computing system that includes a local counter component may access a counter component of another processor of the system, referred to as the reference counter. By comparing the value of the reference counter to the local counter, the processor may determine any drift that may have occurred over a period of time in the local counter. The calculated drift, or counter error, may be converted into one or more adjustments to the local counter to synchronize the local counter with the reference counter. In one embodiment, the adjustment to the local counter includes increasing the rate at which the local counter is incremented for a period of time.

Abstract: The present invention discloses a method for fixing hold time violations in circuits. The method comprises: creating a topology diagram of the circuit with a branch indicating a signal path where the hold time violation occurs in the circuit, and a node on the branch indicating a port of an element where the hold time violation occurs; dividing the circuit into a plurality of regions; and placing a hold time correction element selectively in a region corresponding to the node in the topology diagram to fix the hold time violation thereof, according to a circuit element density of the region corresponding to the node in the topology diagram. With this method there will be no new element in a region whose circuit element density is excessively large, and it is unnecessary to move an element which has been placed in the circuit and an input/output pin thereof.

Abstract: Implementations of the present disclosure involve an apparatus and/or method for conducting simultaneous transition testing of different clock domains of a microprocessor design at different frequencies through a controlled order of clock pulses in each domain. In general, a microelectronic design utilizes test control circuitry associated with each clock domain of the design to conduct simultaneous transition testing of the clock domains. The testing control circuitry associated with each clock domain of the microelectronic design further allows for the testing device to delay testing within a particular clock domain. By delaying the testing within a particular clock domain, the testing of the various clock domains can be synchronized. Through these testing procedures, the amount of time required to perform the ATPG testing of a microelectronic design may be greatly reduced.

Abstract: A frequency calibration method applicable in a Universal Serial Bus device includes: plugging the Universal Serial Bus device to a Universal Serial Bus host; using the Universal Serial Bus device to receive a polling low frequency periodic signal generated from the Universal Serial Bus host; determining a host type of the Universal Serial Bus host according to the polling low frequency periodic signal; and calibrating a programmable oscillator of the USB device according to a specific clock period corresponding to the host type, to make the programmable oscillator generate a target oscillating signal having a predetermined frequency.

Abstract: A skew calibration circuit may include a data delay unit receiving first data and a first code, and output delayed first data as second data by delaying the first data according to the first code; a clock delay unit receiving a first clock signal and a second code, and output delayed first clock signal as second clock signal by delaying the first clock signal according to the second code; a multiplexer receiving a clock signal and output the clock signal or an inverted clock signal of the clock signal as a first clock signal in response to a selection signal; and a control logic unit receiving the second data and the second clock signal and control the first code, the second code and the selection signal in response to the second data and the second clock signal.

Abstract: An application processor includes a main central processing device that operates based on an external main clock signal received from at least one external clock source when the application processor is in an active mode, at least one internal clock source that generates an internal clock signal, and a sensor sub-system that processes sensing-data received from at least one sensor module on a predetermined cycle when the application processor is in the active mode or a sleep mode, and that operates based on the internal clock signal or an external sub clock signal received from the external clock source depending on an operating speed required for processing the sensing-data.

Abstract: A circuit for reducing jitter in a digital signal is provided, comprising a clock and data recovery stage operative to receive an input data signal and generate in response thereto a recovered data signal, a recovered clock signal, and an unfiltered interpolator code; a filter stage operative to receive the unfiltered interpolator code and generate in response thereto a filtered clock signal; and a memory component operative to receive the recovered data signal, the recovered clock signal, and the filtered clock signal; sample the recovered data signal using the recovered clock signal; store the resulting sampled bits; and generate an output data signal by selecting stored bits using the filtered clock signal.

Abstract: A method embodiment of the present disclosure includes receiving a delay value associated with an interconnect delay that is measured across interconnect circuitry communicatively coupling a host semiconductor device with a semiconductor device. The method also includes delaying a local clock signal by an amount of delay indicated by the delay value to produce a delayed local clock signal. The method also includes receiving a delayed source clock signal, where the delayed source clock signal is received from the host semiconductor device via the interconnect circuitry. The method also includes outputting a master clock signal based on a comparison of the delayed source clock signal and the delayed local clock signal, where the master clock signal is utilized to generate one or more aligned clock signals on the semiconductor device that are aligned with a source clock signal generated on the host semiconductor device.

Abstract: Microprocessors are provided with decentralized logic and associated methods for indicating power related operating states, such as desired voltages and frequency ratios, to shared microprocessor power resources such as a voltage regulator module (VRM) and phase locked loops (PLLs). Each core is configured to generate a value to indicate a desired operating state of the core. Each core is also configured to receive a corresponding value from each other core sharing the applicable resource, and to calculate a composite value compatible with the minimal needs of each core sharing the applicable resource. Each core is further configured to conditionally drive the composite value off core to the applicable resource based on whether the core is designated as a master core for purposes of controlling or coordinating the applicable resource. The composite value is supplied to the applicable shared resource without using any active logic outside the plurality of cores.

Abstract: An apparatus comprising a delay circuit and a control circuit. The delay circuit may be configured to generate a plurality of intermediate signals in response to (i) a clock signal and (ii) an adjustment signal. The control circuit may be configured to generate the adjustment signal and a plurality of output signals having a quarter-cycle interval in response to (i) the plurality of intermediate signals and (ii) the clock signal.

Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Abstract: Various exemplary embodiments relate to method and media devices for synchronizing media playback between a receiving media device and sending media device, including: receiving, at the receiving media device, a plurality of messages from the sending media device, wherein the plurality of messages include a plurality of sender timestamps; generating a plurality of clock offset values based on the plurality of sender timestamps and a clock of the receiving media device; identifying a minimum clock offset value from the plurality of clock offset values; locating first media data for playback and a first presentation time associated with the first media data; and causing the first media data to be rendered at a first time that matches the first presentation time based on the minimum clock offset.

Abstract: The present disclosure relates methods and apparatus for conducting a seismic survey using a fiber optic network. The method may include synchronizing a plurality of seismic devices over a fiber optic network where at least one of the seismic devices is separated from a master clock by at least one other seismic device. The method may also include encoding the master clock signal, transmitting the encoded master clock signal, and recovering the master clock signal. The apparatus may include a fiber optic network with seismic devices. The seismic devices may be arranged in a linear or tree topology.

Abstract: In one exemplary aspect, a method of a distributed database system includes the step of detecting that a database node departed from a database cluster. A consensus-based voting process is implemented utilizing all of a set of other database nodes remaining in the database cluster. A cluster configuration is determined with the consensus-based voting process. The cluster configuration includes a new list of the set of other database nodes remaining in the database cluster. The data is automatically rebalanced among the set of other database nodes remaining in the database cluster according to the cluster configuration. Optionally, the consensus-based voting process can include a Paxos algorithm. The database cluster can be a Not-Only SQL (NOSQL) distributed database cluster.

Abstract: The present invention relates to a transmission interface device capable of calibrating the transmission frequency automatically, which comprises a clock generating unit, a data transmission unit, and a control unit. The clock generating unit is used for generating an operating clock, which determines a transmission frequency. The data transmission unit is used for connecting to a host and transmitting a plurality of data to the host or receiving the plurality of data from the host according to the operating clock. When the host or the data transmission unit detects transmission errors in the plurality of data, the host or the data transmission unit generates an error handling. The control unit generates an adjusting signal according to the error handling and transmits the adjusting signal to the clock generating unit for adjusting the transmission frequency of the operating clock.

Abstract: A memory interface includes circuitry configured for applying a variable delay to a portion of a data signal and applying a variable delay to a data strobe. The delayed data strobe samples the delayed portion of the data signal. Delayed portions of the data signal are spaced away from non-delayed portions of the data signal by alternating the routing of delayed bits and non-delayed bits of the data signal. A training block determines and sets a value of the variable delay corresponding to a largest value of a number of recorded eye aperture widths.

Abstract: A system and method for synchronizing multiple backplanes within an information handling system are disclosed. An information handling system includes a first controller that may be operable to generate a time command at a predetermined time interval. A backplane including a second controller is communicatively coupled to the first controller. The second controller may be operable to receive the time command from the first controller and calculate a skew for the time command based at least on a location of the backplane. The second controller may further be operable to adjust a time domain of the backplane based on the calculated skew for the time command to synchronize the backplane.

Abstract: An electronic device comprising a semiconductor memory unit that may include a variable resistance element configured to be changed in a resistance value thereof in response to current flowing through both ends thereof, a toggle data generation unit configured to generate toggle data of which logic value toggles with a predetermined cycle, in a first mode for testing reliability of the variable resistance element, a data transfer line configured to transfer data inputted from an outside, and a driving unit configured to flow current which is changed in its direction with the predetermined cycle, through the variable resistance element in response to the toggle data in the first mode, and flow current through the variable resistance element in a direction determined in response to the data of the data transfer line, in a second mode in writing date into or reading data from the variable resistance element.

Abstract: Mechanisms for clock gating. A clock generation circuit provides a clock signal over a clock signal distribution network within an integrated circuit package. Gating elements within the clock signal distribution network disable the clock signal to one or more portions of the clock signal distribution network. A digital locked loop (DLL) maintains settings without tracking when the clock signal is disabled.

Abstract: A digital transmitter includes: a plurality of adjustable delay lines arranged to delay a plurality of digital input signals by a plurality of delay times to generate a plurality of delayed digital input signals respectively; a plurality of converting devices arranged to convert the plurality of delayed digital input signals into a plurality of converting signals respectively; and a calibration device arranged to adjust a delay time of at least one adjustable delay line in the plurality of adjustable delay lines to make the plurality of converting devices convert the plurality of delayed digital input signals at respective desire time points.

Abstract: An information processing apparatus that is capable of correcting a time-of-day management function in the information processing apparatus even in an environment where the time of day cannot be properly measured in the information processing apparatus in a power-saving mode. A first time of day is obtained from an external apparatus on a network. A second time of day is identified based on the number of input CPU clocks per prescribed time period. The number of input CPU clocks per prescribed time period is corrected based on the first time of day and the second time of day.

Abstract: A method for recovering a clock frequency of a CAN bus, the method including: receiving a data signal, wherein the data signal includes at least one state transition; detecting the state transition; and adjusting a frequency of a clocking signal generated by an oscillator circuit, wherein the frequency is adjusted when the state transition is detected and adjusting the frequency is for recovering the clock frequency of the CAN bus.

Abstract: A system for exposing data stored in a cloud computing system to a content delivery network provider includes a database configured to receive and store metadata about the data, the database being implemented in the cloud computing system to store configuration metadata for the data related to the content delivery network, and an origin server configured to receive requests for the data from the content delivery network provider, and configured to provide the data to the content delivery network provider based on the metadata.

Abstract: A slew rate controller for a computing system includes a slew rate control module, the slew rate control module further comprising a plurality of sampling modules, each sampling module corresponding to one of a plurality of phase signal inputs, wherein each sampling module receives an input signal, a reference voltage, and the sampling module's respective phase signal input, and wherein each sampling module generates a respective sample of a relationship between the input signal and the reference voltage during a time period indicated by the sampling module's respective phase signal input; and a finite state machine configured to output a slew rate control signal to control a slew rate of the input signal based on the plurality of samples from the sampling modules.

Abstract: A computer system includes a processor, and the processor includes at least one interface for communicating with an electronic component. Each of the at least one interface has a set of interface settings. The computer system further includes a memory containing machine executable instructions. Execution of the instructions causes the processor to: monitor communications traffic on the at least one interface; store, eye distribution data acquired during the monitoring of the communications traffic in a database; compare the eye distribution data to a set of predetermined criteria; and generate a set of updated interface settings if the eye distribution does not satisfy the set of predetermined criteria.

Abstract: A method and corresponding apparatus for aligning a data signal with a corresponding clock signal include oversampling the data signal based on the corresponding clock signal and generating corresponding data samples. An indication of skew between the data signal and the corresponding clock signal is detected based on data samples. A variable delay line coupled to the data signal is then adjusted based on the indication of skew detected. According to at least one example implementation, the data signal is oversampled based on the corresponding clock signal and multiple time-shifted versions of the corresponding clock signal. At least one signal of the corresponding clock signal and the multiple time-shifted versions of the corresponding clock signal is employed in sampling the data signal at a potential transition edge of the data signal.

Abstract: An embodiment for skew compensation for a stacked die is disclosed. For an embodiment of an apparatus, an interposer has a first and a second integrated circuit die coupled to the interposer. The first integrated circuit die includes an information generator, a signal delay compensator, and an input/output block. The information generator is configured to determine: a first delay value for a first path of the interposer between the first integrated circuit die and the second integrated circuit die; a second delay value for a second path of the interposer between the first integrated circuit die and the second integrated circuit die; and a difference between the first delay value and the second delay value. The signal delay compensator is coupled to receive the difference and configured to adjust a parameter of the first integrated circuit die to reduce the difference.

Abstract: A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.

Abstract: A programmable logic device is provided that includes: a programmable interconnect adapted to route input signals through the device at a system clock rate; and a digital signal processor (DSP) block coupled to the interconnect, the DSP block including: a plurality of input ports; an input register coupled to the multiple input ports and adapted to sequentially register samples of the input signals from the interconnect received at the input ports at a multiple of the system clock rate; and a multiplier adapted to multiply the registered samples at the multiple of the system clock rate to produce an output signal.

Abstract: A thermal protection method for a computer system including at least a processor includes monitoring the temperature and loading of the processor via a system firmware in the computer system, obtaining the current performance state level and at least an operable performance state levels of the processor when the system firmware determines that the temperature and loading of the processor exceeds a predetermined value respectively, wherein the performance state level is associated to the frequency of the processor, and setting the processor to one of the operable performance state levels, wherein the frequency of the performance state level is lower than the frequency of the current performance state level, according to the current performance state level and the operable performance state levels.

Abstract: Optimizing an I2C bus frequency, the bus including signal lines coupling a master and slave nodes, a signal line coupled to a rise time detection circuit monitoring a voltage of the signal line, the voltage alternating between a logic low and logic high, where optimizing the frequency includes: detecting, during a rise in the signal line, a first voltage, the first voltage being greater than the logic low voltage; starting a counter to increment once for each clock period of the circuit; detecting a second voltage on the signal line, the second voltage greater than the first and less than the logic high; stopping the counter; calculating, in dependence upon the clock period and the counter value, a rise time; determining whether the rise time is greater than a maximum threshold; and increasing the I2C bus frequency if the calculated rise time is greater than the maximum threshold.

Abstract: This invention relates to methods and devices for clock offset and skew estimation. The invention has particular application in the alignment of slave clocks to a master clock. In embodiments of the invention, the slave clock employs an independent free running clock and a recursive estimation technique to estimate the clock offset and clock skew between the slave and master clocks. The slave can then use the offset and skew to correct the free running clock to reflect an accurate image of the master clock.

Abstract: A semiconductor device includes a plurality of data output circuits suitable for outputting data to outside; an address training driver suitable for generating a plurality of address training data and a control signal; a plurality of data lines suitable for transferring the address training data to the data output circuits; and a self-correction circuit suitable for correcting a delay time of the address training data that reaches the data output circuits from the address training driver through the plurality of data lines, and correcting skew of the data that is outputted from the data output circuits.

Abstract: In one embodiment, a microprocessor includes one or more processing cores. At least one processing core includes a clock shaping circuit that is configured to receive a clock input signal. The clock shaping circuit includes rising edge skew logic that is configured to selectively delay a rising edge of the clock input signal and falling edge skew logic that is configured to selectively delay a falling edge of the clock input signal independent of adjustment of the rising edge.

Abstract: A system and method for synchronizing clocks across a packet-switched network eliminates wander accumulation to enable precision clock distribution across a large network. In addition to standard Precision Time Protocol (PTP) synchronization messages or similar time synchronization messages, each clock regenerator stage receives a grand clock error message from the previous stage, updates this error message with its own stage clock error, and then transmits the updated grand clock error to the next stage. This enables the synchronization algorithm to compensate for the error of the previous stage, effectively locking each clock regenerator stage to the grand master clock directly.

Abstract: A correction apparatus includes an acquirer that acquires the execution time of an instruction in a given block among a block group that includes blocks obtained by dividing program code; a detector that detects a first resource group designated by a tail instruction in a preceding block that is executed before the given block and a second resource group designated by a head instruction of the given block; an identifier that identifies a resource common to the first and the second resource groups; a calculator that from the time when the identified resource is used by the head instruction and the time when use of the identified resource by the tail instruction ends, calculates a delay period caused by the preceding block; a corrector that based on the calculated delay period, corrects the acquired execution time; and an output device that outputs the corrected execution time.

Abstract: A synchronization apparatus, comprising: a USB device having a USB microcontroller, circuitry for observing USB traffic, and circuitry for decoding from a USB data stream a periodic data structure (such as a clock carrier signal) containing information about a distributed clock frequency and phase and outputting a decoded carrier signal; and circuitry for receiving the decoded carrier signal, for generating a software interrupt upon receipt of a predefined data packet (such as a SOF packet) and for passing the software interrupt to the USB microcontroller; wherein the USB microcontroller is configured to respond to the software interrupt (such as with an interrupt service routine provided therein) by generating an output signal adapted to be used as a synchronization reference signal.

Abstract: A cable with circuitry that enables the cable to communicate data in one of at least two different signal modes of operation is presented. In a first signal mode, the cable enables data communication between the circuitry and either a source device or a sink device. The first signal mode can be used either to communicate properties of the cable itself or of a signal passing through the cable to either the source device or the sink device. In a second signal mode, the cable enables data communication between the source device and the sink device. The second signal mode can be used to communicate data in accordance with a predetermined protocol.

Abstract: The present technology proposes techniques for generating globally coherent timestamps. This technology may allow distributed systems to causally order transactions without incurring various types of communication delays inherent in explicit synchronization. By globally deploying a number of time masters that are based on various types of time references, the time masters may serve as primary time references. Through an interactive interface, the techniques may track, calculate and record data relative to each time master thus providing the distributed systems with causal timestamps.

Abstract: A method includes communicating between a memory controller and multiple memory devices over an interface that includes at least a control signal and an information signal. For each memory device, a respective individual skew parameter, which is indicative of a timing misalignment between the control signal and the information signal when communicating with that memory device, is produced. The respective individual skew parameter is stored coupled to each memory device. The timing misalignment is corrected at the memory device using the stored individual timing skew.

Abstract: A method of performing and correcting a timing analysis performed by a data processing apparatus on a circuit formed of a plurality of cells to account for the reverse Miller effect. The timing analysis steps includes identifying cells on and in parallel with a signal path that are driven by a same signal and determining an output transition time and a delay using the characterization data for the cell. The correcting steps includes providing further characterization data for some of the cells; correcting the output transition time for some of the cells by increasing the output transition time by an amount dependent upon the Miller capacitance for the cell and using the correction to the output transition time to correct an input transition time for a next cell; and calculating a time taken for a data signal to travel along the signal path from the delay times.

Abstract: A method and apparatus for generating an accurate clock generator timing source, comprising minimal jitter, excellent resolution, and an extended calibration range, for use, for example, in a system requiring accurate low power operation. In particular, a clock generation system is adapted to receive a generated clock input, a reference clock input, and an adjustment parameter comprising a sign bit and p data bits. The calibration logic system is further adapted to output and modify a calibrated clock, using distributed pulse modification. The adjustment parameter may be automatically generated.

Abstract: In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.