Abstract: An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than normal operating speed to ensure correct capture of the pattern at the device to be calibrated. Once the pattern is correctly captured and stored, the test pattern is transmitted to the logic device at the normal operating data rate to perform timing calibration. The improved technique and apparatus permits the use of any pattern of bits as a calibration test pattern, programmable by the user or using easily-interchangeable hardware.

Abstract: A method and system for applying multiple voltage droop detection and instruction throttling instances with customized thresholds across semiconductor chips. Environmental parameters are detected for various locations on a chip, and timing margins are determined for each location on the chip. An acceptable voltage droop for each location is determined based on the environmental parameters and the timing margins for the corresponding location. A droop threshold is then determined for each location based on the corresponding acceptable voltage droop determined for the corresponding location.

Abstract: A source-synchronous parallel interface divides a wide data bus into clock-groups including a sub-group of the data lines and a clock line carrying a copy of the transmit clock. The traces in a clock-group are located physically close together to minimize skew between the signals carried on the traces of the clock-group. Deskew logic on the receiver compensates for skew between received clock-group signals.

Abstract: System and methods of synchronizing reference frequencies are disclosed. In an exemplary implementation, a method may comprise providing separate reference frequencies for each of a plurality of operational components. The method may also comprise connecting the separate reference frequencies to one another in a modular, fault-tolerant circuit topology. The method may also comprise synchronizing the separate reference frequencies so that each of the operational components operate at the same frequency.

Abstract: A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device and a second frequency calibration device both to share an oscillator as so to perform two-stage clock frequency resolution calibrations for generating different frequency-tuning ranges. This can bring an optimal frequency resolution and greatly reduce system complexity and save element cost.

Abstract: An apparatus and method is described for dynamically aligning clocks in independent clock domains with minimal latency. In the preferred embodiments, a reference clock in the destination clock domain that is some multiple times the data clock of the destination clock domain is used to sample a data sample signal from the source domain. The sampled data is used to determine at what time slice of the reference clock the data sample signal is changing and therefore at what phase of time slice or phase of the data clock the clocks can be aligned to ensure valid data will be transferred between clock domains.

Abstract: A computer-implemented system, method and apparatus for operating a reference monitor simulator is operable to recreate the operations performed by a reference monitor on a computer system. In one configuration, the system defines at least one security rule specifying whether to allow or deny a request to access at least one resource under a given set of circumstances and supplies at least one request to access a resource. The system further applies the at least one security rule in response to the at least one request to access a resource to determine whether to allow or prevent the at least one request.

Abstract: An apparatus for synchronizing an output clock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter. The first timing synchronization circuit is operable to generate a delay to synchronize a reference clock signal representative of the input clock signal with a feedback clock signal representative of the output clock signal responsive a strobe signal. The control logic is operable to generate an enable signal based on the reference clock signal and generate the strobe signal based on the feedback clock signal. The counter is operable to count cycles of the reference clock signal occurring between the enable signal and the strobe signal to generate a loop count for the first timing synchronization circuit.

Abstract: A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.

Abstract: Provided is a communication device capable of efficiently performing a power supply control when reducing power consumption by reducing the time during which the power is supplied. In the device, a CPU power saving control unit (301) switches between a normal mode in which the power is supplied to a CPU (302) and a low power consumption mode in which the power supply is stopped at predetermined timing. A session management table (321) stores transmission intervals before and after conversion. An information conversion section (322) converts the transmission intervals of session maintenance messages according to a predetermined rule so that the transmission intervals of the session maintenance messages of respective protocols are mutually synchronized between the protocols.

Abstract: A circuit synchronizes parallel data of different timing for transfer. The synchronous data transfer circuit includes a plurality of first flip-flop circuits in which the parallel data are set by a data strobe signal, a plurality of delay circuits, and a plurality of second flip-flop circuits. By configuring the second flip-flop circuits to share generation of a delay amount, the second flip-flop circuits are utilized for data synchronization by the synchronous data transfer circuit. Thus, it becomes possible to configure the delay circuits with a remarkably reduced amount of delay elements.

Abstract: Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated from the captured first group. A second group of applied data signals is then captured and determined to have been properly captured when the second group corresponds to the group of expect data signals. In this way, when a captured series of data signals is shifted in time from an expected capture point, subsequent captured data signals are compared to their correct expected data signals in order to determine whether that group, although shifted in time, was nonetheless correctly captured. A pattern generator generates expect data signals in this manner, and may be utilized in a variety of integrated circuits, such as an SLDRAMs.

Abstract: A variable timing system for a magnetoresistive random access memory circuit (MRAM IC) is embedded in an MRAM IC and includes a number of timing control circuits, where each timing control circuit generates a timing control signal. A number of variable timing circuits are each coupled to receive at least two of the timing control signals, and each of the number of timing circuits outputs a variable timing in response to the timing control signals. At least one MRAM timing driver is connected to receive the variable timing.

Abstract: A clock filter circuit (20), which serves for filtering the clock of non-isochronous data signals having a selected one of at least two nominal data rates, has an auxiliary clock source (21) that generates an auxiliary clock signal (27) with a pulse repetition rate which is in the range between the at least two predetermined data rates, a delay line (22) connected to the auxiliary clock source (21) for creating a set of mutually delayed copies of the auxiliary clock signal and a multiplexer (23) that switches in a cyclic order between the delayed copies according to predetermined rules, which depend on the selected data rate to generate a filtered clock signal (28). A control circuit determines whether the rate of the filtered clock (28) signal must be increased or decreased as compared to said data signal and controls the multiplexer (23) to delay or advance the cyclical switching accordingly.

Abstract: A memory controller comprises a DQ path, a DQS path, a delay element, a flip flop, and an adjustment unit. The DQ path receives and passes a data signal, and outputs a delayed data signal. The DQS path receives and passes a data strobe signal. The delay element is coupled to the DQS path, receiving the data strobe signal to generate a compensated data strobe signal having a calibrated latency. The calibrated latency is determined by an adjustment signal. The flip flop is coupled to the data signal path and the delay element, sampling the delayed data signal by the compensated data strobe signal to generate an output data. The adjustment unit generates the adjustment signal according to the output data. The adjustment unit performs a calibration to adjust the adjustment signal, thus the calibrated latency is adjusted.

Abstract: An apparatus and method for processing a captured image and, more particularly, for processing a captured image comprising a document. In one embodiment, an apparatus comprising a camera to capture documents is described. In another embodiment, a method for processing a captured image that includes a document comprises the steps of distinguishing an imaged document from its background, adjusting the captured image to reduce distortions created from use of a camera and properly orienting the document is described.

Abstract: A circuit for calibrating a data control signal includes a time-delay compensation circuit and a voltage-control delay circuit. The time-delay compensation circuit receives two complementary signals and a direct current voltage which has two voltage cross points with the two complementary signals respectively, and outputs a control voltage according to a time difference between the two voltage cross points. The voltage-control delay circuit delays a data control signal for a predetermined time according to the control voltage, thereby eliminating signal skew between the data control signal and a data signal.

Abstract: The present invention discloses, in one aspect, a synchronizing circuit for synchronizing transmitted data. In one embodiment, the synchronization technique comprises a subsystem configured to compare positive and negative transitions of a core clock signal with positive and negative transitions of a source clock signal to determine a relationship between the transitions of the core clock signal and positions of the negative transitions of the source clock signal. The synchronization circuit also comprises logic circuitry coupled to the subsystem and configured to generate a final sampling signal based on the relationship. In addition, the synchronization circuit comprises a data sampler coupled to the logic circuitry and configured to sample a source data signal synchronized with the source clock signal using the final sampling signal, and to generate a core data signal synchronized with the core clock signal based on the sampling.

Abstract: A timing recovery system and method for accelerated clock synchronization of remotely distributed electronic devices is provided. The system includes a phase locked loop, a linear estimator and control logic. The method includes sampling a clock signal received from an electronic device, applying a linear estimation technique to estimate the frequency and phase of the received signal and providing those estimates to a phase locked loop to accelerate the phase locked loop acquisition rate and secure signal lock quickly.

Abstract: A clock device comprises a time information acquisition unit which acquires time information representing present time from an external device at preset time intervals, a time correction unit which corrects time of an internal clock based on the time information, an error calculation unit which calculates an error of the time of the internal clock based on the present time represented by the time information, and a setting change unit which changes the set value of the time interval based on the error. The setting change unit updates the set value to m times the set value when the error is smaller than a first threshold value, while updating the set value to n times the set value when the error is larger than a second threshold value larger than the first threshold value (m, n: positive values satisfying m>1, n<1 and m·n?1).

Abstract: Disclosed are a method and system for estimating the skew and offset between two clocks in a computer system. The method comprises the steps of obtaining a first set of data values representing a forward delay between the first and second clocks, and obtaining a second set of data values representing a negative backward delay between the first and second clocks. The method comprises the further steps of forming a lower convex hull for said first set of data values, and forming an upper convex hull, above the lower convex hull, for said second set of data values. The clock offset and the skew between said first and second clocks are estimated using those convex hulls. In a preferred embodiment, this estimation is made by identifying a best clock line between the first and second convex hulls.

Abstract: It is so arranged that an appropriate deadline is assured with little consumption of power. A register (24) for remaining transfer time senses time that remains up to a limit by which data is to be transferred. A register (25) for remaining amount of data transfer senses the remaining amount of data that is to be transferred. The clock of the processing module is changed over dynamically based upon the remaining time sensed by the remaining transfer time register (24) and the remaining amount of transfer data sensed by the remaining transfer amount register (25).

Abstract: A system, method and computer program product for steering a time-of-day (TOD) clock for a computer system having a physical clock providing a time base for executing operations that is stepped to a common oscillator. The method includes computing a TOD-clock offset value (d) to be added to a physical-clock value (Tr) value to obtain a logical TOD-clock value (Tb), where the logical TOD-clock value is adjustable without adjusting a stepping rate of the oscillator.

Abstract: A clock data recovery circuit includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive data and a clock signal and to detect transitions in the data and provide a first signal based on the clock signal and the transitions in the data. The second circuit is configured to receive the first signal and provide a first shift signal based on the first signal. The third circuit is configured to receive the first shift signal, wherein the first circuit, the second circuit, and the third circuit are configured to form a first circuit loop and the third circuit is configured to disable the first circuit loop and shift the clock signal based on the first shift signal.

Abstract: Nodes in a network include a pseudo-timestamp in messages or packets, derived from local pseudo-time clocks. When a packet is received, a first time is determined representing when the packet was sent and a second time is determined representing when the packet was received. If the difference between the second time and the first time is greater than a predetermined amount, the packet is considered to be stale and is rejected, thereby deterring replay. Because each node maintains its own clock and time, to keep the clocks relatively synchronized, if a time associated with a timestamp of a received packet is later than a certain amount with respect to the time at the receiver, the receiver's clock is set ahead by an amount that expected to synchronize the receiver's and the sender's clocks. However, a receiver never sets its clock back, to deter attacks.

Abstract: To provide a semiconductor device including a data input circuit and a data output circuit connected to a plurality of data input/output terminals, where at least one of the data input circuit and the data output circuit fetches data in response to multi-phase clock signals having different phases to be timing signals for fetching data, and adjusts a valid range for fetching data to be substantially uniform for each of the multi-phase clock signals. According to the present invention, the window width of data can be made uniform by individually adjusting the multi-phase clock signals that are input or output timing signals, and thus characteristics of the semiconductor device can be improved.

Abstract: An embodiment of the invention provides an apparatus for computation of processor clock frequency ratios in a multi-processor system. The apparatus includes a computation engine configured to determine a processor clock frequency ratio by reading counter values of a first counter and of a second counter within a frequency ratio computation interval, and configured to determine a value of the second counter at an end of a frequency ratio valid interval where the frequency ratio is applied, wherein the frequency ratio valid interval is subsequent to the frequency ratio computation interval, and wherein the frequency ratio valid interval does not overlap the frequency ratio computation interval.

Abstract: A system comprises a central processing unit and a set of peripheral units accessible by the CPU and being able to be driven by the same clock source. At least one programmable delay line is located in the clock branch of one of the peripheral units and has a delay selection input that is accessible by software running on the system.

Abstract: A physical coding sublayer (PCS) transmitter circuit generates a plurality of encoded symbols according to a transmission standard. A symbol skewer skews the plurality of encoded symbols within a symbol clock time. A physical coding sublayer (PCS) receiver core circuit decodes a plurality of symbols based on encoding parameters. The symbols are transmitted using the encoding parameters according to a transmission standard. The received symbols are skewed within a symbol clock time by respective skew intervals A PCS receiver encoder generator generates the encoding parameters.

Abstract: Integrated circuits such as programmable logic device integrated circuits with memory interface circuitry are provided. The memory interface circuitry measures the timing characteristics of an associated memory during a series of dummy read operations. A multiplexer and phase detector are used to measure phase shifts of memory group clock signals compared to a system clock signal. The memory interface circuitry uses these measurements to adjust a delay-locked-loop circuit. The delay-locked-loop circuit produces a capture clock that is used to read data from the memory.

Abstract: An exemplary method for adjusting clock phase of a monitor includes: setting a reference threshold voltage, when an input voltage of image signals is greater than the reference threshold voltage, a scaler begins to receive clock phases generated by a Phase Locked Loop; dividing the clock phase into a plurality of equal periods, recording a corresponding input voltage at each point dividing two adjacent period, and setting the corresponding input voltage as a threshold voltage of the next period; recording a quantity of the clock pulses in each period; evaluating whether a period of the clock phase is a regular period according to whether the quantity of clock pulse in the period is equal to a reference quantity or not, while the input voltage is generating retardation; and selecting the input voltage of the image signals corresponding to a regular period as a threshold voltage of the scaler.

Abstract: When a beacon (n?1) that is transmitted from a piconet coordinator (PNC) is detected in a MAC layer of the PNC and a MAC layer of a device (DEV), a detection signal is immediately transmitted to a LINK layer. In the LINK layer, a count is made from the detection of the beacon to a predetermined timing to generate a cycle timer. The PNC adds the PNC cycle timer to the subsequent beacon (n) and transmits the beacon to the DEV. In the LINK layer of the DEV, a comparison is made between a DEV cycle timer generated according to the beacon (n?1) and the PNC cycle timer received from the PNC and uses the value of the difference therebetween to correct the DEV cycle timer to be matched with the PNC cycle timer.

Abstract: A conditioning buffer is provided for a clock interpolator that controls the duration of the clock edges to achieve high-linearity interpolation. The conditioning buffer includes a first buffer and a second buffer, with a fixed or variable strength, that receive their respective inputs from a set of mutually delayed clock signals, such as a set of N equidistant clock phases with mutual delay of 360/N degrees, to form a two-tap transversal filter that is insensitive to changes in Process, Temperature, and Voltage (PVT). Use of an equidistant set of clock phases makes the time constant of such transversal filter proportional to the clock period thus making it insensitive to changes in clock frequency as well. Such transversal filtering action operated in conjunction with natural bandwidth limitations of the buffers yields an efficient clock conditioning circuit that is highly insensitive to PVT and clock frequency variations.

Abstract: Methods and system for reducing latency associated with a read operation in a processor memory system are provided. In one implementation, the method includes receiving an early indicator corresponding to read data from a memory, delaying the early indicator in accordance with a pre-determined delay such that the early read indicator is passed to a bus in advance of the read data; and dynamically adjusting the pre-determined delay using an adjustment delay circuit, the pre-determined delay being adjusted responsive to a change in operational speed of the bus or change in operational speed of a processor coupled to the bus.

Abstract: A method for handling data in which a serial data flow, with which a plurality of data is transmitted simultaneously per line, is transmitted using a serial protocol, which is formed from data blocks and synchronization blocks.

Abstract: A communication system includes: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves. The master supplies electricity to the bus in a power supply period. The master or the slave drives the bus for transmitting a one-bit data through the bus in a data transmission period. The power supply period and the data transmission period are successively performed so that data communication provided by a plurality of one-bit periods is performed among the master and the plurality of slaves. The master finely changes a communication frequency in the data communication. The master changes a drive level of the bus within a predetermined acceptable range in the data communication.

Abstract: An interface apparatus is provided having a first register device and a second register device, which is connected in parallel with it. The register devices are configured to receive a data word. The interface apparatus includes a synchronization circuit, to which a first and a second clock signal is supplied and which is configured to emit a selection signal, which is derived from the first clock signal, for selection of the first or second register device for storage of a data word. The synchronization circuit is also configured to emit a control signal derived from the selection signal and the second clock signal, at a control output. The control output is coupled to a selection circuit, by means of which the output of one of the two register devices can be connected to the data output of the interface apparatus. Comparison of the selection signal with the second clock signal means that there is no need for an additional registration device.

Abstract: An integrated circuit device is described. The circuit device may include a group of signal nodes, including a first signal node and a second signal node, a transmitter coupled to the group of signal nodes, and a first clock circuit coupled to the transmitter. The transmitter may transmit a first signal on the first signal node and a second signal on the second signal node. The first signal and the second signal may correspond to a first sequence of data bits during a sequence of bit times. The first clock circuit may control a transmit time of at least one of the first signal and the second signal. The first clock circuit may include a first phase adjustment element that provides compensation for a first timing offset between the first signal and the second signal. The first timing offset may be less than a bit time in the sequence of bit times.

Abstract: A method, apparatus and computer instructions for application based tracing and for normalization of processor clocks in a symmetric multiprocessor environment. By deliberately establishing a large skew among processor clocks, it is possible to perform application based tracing by directly using the processors. In addition, the identity, time stamp, and drift information of each processor may be used to create a time library. The time library is used to adjust a measured time to execute a program or software routine. The adjusted time is a normalized time that is statistically more accurate than the measured time alone. The adjusted time is then reported as the time to execute the program or software routine.

Abstract: Programmable logic device integrated circuits are provided that have configurable receivers with dynamic phase alignment capabilities. In situations in which receivers require dynamic phase alignment circuitry, programmable logic elements can be configured to implement a dynamic phase alignment data capture and synchronization circuit. In situations in which dynamic phase alignment receiver circuitry is not required, resources are made available for implementing other user logic. Multiple dynamic phase alignment receiver circuits can share an eight-phase dynamic phase alignment clock signal that is generated by a phase-locked-loop circuit. Switches may be configured to selectively route the dynamic phase alignment clock signal to desired locations on the programmable logic device integrated circuit.

Abstract: In a delay failure test circuit, a delay failure test between two clock domains among a plurality of clock domains having different operation clock rates is performed. The delay failure test circuit inputs, to a first clock domain, a clock signal having only a launch edge for transferring data from the first clock domain to a second clock domain, and to input, to the second clock domain, a clock signal having only a capture edge for capturing the data.

Abstract: A dynamic clock frequency module for a system-on-chip (SOC) including modules that communicate over a system bus includes a request evaluation module that receives requests to utilize the system bus from the modules. A frequency assignment module calculates a clock frequency value for the system bus based on the requests received by the request evaluation module. The request evaluation module includes a summing module that generates a sum of requests between the modules. A pulse stretch module increases a period of time that at least one of the requests is asserted. A low pass filter prevents changes to the clock frequency value when the sum at least one of increases and decreases for less than a predetermined period. A slew rate control module adjusts at least one of a rate of increase and a rate of decrease in the clock frequency value.

Abstract: A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

Abstract: Two clocks may be synchronized by calculating skew and offset values that may be determined from several correlation events. A correlation event may be the passing of messages in both directions between the two devices. The skew and offset values may be used to determine the time of non-correlated events. The clock synchronization may be performed on a real time basis or may be performed on a post processing basis. One method for calculating the skew and offset may use inequalities within a solution space to refine a solution set with multiple sets of correlation events.

Abstract: A communication system includes: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves. The master supplies electricity to the bus in a power supply period. The master or the slave drives the bus for transmitting a one-bit data through the bus in a data transmission period. The power supply period and the data transmission period are successively performed so that data communication provided by a plurality of one-bit periods is performed among the master and the plurality of slaves. The master finely changes a communication frequency in the data communication. The master changes a drive level of the bus within a predetermined acceptable range in the data communication.

Abstract: Methods and systems for detecting fraud based on velocity counts are disclosed.

Abstract: A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the register has bits to indicate the desired mode and the input clock frequency. In the fast data access mode, a clock delay circuit uses the clock frequency setting bits to select a delay to be added to the input clock. The higher the clock frequency, the less the added delay. The delayed clock generates FIFO control signals to control a data FIFO register. During the fast data access mode, the data is output from the data FIFO register at a faster rate than in the standard clock mode.

Abstract: Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of read data received through the read data lanes. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames.

Abstract: Systems and methods are disclosed herein to provide improved jitter tolerant delay-locked loop circuitry. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a plurality of delay cells each having a plurality of programmable delay taps. Each delay cell is adapted to provide a delayed clock signal delayed by a selected number of the delay taps. A phase detector is adapted to compare a first clock signal with a selected one of the delayed clock signals to obtain a comparison result and provide a plurality of control signals in response to the comparison result. An arithmetic logic unit (ALU) is adapted to vary the selected number of delay taps in response to the control signals provided by the phase detector.

Abstract: A frequency control system includes a voltage-controlled oscillator, a sampling circuit for sampling a clock signal produced by the oscillator for two consecutive transitions of an unstable incoming digital signal, and a frequency comparator for incrementing and decrementing a transition upcounter-downcounter controlling the oscillator. The system tolerates variation of the frequency of the incoming signal about a mean value, which has no effect on a clock signal to be extracted by means of a phase comparator or on the synthesized clock signal supplied by the oscillator if the incoming signal contains a high level of jitter and is supplied by a programmable frequency divider.