Abstract: A data transmission system including a slave device (30) and a master device (10) is disclosed. Slave device (30) may include a slave side clock signal generator section (32) for generating a slave side clock signal (CLKSOUT), a phase adjusting circuit (40) for controlling a phase of a slave side clock signal (CLKSOUT), output sections (33-1 to 33-m) for outputting transmission data signals (SD1 to SDm) in response to slave side clock signal (CLKSOUT), and a timing reference signal generator section (34) for outputting a timing reference signal (SSPH) in response to slave side clock signal (CLKSOUT).

Abstract: A master clock reference signal may be provided to selected packet fiber nodes in order to synchronize the local clock reference signals generated at selected devices in a cable network. In this way, selected portions of the cable network may be synchronized to a common timing reference signal. Additionally, synchronized timestamp information may also be provided to selected network devices in order to achieve synchronization of timestamps across a selected portion of the cable network.

Abstract: A data processing system is provided having a clock signal comparator comprising a reference input port for receiving a reference clock signal and at least a further input port for receiving respective further clock signal. Checking logic is provided within the clock signal comparator to check for a correspondence between the clock edge of the reference clock signal and a corresponding clock edge of the further clock signal within a predetermined time window. The checking logic is operable to check for the correspondence during operation of the data processing system. The clock-signal comparator can be provided on an integrated circuit or as part of the data processing apparatus having at least two different timing domains such as timing domains associated with two different instances of the same clock.

Abstract: A system, method and computer program product for synchronizing adjustment of a time of day (TOD) clock for a computer system having multiple CPUs, each CPU having an associated physical clock providing a time base for executing operations that is stepping to a common oscillator, and an associated logical TOD clock. The method includes detecting propagation of a carry at a pre-determined bit position of the physical clock associated with a CPU in the computer system; and, updating, in response to the detecting of the pre-determined bit position carry, a TOD-clock offset value (d) to be added to a physical clock value (Tr) value to obtain a logical TOD clock value (Tb) for use by a CPU in the system. In this manner, each CPU computes a new logical TOD clock value in synchronization—the new logical TOD clock value taking effect simultaneously for the multiple CPUs.

Abstract: A method of determining timing skew between data outputs of a memory device can include writing a predetermined data pattern to a memory device at a first operational frequency that is less than a normal operational frequency used to write non-predetermined data to the memory device. The memory device is read to output the predetermined data pattern therefrom at a second operational frequency that is greater than the first operational frequency and about equal to a normal operational frequency used to read non-predetermined data from the memory device. Timing skew is determined between outputs from the memory device based on the actual time when the predetermined data is provided from the memory device.

Abstract: An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.

Abstract: A semiconductor integrated circuit including a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region supplied with a second power supply voltage, and having a second clock distribution network, a first phase synchronizer which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at a first point of the first clock distribution network, to a second point of the first clock distribution network, and a second phase synchronizer which provides a second output signal obtained by making the phase of the reference clock signal coincident with a phase of a clock signal at a first point of the second clock distribution network, to a second point of the second clock distribution network.

Abstract: A method of adjusting systemic frequency in a storage device, wherein a command is provided by a computer system to count the number of the clock pulses in a set time period of the computer system and the storage device; the value of correction of the systemic frequency of the storage device is obtained by calculation of the computer system, then the value of correction is stored in a storing medium; and the systemic frequency of the storage device is adjusted by the system operating clock frequency adjusting unit according to the value of correction of the systemic frequency, so that the systemic frequency of the storage device can be controlled within a predetermined range that meets the requirement for a device with higher system performance specification, and thereby the cost of production can be reduced.

Abstract: A receiving apparatus receives data sequences, each of which includes plural data blocks, from plural transmission lines, respectively. The apparatus includes plural elastic buffers and a deskew circuit. The corresponding data sequence is written into each elastic buffer. A predetermined number of consecutive timing control symbols are inserted into the data sequences as markers for data blocks to be read from the data sequences at the same cycle. The elastic buffers adjust numbers of the timing control symbols included in the written data sequences, respectively. The data sequences, in each of which the number of the timing control symbols has been adjusted, are read from the elastic buffers in synchronization with a reading clock. The data sequences are written into the deskew circuit. The deskew circuit adjusts the number of the timing control symbols included in each data sequence so as to be equal to the predetermined number.

Abstract: A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and multiplexor pairs, selectively employable to apply an aggregate amount of time delay to a data signal. The detection circuit includes circuit elements to detect a critical reference time distance between a reference point of a data signal and at least a selected edge of a clock signal being smaller than a desired threshold. The control circuit includes circuit elements to dynamically control the aggregate amount of time delay applied by the delay circuit based at least in part on the detection of the detection circuit. In one application, m units of the data transmission error reduction circuit are correspondingly employed to reduce data transmission errors on m high speed parallel data signals of a data interface.

Abstract: Methods and apparatus to provide a clustered variations-aware architecture are described. In one embodiment, one or more variations within a clock domain are detected and utilized to adjust a clock signal of the clock domain.

Abstract: A system and method for effectively performing a clock adjustment procedure includes a multi-core processor that has a plurality of processor cores that each operate with reference to a target clock signal for performing various processing tasks. The processor cores include functional processor cores and one or more non-functional processor cores. A clock manager performs the clock adjustment procedure under control of a master processor core by selecting and applying a target clock frequency for the target clock signal. The target clock frequency is selected to allow the functional processor cores to compensate for the non-functional processor cores by collectively performing all of the required processing tasks.

Abstract: In one embodiment, the present invention includes a method for transmitting a predetermined data pattern from a first agent to a second agent of an interface, receiving an indication of correct receipt of the predetermined data pattern in a buffer of the second agent, determining in a state machine of the first agent an updated load position within a window of the predetermined data pattern at which the buffer can realize the correct receipt, and transmitting the updated load position to the second agent to enable the second agent to capture incoming data from the first agent at the updated load position. Other embodiments are described and claimed.

Abstract: A signal processing device includes a start time obtaining part that obtains a start time when a predetermined process is started in response to an interrupt request associated with a valid edge of a pulse input signal, an edge occurrence time obtaining part that obtains a time of occurrence of the valid edge of the pulse input signal after the start time of the predetermined process is obtained, and a processing part that selectively performs a process based on a time relationship between the start time of the predetermined process and the time of occurrence of the valid edge.

Abstract: Buffer circuitry receives data to be processed by electronic circuitry using a first clock signal associated with a first clock domain. The buffered data is output using a second clock signal associated with a second clock domain. The buffering of the data is associated with a buffering delay. Counting circuitry receives at a start count input a write timing signal associated with the first clock domain and with writing data to the buffer circuitry. The counting circuitry receives at a stop count input a read timing signal associated with the second clock domain and with reading data from the buffer circuitry. A count value accumulated between receiving the write timing signal and the read timing signal corresponds to the buffering delay. Control circuitry performs a control operation based on the count value.

Abstract: Integrated circuits include clock deskew circuitry. The clock deskew circuitry, at the receiver side, receives data signals and a forwarded clock signal from a transmitter. The receiver detects a clock drift in a receiver clock tree, and transmits the detected clock drift to the transmitter. Based on the detected clock drift, the transmitter adjusts the timing of the transmitted signals so that the center of the data eye is aligned with the clock edge at the output of the receiver clock tree.

Abstract: Core clock alignment circuits include a serial-in parallel-out (SIPO) data processing circuit, which is configured to generate a plurality of lanes of deserialized data in response to a corresponding plurality of lanes of serialized data. The SIPO data processing circuit is further configured to generate a plurality of recovered clock signals from corresponding ones of the plurality of lanes of serialized data. These recovered clock signals may be out-of-phase relative to each other. The devices also include a plurality of lane FIFOs, which are configured to receive respective ones of the plurality of lanes of deserialized data and respective ones of the plurality of recovered clock signals at write ports thereof. A core clock alignment circuit is provided, which may be electrically coupled to the plurality of lane FIFOs.

Abstract: A measurement system includes a clock recovery system and a measurement module coupled to the clock recovery system. The clock recovery system has an associated response characteristic. The clock recovery system receives an input signal and recovers a clock signal from the input signal. The measurement module is coupled to the clock recovery system and measures a phase error signal received from the clock recovery system, time-referenced to a trigger signal that is applied to the measurement module, where the phase error signal represents the phase difference between the input signal and the recovered clock signal. A processor applies the associated response characteristic to the measured phase error signal to determine the phase of the input signal.

Abstract: In one embodiment, the present invention includes a method for receiving data from a second device in a first device, forwarding the data from an input/output (I/O) clock domain to a system clock domain of the first device, and providing the data to a functional unit of the first device at a deterministic time. In such manner, the two devices may operate in lockstep fashion. Other embodiments are described and claimed.

Abstract: Embodiments that facilitate the fair and dynamic distribution of central processing unit (CPU) time are disclosed. In accordance with one embodiment, a method includes organizing one or more processes into one or more groups. The method further includes allocating a CPU time interval for each group. The allocation of a CPU time interval for each group is accomplished by equally distributing a CPU cycle based on the number of groups. The method also includes adjusting the allocated CPU time intervals based on a change in the quantity of the one or more groups.

Abstract: An integrated circuit includes a first clock island, a second clock island, a clock generator, and a first programmable delay element. The first clock island is configured to receive a first clock signal. The second clock island is configured to receive a second clock signal. The clock generator is configured to provide a generated clock signal and the first and second clock signals are based on the generated clock signal. The first programmable delay element is coupled between the clock generator and the first clock island. The first programmable delay element is configured to receive the generated clock signal and provide the first clock signal. The integrated circuit is configured to account for a clock skew between the first and second clock signals when information is transferred between the first and second clock islands.

Abstract: A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second channels 20 and 22 have signal generation blocks 10 and 12 that have clock phase shift circuits 26 and 28, memories, parallel to serial converters and DACs respectively. A phase comparator 24 compares data reading clocks from the signal generation blocks 10 and 12 to produce a phase difference signal wherein the data reading clocks are used to read waveform data from the memories within the signal generation blocks 10 and 12. A CPU controls the clock phase shift circuits 26 and 28 according to the phase difference signal to shift phases of the clocks provided to the signal generation blocks 10 and 12 and then makes phase relationship between the output signals of the first and second channels 20 and 22 as desired.

Abstract: Methods and systems are disclosed for providing independent clock failover for scalable blade servers that include assigning a server blade to one of a plurality of clock failover groups, providing a plurality of independent clock signals to the clock generator of the server blade, wherein one of the plurality of independent clock signals is an active clock signal, detecting a failover condition for the clock failover group assigned to the server blade, and switching the active clock signal, in response to the detected failover condition, from one independent clock signal to another independent clock signal.

Abstract: A method of determining timing skew between data outputs of a memory device can include writing a predetermined data pattern to a memory device at a first operational frequency that is less than a normal operational frequency used to write non-predetermined data to the memory device. The memory device is read to output the predetermined data pattern therefrom at a second operational frequency that is greater than the first operational frequency and about equal to a normal operational frequency used to read non-predetermined data from the memory device. Timing skew is determined between outputs from the memory device based on the actual time when the predetermined data is provided from the memory device.

Abstract: A DRAM interface circuit includes a clock generation circuit configured to generate a plurality of internal clock signals and skew data in response to a plurality of data strobe signals (DQS) received at an interface of the integrated circuit device. A data capture circuit is also provided. The data capture circuit is configured to capture a plurality of data streams (DQ) associated with the plurality of data strobe signals in a manner that sufficiently reduces skew between the captured data streams so that all of the plurality of data streams may then be reliably captured in-sync with a common clock.

Abstract: Adjustable transceiver circuitry is provided for programmable integrated circuits. The transceiver circuitry has a dynamic phase alignment circuit that can be used for aligning clock and data signals. The transceiver circuitry supports a phase-locked-loop source synchronous mode that can be used to receive data from transmitting integrated circuits that are clocked with a common clock. Each transmitting integrated circuit transmits a clock and associated data signals over a bus. The transceiver circuitry uses a master-slave architecture. A master dynamic phase alignment circuit in each transceiver receives the clock for that bus and selects a corresponding optimal clock phase to use in receiving input data for the bus from a multiphase clock. The master dynamic phase alignment circuit in each transceiver distributes the optimal clock phase to associated slave dynamic phase alignment circuits. Only a single phase-locked loop circuit is need to generate the multiphase clock.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: The present invention provides a clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof. In an embodiment, a digital system is provided that includes a first digital circuit that operates at a first rate determined by a first clock signal and a second digital circuit that operates at a second rate determined by a second clock signal. The first digital circuit is coupled to the second digital circuit by a bus that is used for communications between the first digital circuit and the second digital circuit. A clock ratio controller is used to adjust the frequency of the first clock signal and/or the second clock signal in response to a power management signal without causing a loss of synchronization between the first digital circuit and the second digital circuit.

Abstract: The various embodiments of the invention provide an apparatus, system and method for data content deskewing among a plurality of data channels for data synchronization. The various embodiments determine whether a data alignment signal has been written, for each data channel of the plurality of data channels, such as a comma character. When a data alignment signal has been written in a data channel of the plurality of data channels, the embodiments determine a corresponding channel location of the data alignment signal for each data channel having the data alignment signal. When each data channel of the plurality of data channels has the data alignment signal, and when the data alignment signal is to be read on a next read cycle in at least one data channel, the various embodiments move a corresponding read pointer for each data channel of the plurality of data channels to the corresponding channel location of the data alignment signal.

Abstract: The development of transmission technologies have resulted in a several tens Gbps optical transmission system. In the present invention, a low-speed FPGA receives a plurality of several Gbps signals according to a very high-speed parallel converting unit and the SFI-5, divides each of the plurality of several Gbps signals into a plurality of several hundreds (Mbps) parallel signals, and processes the plurality of several hundreds (Mbps) parallel signals in order to constitute an SFI-5 receiving end.

Abstract: A clock generator supplies a clock signal to a data transmission circuit for a jitter resistance test of a data transmission/reception circuit, while supplying a clock signal to a data reception circuit. At this time, the clock signal supplied by the clock generator to the data transmission circuit is allowed to include jitter of the modulation frequency and depth based on various types of setting signals. A signal is at the H level during the test.

Abstract: A test apparatus that test a device under test includes a plurality of signal input/output units each of which has a signal output section and a signal input section that: firstly, adjusts each of the signal input/output units such that the phase difference between a time at which the signal output section outputs a signal and a time at which the signal input section inputs the signal is substantially the same as that of the other input/output units; next, detects, in the state that the plurality of signal input/output units are connected to each other, the amount of shift to shift the signal input timing in order to input the signal outputted by the first signal output section by the second signal input section and the amount of shift to shift the signal input timing in order to input the signal outputted by the second signal input section by the first signal input section; and then, adjusts such that the phases of the signal input/outputs between the first signal input/output unit and the second signal inpu

Abstract: Apparatus and methods are disclosed for adjusting phase of data signals to compensate for phase-offset variations between devices during normal operation. The phase of data signals are adjusted individually in each transmit data unit and receive data unit across multiple data slices with a common set of phase vector clock signals and a corresponding clock cycle count signal. The transmission of signal information between a first device (such as a memory controller) and a second device (such as a memory component) occurs without errors even when the accumulated delays between the first device and second device change by a half symbol time interval or more during operation of the system. The apparatus reduces the circuitry required, such as phase-lock-loops, for individually adjusting the phase of each transmit data unit and receive data unit across multiple data slices, which in turn results in reduction in complexity and cost of the system.

Abstract: A dual mode digital interface supports the HyperTransport Standard and at least one other interface standard. The dual mode digital interface includes a plurality of data line deskew/sampling blocks, a data group deskew module, and an enablement control module. The plurality of data line deskew/sampling blocks deskew and sample incoming data on respective data lines based upon a clock signal to produce deskewed data. The data group deskew module receives deskewed data from each of the plurality of data line deskew/sampling blocks and removes inter-data line skew from the deskewed data to produce received data. The plurality of data line deskew/sampling blocks and the data group deskew module can be configured in a first mode when supporting an aspect of the HyperTransport Standard and configured in a second mode when supporting the at least one other interface standard.

Abstract: An apparatus and method for micro-tuning an effective clock frequency of a core in a microprocessor. The apparatus includes a microprocessor having at least one core with logic configured to transition between states, a clock signal coupled to the microprocessor, the clock signal having a predetermined clock frequency based on a worst-case clock frequency and a predetermined clock period. The apparatus further including at least one voltage drop sensor coupled to the core, the sensor being configured to generate an output signal for detecting a voltage drop in the core and to determine whether or not the output signal is detected within the clock period and, if the output signal is not detected, the sensor dynamically adjusts the clock period of the clock signal provided to the core to allow more time to complete state transitions, such that, dynamically adjusting the clock period effectively changes an effective core clock frequency.

Abstract: An integrated circuit device includes a transmitting means for transmitting transmit data to an external signal line and a storing means for storing a first value representative of a transmit phase adjustment that is used to adjust when the transmit data is transmitted by the transmitting means. The first value is determined based on information stored in a memory device external to the integrated circuit device.

Abstract: Systems, methods, and other embodiments associated with synchronizing link delay is provided. In one example system, a system for synchronizing signal communication between a first electronic component and a second electronic component connected by one or more serial communication links comprises an offset logic configured to apply a selected offset to signal transmissions to cause a unidirectional delay between the first and the second electronic components to be synchronized for both directions of signal transmissions. A synchronization logic is configured to determine the uni-directional delay for signal transmissions between the first and second electronic components and configured to control the offset logic to apply the selected offset.

Abstract: A semiconductor memory device includes a mode register set for establishing information on a delay time, a delay time calculator for calculating an I/O path delay time of a data clock on a basis of a unit period of a system clock, and a delay locked clock generator for reflecting in the data clock a value of subtracting an output of the delay time calculator from the information established in the mode register set.

Abstract: In one embodiment, an apparatus comprises a first clocked storage device operable in a first clock domain corresponding to a first clock signal. The first clocked storage device has an input coupled to receive one or more bits transmitted on the input from a second clock domain corresponding to a second clock signal. The apparatus further comprises control circuitry configured to ensure that a change in a value of the one or more bits transmitted on the input meets setup and hold time requirements of the first clocked storage device. The control circuitry is responsive to a sample history of one of the first clock signal or the second clock signal to detect a phase relationship between the first clock signal and the second clock signal on each clock cycle to ensure the change meets the setup and hold time requirements.

Abstract: A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

Abstract: Two or more circuits (e.g. processing cores of a graphics processor) operate synchronously at a fast clock frequency. A core interface to each of the processing cores is designed to communicate in synchronous fashion with one or more other core interfaces at a slow clock frequency. The fast clock is distributed to each processing core in a manner that provides minimized skew and jitter, e.g. with a balanced tree network. The slow clock is locally derived from the fast clock in each core interface. One of the core interfaces is selected to provide a synchronism signal, and the synchronism signal is distributed among the multiple core interfaces to synchronize the locally derived slow clocks.

Abstract: A timing circuit for generating a timing signal having a predetermined relationship with a reference signal. The timing circuit includes a locked loop for generating the recovered clock signal, comparing the phase of the reference signal to the phase of the timing signal, and adjusting the phase of the timing signal based on the comparison; and a PVT (Process-Voltage-Temperature) line operatively associated with the locked loop so that PVT drift in the PVT line counters PVT drift in the locked loop.

Abstract: Software-based audio rendering is described. A particular implementation includes computer readable media configured to measure a first drift rate between an external clock and an audio clock until the drift reaches a threshold. Responsive to the drift reaching the threshold and based upon the first drift rate, the implementation manipulates the audio clock to achieve a second drift rate having a smaller value and an opposite polarity from the first drift rate.

Abstract: Systems and methods are disclosed herein to provide signal monitoring techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a phase detector circuit that receives an input signal and samples the input signal to provide binary state signals. A signal monitoring circuit decodes the binary state signals and provides at least one output signal indicating for the input signal path equalization and/or duty cycle distortion.

Abstract: A CAN communication module (10) comprising a protocol kernel (14) and a CAN logic block (12) is provided. The protocol kernel includes a CAN bus interface and the CAN logic block includes a module interface for connection to an external peripheral bus (22), a message RAM (28) and a CAN message handler (26). The protocol kernel (14) and the CAN logic block (12) have separate clock inputs (32,36).

Abstract: The method is applicable to the reception of data in the case of a digital transmission in which the pieces of data are transmitted by a unit of equipment A to a unit of equipment B with an accompanying clock signal HA. This accompanying clock signal transmitted by the transmitter equipment A is used by the receiver equipment B to sample the transmitted data. An alternation is effected at the receiver equipment B between a phase of operation during which the clock signal HA accompanying the data is replaced by a local clock signal HLS of the same frequency and a phase of operation during which the local clock signal is periodically re-synchronized with the accompanying clock signal. Means to implement the method are also disclosed.

Abstract: Variable compensation for part to part skew of components in a substrate-mounted circuit is described. The variability may be provided through a computer software program acting on a programmable delay buffer such that compensation for a skewed signal may be continuously checked against a reference signal or through other methods. The skewed signal may be delayed until the signal matches, within a predetermined margin of error, the reference.

Abstract: A true random number generator may comprise a multi-gigabit transceiver with a transceiver to receive a signal of predetermined source data. Recovery circuitry of the transceiver may be operable to recover data from the received signal. A controller may stress the recovery circuit to cause a portion of the data recovered to differ from the respective portion of the predetermined source data. An extractor may define numbers for a true random number sequence based on differences between the recovered data and the predetermined serial source data over an interval of time. In a particular example, the controller may influence at least one of the serial data transfer rate, the number of sequential same-state bits for the predetermined source data, and the stability of a clock signal to be recovered by a portion of the recovery circuit.

Abstract: The lane skew alignment device of the present invention facilitates the use of the SFI-5 standard interface in an FPGA without the need to rely on feedback signals from a remote device. The delay between lanes is determined using a D-Flip Flop or other type of phase comparator. To minimize the components needed to physically implement the solution a cross-point switch is used to select one of the parallel lanes at a time to be compared to a reference lane, over which the same test signal is transmitted.

Abstract: Some embodiments of the invention provide a training sequence that may be used in a deskewing process or a protocol to be implemented in a training sequence deskew. Embodiments may also comprise a training pattern that allows for header or frame alignment.