Abstract: A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is calibrated during a power on the initialization sequence in concert with a DDR memory in a system environment, thereby minimizing the effects of system delays and increasing both device and system yield. An additional embodiment also includes programmably delaying the incoming dqs signal.

Abstract: Even in a case where a master-CPU of an image forming section and a slave-CPU of a sheet transportation section are driven by respective oscillation circuits with different oscillation accuracies, a large difference in accuracy is not caused in transfer sheet transportation speed driven by clock signals formed by the respective oscillation circuits. In the master-CPU and the slave-CPU that are cascadingly connected to each other, in order to calculate a clock frequency of an oscillation circuit of the target-CPU, a predetermined time transmitted from the other CPU connected to the target-CPU is counted by the clock signal of the target-CPU. With reference to the predetermined time, an operating process, such as division of an acquired counter value by the predetermined time, acquires an error of the clock frequency of the oscillation circuit driving the slave-CPU, and corrects the error, thereby improving the accuracy thereof.

Abstract: A clock skew controller for adjusting a skew between a first clock, which is input to a first clock mesh, and a second clock mesh input to a second clock mesh, includes a pulse generator adapted to output a pulse signal corresponding to a delay time between a first output clock output from the first clock mesh and a second output clock output from the second clock mesh, a pulse width detector adapted to generate a digital signal corresponding to a pulse width of the pulse signal, and a clock delay adjuster adapted to delay one of the first and second clocks by a time corresponding to the digital signal.

Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.

Abstract: A system and method for performing dynamic trimming. Specifically, the system comprises a clock for generating a reference clock signal. The reference clock signal comprises a first frequency that is a factor of a second frequency of a signal (e.g., data clock signal from DDR memory). A counter is coupled to the clock and generates a plurality of clock pulses based on pulses of the reference clock signal. The plurality of clock pulses is generated at a slower frequency from the first frequency for low power operation. A phase length detector is coupled to the counter and comprises a trimmer chain for detecting an average length of at least one of the generated plurality of clock pulses. A transformation module is coupled to the phase length detector for transforming the average length to a phase delay of the signal.

Abstract: An embodiment of a system on a chip includes a reference clock circuit configured to produce a reference clock signal, a first clock circuit configured to produce a first clock signal, and adjustment circuitry. The adjustment circuitry is configured to make a determination of whether a characteristic of the reference clock signal compares unfavorably with a characteristic of the first clock signal, and when the characteristic of the reference clock signal compares unfavorably with the characteristic of the first clock signal, to adjust a parameter of the first clock circuit that results in tuning the first clock signal.

Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Abstract: A semiconductor integrated circuit apparatus, comprising a data transmitter circuit, and a plurality of data receiver circuits each having a data converter circuit which restores each of bits of identification number data and transfer data from a shift register of the data transmitter circuit to 2-bit complementary data transmitted via first and second transmission lines, a reception control circuit which, when a transfer completion signal has been received via a third transmission line, compares an allocated identification number with the restored identification number data, and a shift register provided in association with the reception control circuit, wherein each reception control circuit feeds transfer data transmitted from the data transmitter circuit corresponding to the identification number data to the associated shift register in accordance with a result of comparison between the identification number data and the allocated identification number.

Abstract: De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.

Abstract: A phase amount added to a clock signal or a plurality of data signals for adjusting a phase relationship therebetween in a reception apparatus is changed, and, a result of the phase adjusting operation is stored when the phase amount added to the clock signal or the plurality of data signals is changed.

Abstract: Fixing a problem is usually greatly aided if the problem is reproducible. To ensure reproducibility of a multiprocessor system, the following aspects are proposed: a deterministic system start state, a single system clock, phase alignment of clocks in the system, system-wide synchronization events, reproducible execution of system components, deterministic chip interfaces, zero-impact communication with the system, precise stop of the system and a scan of the system state.

Abstract: Systems and methods are described for synchronizing an HVAC control system. A method, includes: a synchronization sequence including: reading a base time from an internal clock at a first time and saving the base time; measuring an elapsed time interval, from the first time to a second time, by counting an external clock using a frequency counter; and then resetting the internal clock to the base time plus the elapsed time.

Abstract: Disclosed is a method of minimizing clock uncertainty using a multi-level de-skewing technique. The method includes the steps of obtaining a chip wherein at least a portion of the chip has a regular array of buffers on multiple levels, the buffers being driven by first drivers and the first drivers being driven by second drivers; grouping the buffers in a first direction to create clusters with the same number of buffer inputs, wherein if there are not the same number of buffer inputs in each cluster, then adding dummy buffers to the cluster with a deficient number of buffer inputs; wiring outputs of the first drivers together in a second direction, wherein the first and second directions are orthogonal; and wiring outputs of the second together in the second direction.

Abstract: A high-definition multimedia interface (HDMI) receiver recovers high speed encoded data which are transmitted differentially over data channels of a lossy cable, along with a clock. Inter symbol interference, high-frequency loss, skew between the clock and data channels, and differential skew within a differential signal are compensated by analog circuits which are automatically tuned for best performance by observing the quality of the recovered analog signal. Oversampling is used to provide a 24-bit digital representation of the analog signal for determining the quality of the signal. A corresponding method of deskewing a differential signal and a system and circuit therefor are also provided.

Abstract: A method for generating a skew schedule for a clock distribution network generates a schedule that accounts for both the timing requirements of the memory elements at the endpoints of the clock distribution network and the timing requirements of the gating signals that feed clock gates and other clock control elements within the clock distribution network. The method provides a total solution to the skew scheduling problem by way of a two-phase iterative process. The two phases of the process alternately keep track of the schedule generated by first taking the gating elements of the clock distribution network into account, followed by balancing any remaining skew that may exist on the memory elements of the same clock distribution network. Finally, the method describes a procedure to post-process the skew schedule to ensure that it can be implemented using a clock tree generation tool.

Abstract: A method of programming an infusion device includes receiving an infusion rate for a time period, wherein the time period overlaps with a predefined start of a predefined period of the infusion device. The time period is converted into (1) a first converted time period extending from a start of the time period to the predefined start of the predefined period, and (2) a second converted time period extending from the predefined start of the predefined period to an end of the time period. The infusion device is programmed with the infusion rate for the first converted time period and the second converted time period.

Abstract: For synchronizing a master device and a slave device connected by a data transfer link, the master device measures a phase offset in a signal received from the slave device with respect to the master's clock signal. The master determines a control symbol based on the phase offset. The master encodes the control symbol in a transmit signal for the slave. The slave decodes the control symbol from the signal received from the master. The slave uses the control symbol to adjust the phase shift to compensate for the phase offset of a signal to be transmitted to the master device. When the phase compensated signal is received at the master, its phase offset is smaller than the original phase offset. This procedure can be performed iteratively until the phase offset is within a desired tolerance.

Abstract: The invention relates to an automation device, with which a multiplicity of physically distributed functional units communicate with each other by means of a common transmission protocol. The device has a microcontroller (110), which is assigned at least one clock generator (120) and one memory unit (150), and which is connected at least to one data source (140), which is designed to output a data bit-stream to be transmitted.

Abstract: Adjusting a local frequency source is disclosed. A local frequency comparison data is compared with a received frequency comparison data, wherein the local frequency comparison data reflects a difference, if any, between a locally measured AC frequency and a frequency generated using the local frequency source. The local frequency source is adjusted based at least in part on a result of the comparison.

Abstract: A circuit is described for automatically adjusting a phase of an input register load clock to be synchronized with transitions of data bits forming an n-bit word. The circuit detects the first transition of a data bit in the n-bit word. The circuit then time-shifts the input clock, to generate a shifted clock, so that a triggering edge of the shifted clock occurs sometime after generation of the transition detect signal, such as in the middle third of a data cycle. Shifting the input clock may be performed by multiplying the input clock to generate a plurality of sub-clock cycles and selecting one of the sub-clock cycles as the start of the shifted clock cycle. The parallel data are applied to inputs of input registers clocked using the shifted clock as the load clock. Thus, the load clock occurs at an optimum time near the middle of a data cycle.

Abstract: An important component in digital circuits is a phase rotator, which permits precise time-shifting (or equivalently, phase rotation) of a clock signal within a clock period. A digital phase rotator can access multiple discrete values of phase under digital control. Such a device can have application in digital clock synchronization circuits, and can also be used for a digital phase modulator that encodes a digital signal. A digital phase rotator has been implemented in superconducting integrated circuit technology, using rapid single-flux-quantum logic (RSFQ). This circuit can exhibit positive or negative phase shifts of a multi-phase clock. Arbitrary precision can be obtained by cascading a plurality of phase rotator stages. Such a circuit forms a phase-modulator that is the core of a direct digital synthesizer that can operate at multi-gigahertz radio frequencies.

Abstract: Data and clock synchronization within a gigabit receiver is maintained throughout the data byte processing logic of the receiver by utilizing the same byte clock signal. The deserialization clock signal that is used to deserialize the received serial data stream is phase coherent with the distributed byte clock signal used within the physical coding sublayer (PCS), thus establishing reliable data transfer across the physical media attachment (PMA) and PCS layers of the gigabit receiver while maintaining a known, fixed latency. The phase relationship between a derived bit clock signal and the byte clock signal is shifted in a manner that achieves coarse data alignment within each data byte without affecting the latency. Conversely, the coarse data alignment is combined with a data alignment toggling procedure to reduce data alignment granularity with minimized latency changes.

Abstract: A buffering apparatus to process digital communication signals includes a plurality of buffers, a processing unit, and programmed memory. The programmed memory has instructions directing the processing unit to process the digital samples corresponding to a group of symbols to be processed in a plurality of buffers. The digital samples start in a first buffer of the plurality of buffers and end in a second buffer of the plurality of buffers. The digital samples are received at a third buffer of the plurality of buffers during the processing of the digital samples.

Abstract: To provide a data fetch circuit, which reliably cuts off transmission of a high impedance state of a data strobe signal even if a manufacture condition or an operation condition is changed, and a control method thereof. The data fetch circuit includes an RL measuring part 10 measuring a latency measurement value RLB from an input of a read instruction signal RD to a valid edge of a data strobe signal DQS and an RL count comparing part 30 outputting a BL count start signal BST giving an instruction of a cancel of the cut-off of the data strobe signal DQS after standing by during the time based on the latency measurement value RLB in accordance with an input of a delay read instruction signal RDD.

Abstract: A design structure is described for dynamically aligning clocks in independent clock domains with minimal latency. In the preferred embodiments, a reference clock in the destination clock domain that is some multiple times the data clock of the destination clock domain is used to sample a data sample signal from the source domain. The sampled data is used to determine at what time slice of the reference clock the data sample signal is changing and therefore at what phase of time slice or phase of the data clock the clocks can be aligned to ensure valid data will be transferred between clock domains.

Abstract: An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and one or more receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector that both indicate a lockout time. The select vector is employed to select a delayed version of the reference clock that lags the reference clock by the lockout time. The lockout time is slightly less than a number of cycles of the reference clock. The one or more receivers are each coupled to the delay-locked loop. Each of the one or more receivers receives the encoded select vector and a corresponding strobe, and locks out reception of the corresponding strobe for the lockout time following transition of the corresponding strobe. The encoded select vector is employed to determine the lockout time by selecting a delayed version of the corresponding strobe.

Abstract: An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.

Abstract: This invention provides an image forming apparatus that suppresses a control error between CPUs when the CPUs operate in cooperation with each other in distributed control by the CPUs. To accomplish this, the image forming apparatus utilizes a distributed control system. Respective CPUs measure time interval concerning image formation processing using their built-in clock oscillators, and perform operations in cooperation with each other. Correction coefficients are calculated based on the time interval measured by the respective CPUs to correct a measurement error generated by the operation an error of the respective clock oscillators. Clock count values each indicating a timing to drive a load is corrected based on the correction coefficients.

Abstract: Methods and apparatus provide a delayed clock signal to a plurality of serially connected processing elements, such as a bidirectional pipeline processor. The processing elements include forward and reverse processing paths and forward and reverse processing time intervals along the respective paths. The forward and reverse processing time intervals begin when a block of data, such as encryption data, is gated into an individual processing element for processing and terminate when the processed block of data is gated into a subsequent adjacent processing element along the respective forward or reverse processing path. A clock signal distribution circuit provides a clock signal to the plurality of processing elements such that the clock signal arrives at successive processing elements along the clock signal distribution circuit with an increasing amount of delay so that one of the forward or reverse processing time intervals is greater than the other.

Abstract: A memory controller includes an output buffer for receiving a clock signal and outputting the clock signal to an external memory; and a replica buffer for receiving the clock signal and outputting the clock signal to a counting circuit; wherein the replica buffer and the output buffer have the same delay time such that the clock signal received by the counting circuit can be synchronized with that received by the external memory, and therefore the counting circuit can accurately count to a predetermined time according to the clock signal and output an enabling signal to enable a data control signal. The present invention further provides a signal synchronizing method for the memory controller.

Abstract: Return path clocking mechanism for a system including a master device connected to a plurality of slave devices via a bus. The master device may first generate a global clock. The master device may transmit data to one or more of the slave devices at a rate of one bit per clock cycle. One or more of the slave devices may transmit data to the master device at a rate of one bit per two consecutive clock cycles. The master device may sample the transmitted data on the second cycle of each two consecutive clock cycle period. Alternatively, the slave devices may transmit data to the master device at a rate of one bit per N consecutive clock cycles, where N?2, and the master device may sample the transmitted data on the Nth cycle of each N consecutive clock cycle period.

Abstract: A microprocessor programmable clock calibration device compares, in response to a calibration command from a programmable processor, turns on a normally off reference oscillator clock, compares the frequency of the reference oscillator clock with the frequency of a calibratable oscillator clock, turns off the reference oscillator clock and adjusts, in response to a difference in those frequencies, the frequency of the calibratable oscillator clock towards that of the reference oscillator clock.

Abstract: In order to provide a semiconductor memory apparatus which can adjust the locked loop circuit such as a DLL in detail after producing the semiconductor memory apparatus, and moreover, which can adjust the locked loop circuit by using a measuring apparatus which has a low testing frequency, an exclusive-OR circuit generates an adjusting clock signal TCLK obtained by multiplying a frequency of a pair of test clock signals which respectively have a phase difference. A DLL circuit inputs the adjusting clock signal TCLK in place to an external clock signal CLK. The counter circuit counts the control clock signal CCLK outputted from the DLL circuit for a predetermined time. A comparator compares a counted value to an expected value and outputs a comparison result. A phase adjusting circuit outputs an adjusting signal to a delay circuit inside the DLL circuit based on the comparison result outputted from the comparator, and adjusts a phase of the control clock signal CCLK outputted from the DLL circuit.

Abstract: A method for adjusting the working frequency of a chip is provided. The method detects a frequency adjustment range of a graphic chip when a system is booted. Then, an application program in full screen mode is executed, and a control hot key is enabled. Afterwards, an input of the control hot key is received to display a user interface. Finally, an input frequency inputted from the user interface is received, and the working frequency of the graphic chip is adjusted according to the input frequency in the frequency adjustment range. Therefore, even though the application program is executed in full screen mode, the working frequency of the graphic chip can still be adjusted according to requirements in any time, which is convenient for the user.

Abstract: Systems and methods for distributing a clock signal are disclosed. In some embodiments, systems for distributing a clock signal include a plurality of resonant oscillators, each comprising an inductor; and a differential clock grid that distributes the clock signal. The differential clock grid is coupled to the plurality of resonant oscillators and the clock signal, and the inductances of the inductors are configured such that a resonant frequency of the plurality of resonant oscillators is substantially equal to the frequency of the clock signal.

Abstract: An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.

Abstract: A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device, a second frequency calibration device and a third frequency calibration device to share the same oscillator as so to perform multi-stage clock frequency resolution calibrations for different frequency-tuning ranges. This can bring an optimal frequency resolution, greatly reduce system complexity and save element cost.

Abstract: A clock signal generator for a USB device. The clock signal generator includes a control circuit and a clock generator that does not need to include a crystal oscillator. The control circuit counts the cycle of the clock signal during the period between two sync signals successively inputted, and generates a frequency control signal corresponding to the count value. The clock generator generates the clock signal with a frequency corresponding to the frequency control signal. The clock signal generator can generate a clock signal that is suitable for the data transfer rate defined, in the USB specification. In addition, the clock; signal generator can generate an RX clock signal so that an RX data signal can be recovered with its energy being stable.

Abstract: A method and multi-component electronic module device are provided that control the timing of output of data from a plurality of components on the multi-component module. One or more of the components are programmed to delay outputting data by a corresponding amount of time. In one embodiment, the one or more components are programmed such that all of the components output data at substantially the same time when they respond to a control signal. This is particularly useful for multi-component modules that are configured to respond to control signals in a so-called fly-by (or other) configuration that results in the control signal arriving at the components at different times causing the components to react to the control signal at different times.

Abstract: Clock processors are provided to economically control system and data clocks in high-speed signal converters. The processors generally include at least one of a delay-locked loop, phase-locked loop or a duty cycle stabilizer which generates an error signal in its operation. In the example of a stabilizer, it is configured to respond to an input clock to initiate a first portion of each cycle of the system clock and to include a control loop to provide an error signal that controls a second portion of the cycle to thereby maintain a selected duty cycle. The processors also include a data clock aligner configured to share the error signal and provide a data clock that is delayed by a selected delay from a selected one of the input and system clocks. In addition to providing effective control that is independent of disturbing effects (e.g., temperature and clock rate), the shared use reduces processor costs.

Abstract: A semiconductor memory device, which includes a clock tree circuit for correcting the duty cycle of a clock. The device sets a beta ratio to cause a constant duty cycle by using a reference clock having a constant duty cycle in a test mode, and then applies the set beta ratio to a DLL clock outputted from a delay-locked loop. Then, when the duty cycle of the DLL clock, to which the beta ratio has been applied, is not constant, the duty cycle of the DLL clock is corrected in the delay-locked loop.

Abstract: Disclosed are a method and system for calculating clock offset and skew between two clocks in a computer system. The method comprises the steps of sending data packets from a first processing unit in the computer system to a second processing unit in the computer system, and sending the data packets from the second processing unit to the first processing unit. First, second, third and fourth time stamps are provided to indicate, respectively, when the packets leave the first processing unit, arrive at the second processing unit, leave the second processing unit, and arrive at the first processing unit. The method comprises the further steps of defining a set of backward delay points using the fourth time stamps, and calculating a clock offset between clocks on the first and second processing units and clock skews of said clocks using said set of backward delay points.

Abstract: A frequency regulator for varying a clock frequency of a power-supplied consumer operated in a clocked manner, wherein the frequency regulator is implemented to perform an overall variation of the clock frequency from an actual frequency to a set frequency, such that the overall variation is obtained by a plurality of clock changes, each with a different amount of change, wherein each of the respective amounts of change depends on a power change caused by the associated clock frequency change.

Abstract: The present invention discloses a computer motherboard, which comprises: at least one memory module slot, a flash memory, a central processing unit socket; wherein, the memory module slot is used to plug at least one memory module; the flash memory is used to store BIOS programming codes, in which the BIOS programming codes are provided with at least one memory configuration programming codes for configuring the memory frequency and memory timing of the memory module; the central processing unit socket is used to plug the CPU, and the CPU is at least used to execute the memory configuration programming codes, so, after execution, they could provide a plurality of parameter options for memory frequency and memory timing of the memory modules to be selected one from them.

Abstract: An apparatus and method is disclosed for providing capacity on demand using control to alter latency and/or bandwidth on a signaling bus in a computer system. If additional capacity is required, authorization is requested for additional capacity. If authorized, bandwidth of the signaling bus is increased to provide additional capacity in the computing system. Alternatively, upon authorization, latency of data transmissions over the signaling bus is reduced. In another alternative, upon authorization, memory timings are adjusted to speed up memory fetches and stores.

Abstract: The present invention provides a method and mechanism for data recovery with phase synchronized clock using interpolator and timing loop module and a data latching circuit. The interpolator can be considered as a programmable delay circuit with a specified delay resolution over the clock period.

Abstract: Methods and apparatuses for manufacturer to present Web-based edu-games so as to train retail staff member about the manufacturer and its products and to access edu-game data and retail sales data from a database. A Website can be created to provide a point of interaction between the manufacturer, retailer, and retail staff member. By accessing this Website, the retail staff member is presented with the web-based edu-games and learns about the manufacturer and its products. The retail staff member can be presented with incentives by the manufacturer for completing the web-based training off time, which may prevent the retailer from paying for the costs of training the retail staff member. Alternately, retailers can also do training in-house (e.g., if required by statute). Manufacturers and retailers compare education levels to sales data to determine the effects of the training.

Abstract: Method for monitoring a real time clock and a device having real time clock monitoring capabilities, the device includes: (i) a real time clock tree, (ii) a clock frequency monitor that is adapted to determine a frequency of a real time clock signal, during a short monitoring period; (iii) a monitoring enable module, adapted to activate the clock frequency monitor during short motoring periods and to deactivate the clock frequency monitor during other periods, wherein the monitoring enable module is adapted to determine a timing of the short monitoring periods in a non-deterministic manner; and (iv) a real time clock violation indication generator adapted to indicate that a real time clock violation occurred, in response to an error signal provided from the clock frequency monitor.

Abstract: A system includes a memory controller and a plurality of memory devices connected in-series that communicate with the memory controller. Each of the memory devices has multiple independent serial ports for receiving and transmitting data. The memory controller a device address (DA) or ID number for designating a device that executes a command. Data contained in the command sent by the memory controller is captured by an individual link control circuit, in response to internally generated clock with appropriate latencies. The captured data is written into a corresponding memory bank. The data stored in one of a plurality of memory banks of one memory device is read in accordance with the addresses issued by the memory controller. The read data is propagated from the memory device through the series-connected memory devices to the memory controller.

Abstract: A method of transmitting encoded computer display images between computers over a nondeterministic network is disclosed. During a display session in which images are transmitted from a host to a client, the client requests sections of encoded image updates at a predetermined time in advance of when the requested at least one section is to be transmitted by the display controller. When the requested section is received, a time value is compared to a display controller timing value and, if the difference between the compared times is outside of an acceptable range, the client adjusts a predetermined time at which time the client requests image sections from the host.