Abstract: A processor capable of changing redundant processing node comprises a plurality of processing nodes and a plurality of comparators. The plurality of processing nodes comprises a first processing node, a second processing node, and a third processing node, wherein the first processing node performs a first computation, the second processing node selectively performs the first computation or a second computation, and the third processing node performs the second computation. The plurality of comparators comprises a first comparator and a second comparator, wherein the first comparator connects to the first and second processing nodes to compare whether the results of the first computation performed by the first and second processing nodes are identical, and the second comparator connects to the second and third processing nodes to compare whether results of the second computation performed by the second and third processing nodes are identical.

Abstract: Methods, systems, and devices for memory data correction using multiple error control operations are described. A single command may be received to correct an error detected in data stored by a memory array. A first error control operation and a second error control operation may be implemented based on the single command. The first error control operation may be performed on the data stored by the memory array using one or more different reference voltages to read the data. The error may be determined to remain in the data after performing the first error control operation. The second error control operation may then be performed on the data stored by the memory array. The second error control operation may use one or more voltage distributions associated with the memory cells of the memory array.

Abstract: The present disclosure relates to an assembly including a first processor having a first core, a second core and a controller, and a second processor having a first core, and wherein the first core and the second core of the first processor, and the first core of the second processor are configured to execute a first procedure. The controller of the first processor is configured to compare a first result from executing the first procedure on the first core of the first processor with a second result from executing the first procedure on the second core of the first processor; and comparing each of the first and second results with a third result from executing the first procedure on the first core of the second processor, if the first and second results differ from one another.

Abstract: The controlling apparatus for an industrial product of this disclosure has a couple of microcomputers each of which has a CPU and a memory and each of which runs the same controlling program as well as the same diagnostic program sequence parallelly and simultaneously. After the CPU of the microcomputer writes the calculated result of the diagnostic program sequence in the predetermined area of the storing area for monitoring value, such CPU send the same calculated result to the other one of the microcomputers (receiving microcomputer). The CPU of the receiving microcomputer makes a diagnosis for finding whether or not the received result is identical with its own calculated result.

Abstract: Provided are a computer program product, system, and method verifying mirroring of source data units to target data units. Source data units in a source storage are mirrored to corresponding target data units in a target storage. The source data units are read to compare to corresponding mirrored target data units. The read source data units that did not match the corresponding target data units are saved in source version data. The source data units that were read and did not match the corresponding target data units are read. The mirroring of the source data units are verified in response to determining that for each mirrored source data unit, one of a read source data unit and the read source data unit saved in the source version data matches the corresponding target data unit.

Abstract: This disclosure describes hardware-based mutexes that employ software process authentication to prevent a software process from releasing the lock of a mutex locked by another software process. For example, systems are described in which a mutex controller receives a request from a process to lock a mutex. The mutex controller locks the mutex, writing a process key and process identifier to one or more hardware registers associated with the mutex. If the mutex controller receives a request to release the lock on the mutex, the mutex controller determines if the key received with the request matches the process key written in the one or more hardware registers of the mutex and, if so, releases the lock on the mutex.

Abstract: A method for balancing load across multiple file servers is disclosed. In one embodiment, such a method includes monitoring load experienced by multiple file servers arranged in an active-active configuration. The method receives, from a client node, a request for an address associated with one of the file servers. The method determines a particular file server of the file servers that, if assigned to the client node, would reduce load imbalance between the file servers. In certain embodiments the particular file server is the file server experiencing the least load. The method returns, to the client node in response to the request, an address associated with the particular file server, thereby enabling the client node to mount the particular file server to access files thereon. A corresponding system and computer program product are also disclosed.

Abstract: The present disclosure discloses a parameter configuration method and apparatus, and a display device, belonging to the field of display technologies. The method is applicable to a controller connected to a plurality of drivers, and includes: sending a component information request instruction to a first driver over a first signal line, wherein the first driver is one of the plurality of drivers; receiving a component information response instruction sent over the first signal line by the first driver, wherein the component information response instruction includes component information; determining configuration parameters corresponding to the component information; and performing parameter configuration for the plurality of drivers by using the determined configuration parameters.

Abstract: In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first memory error packet associated with a first memory; receiving, with the first buffer, a second memory error packet associated with a second memory; transmitting a first reading request for reading the first memory error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central memory error management unit (MEMU); in response to receiving the first reading request, reading the first memory error packet from the first buffer, transmitting the first memory error packet to a controller of the central MEMU, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second memory error packet.

Abstract: The present disclosure generally relates to improved foggy-fine programming. Rather than initially writing to SLC and then later performing a foggy write to QLC with the data read from SLC and then a fine write to QLC with data re-read from SLC, the foggy write to QLC can be performed in parallel to the initial writing to SLC using the same buffer. Once the foggy write to QLC has completed, and the writing to SLC has also completed, the data buffer can be released. The data written in SLC is then be read from SLC and passes through a relocation buffer for the first and only time to then be written using fine programming to QLC. Thus, the data only passes through the relocation buffer one time and the relocation buffer can be freed to usage after only one pass of the data therethrough.

Abstract: Techniques to provide direct access to backup data are disclosed. An indication is received to provide access to backup data backed up previously to a target device. The backup data as stored on the target device is used to spawn on the target device a logical volume corresponding to the backup data. Access to the logical volume as stored on the target device is provided to a production host.

Abstract: Aspects of the present invention disclose a method for avoiding overvoltages of a processor chip. The method includes one or more processors identifying one or more processing units of a computing device. The method further includes determining respective activity levels of one or more processing elements of the one or more processing units of the computing device. The method further includes determining respective voltages of the one or more processing units of the computing device. The method further includes regulating the respective voltages of the one or more processing units of the computing device based at least in part on the respective activity levels of the one or more processing elements.

Abstract: A computer system that has two or more processing engines (PE), each capable of performing one or more operations on one or more operands but one or more of the PEs performs the operations unreliably. Initial results of each operation are debiased to create a debiased result used by the system instead of the initial result. The debiased result has an expected value equal to a correct output where the correct output is the initial result the respective operation would have produced if the respective operation performed was reliable.

Abstract: A system, method and computer program product synchronize a plurality of processes of one or more applications executed by a plurality of processors. In addition to the processors, the system includes a plurality of memories with each memory associated with a respective process and configured to maintain a local count representative of a message of the respective process with which the memory is associated and at least one remote count representative of a message of a corresponding process executed by another processor. The system also includes a reflector configured to reflect the local count of the respective process to a remote count of the corresponding process. For synchronization, a first process of a first application executed by a first processor is configured to enter a delay period if the local count and at least one remote count maintained by the memory associated with the first process fail to match.

Abstract: A system for dynamically load-balancing at least one redistribution element across a group of computing resources that facilitates at least an aspect of an Industrial Execution Process in an M:N working configuration is illustrated.

Abstract: A distributed database system may implement dynamic quorum group membership changes. In various embodiments, a quorum set may maintain a replica of a data object among group members according to a protection group policy for the data object. A group member may be identified as to be replaced. In response, a new quorum set may be created from the remaining group members and a new group member. The protection group policy may be updated to include the new group members such that subsequently received updates are maintained at both the previous to quorum set and the new quorum set. Previously received updates may be replicated on the new group member. Upon completion of replicating the previously received updates, the protection group policy for the data object may be revised such that subsequently received updates are maintained at the new quorum set.

Abstract: According to one embodiment, a computing device comprises one or more hardware processor and a memory coupled to the one or more processors. The memory comprises software that supports a virtualization software architecture including a first virtual machine operating under control of a first operating system. Responsive to determining that the first operating system has been compromised, a second operating system, which is stored in the memory in an inactive (dormant) state, is now active and controlling the first virtual machine or a second virtual machine different from the first virtual machine that now provides external network connectivity.

Abstract: A distributed processing method to receive data by a plurality of servers each including a processor and a memory, and process the data by replicating, the method includes a first determination step in which the servers each receive the replicated data, and a first determination unit determines a degree of consistency of the received data and an output step in which the servers each receive a determination result of the degree of consistency of the data from the first determination unit, and if the determination result includes data that guarantees consistency, the server outputs the data that guarantees consistency. A first number of servers that are to receive the data is set in advance based on a prescribed allowable number of failures that defines the number of servers that can have failures, and an allowable number of byzantine failures that defines the number of servers that can have byzantine failures.

Abstract: A distributed computing system, such as may be used to implement an electronic trading system, supports a notion of fairness in latency. The system does not favor any particular client. Thus, being connected to a particular access point into the system (such as via a gateway) does not give any particular device an unfair advantage or disadvantage over another. That end is accomplished by precisely controlling latency, that is, the time between when request messages arrive at the system and a time at which corresponding response messages are permitted to leave. The precisely controlled, deterministic latency can be fixed over time, or it can vary according to some predetermined pattern, or vary randomly within a pre-determined range of values.

Abstract: An information processing apparatus that is capable of resuming an interrupted process without applying the time and effort more than needed to a user. A data transmission unit transmits execution data to a process execution apparatus. A detection unit detects an abnormal state of the information processing apparatus. A reboot unit reboots the information processing apparatus. An obtaining unit obtains an execution condition of the execution data by the process execution apparatus. The reboot unit reboots the information processing apparatus when the detection unit detects the abnormal state of the information processing apparatus. The transmission unit transmits the execution data to the process execution apparatus based on the execution condition obtained by the obtaining unit when the information processing apparatus was rebooted.

Abstract: A command to transfer data in a portion of a memory component to a recovery portion of a different memory component is received from a host system, wherein the portion of the memory component is associated with a portion of the memory component that has failed, and the data in the portion of the memory component is recovered and transferred to the recovery portion of the different memory component without moving or processing the data through the host system responsive to receipt of the command.

Abstract: A test method for a basic input/output system (BIOS), configured to test a computer device which includes the BIOS when a power on self test (POST) of the BIOS fails, is disclosed including following operations: enabling a fixing function of the BIOS by a debug port of a motherboard of the computer device; enabling a first memory device and disabling a second memory device, by the debug port; according to the fixing function, turning on the computer device by the first memory device; and determining whether the computer device is turned on successfully.

Abstract: Methods and systems for an extensible, universal ledger. One of the methods includes receiving at a journal manager engine a register transaction type request for a first transaction type, the journal manager engine reading and writing to a journal that stores a history of object state and of code by which object state is changed, wherein the register transaction type request is based at least in part on a template and specifies at least one action that can be performed as part of the first transaction type; writing the transaction type request to the journal including an operation definition for the first transaction type; receiving a transaction request of the first transaction type; obtaining the operation definition from the journal; executing an operation in response to the transaction request to produce a transaction result; and recording the transaction result in the journal.

Abstract: A new physical computer architecture that combines elements in a virtuous cycle to eliminate performance killing inefficiencies in compute systems and need never be physically repaired during its lifetime is described. The system comprises a three dimensional rectangular cube structure with integrated liquid cooling and a multi-dimensional direct network laced through it. The network comprises a distributed, dynamically adaptive, multiply-fault-tolerant routing protocol that can logically replace failed components.

Abstract: Systems and methods for fault tolerant computing in accordance with various embodiments of the invention are disclosed. Fault tolerant computer systems in accordance with a number of embodiments of the invention include multiple processing systems supervised by a Fault Management Unit (FMU). The FMU can build a representation of the state of all of the multiple processing systems and then determines which of the processing systems to utilize to perform a particular function based upon this state representation.

Abstract: A distributed database system may implement fast crash recovery. Upon recovery from a database head node failure, a connection with one or more storage nodes of a distributed storage system storing data for a database implemented by the database head node may be established. Upon establishment of the connection with the storage nodes, that database may be made available for access, such as for various access requests. In various embodiments, redo log records may not be replayed in order to provide access to the database. In at least some embodiments, the storage nodes may provide a current state of data stored for the database in response to requests.

Abstract: A method of performing failover for programmable logic controllers (PLCs) in an automation environment and controlling a physical system includes an input/output module receiving sensor inputs from field devices and creating a copy of the sensor inputs for a first group of PLC in a first PLC bank. The input/output module transfers the copy the sensor inputs to each PLC in the first group of PLCs and receives processing results from each PLC in the first group of PLCs in response to transferring the copy of the sensor inputs. The input/output module determines whether there are any inconsistencies between the processing results received from each PLC in the first group of PLCs. If there are any inconsistencies between the processing results received from each PLC in the first group of PLCs, a failover control process is initiated by sending a failover control message to a second input/output module.

Abstract: The present disclosure provides systems and methods for executing instructions. The system can include: processing unit having a core configured to execute instructions; and a host unit configured to: compile computer code into a plurality of instructions that includes a set of instructions that are determined to be executed in parallel on the core, wherein the set of instructions each includes an operation instruction and an indication bit and wherein the indication bit is set to identify the last instruction of the set of instructions, and provide the set of instructions to the core.

Abstract: An IC design enhancing tool for automatically reviewing and environmentally hardening an IC design layout. The IC design enhancing tool may be realized, for example, in software that scans through an IC netlist generated by an electronic design automation (EDA) tool and replaces components that are not compliant with one or more hardening criteria. The newly created netlist can then be re-checked by the EDA tool and an iterative process takes place between the EDA tool and the IC design enhancing tool until the final design layout is fully compliant for a given environment. Interrogation of the IC design layout involves determining if at least a portion of the hardware layout netlist meets one or more predetermined hardening criteria. If it does not, then one or more of the hardware components are replaced using one or more predefined hardened components.

Abstract: Disclosed are systems, methods, and non-transitory computer-readable storage media for efficiently monitoring the operating context of a computing device. In some implementations, the context daemon and/or the context client can be terminated to conserve system resources. For example, if the context daemon and/or the context client are idle, they can be shutdown to conserve battery power or free other system resources (e.g., memory). When an event occurs (e.g., a change in current context) that requires the context daemon and/or the context client to be running, the context daemon and/or the context client can be restarted to handle the event. Thus, system resources can be conserved while still providing relevant context information collection and callback notification features.

Abstract: A method for detecting a failure in an electronic signal processing system having a signal processing path comprises a configurable functional unit for performing a given function and at least one redundant version of the signal processing path including a corresponding configurable functional unit for performing the given function and configuring a first operating point for the functional unit in the signal processing path for performing the given function and configuring a second operating point for the corresponding functional unit in the redundant version of the signal processing path. The second operating point is different from the first operating point. The method further comprises applying a same input signal to the functional unit and the corresponding functional unit, comparing a first output signal produced by the functional unit with a second output signal produced by the corresponding functional unit, and deriving a failure indication from the comparing.

Abstract: A terminal device management method is implemented in a server coupled to a number of terminal devices. The terminal device management method includes acquiring network configuration information of each terminal device, grouping the terminal devices according to the network configuration information, selecting a preset proportion of terminal devices in each group as primary connection devices, maintaining a communication connection with the primary connection devices, and communicating with the other terminal devices in the groups through the primary terminal devices.

Abstract: A system that implements a data storage service may store data on behalf of storage service clients. The system may maintain data in multiple replicas of partitions that are stored on respective computing nodes in the system. A master replica for a replica group may increment a membership version indicator for the group, and may propagate metadata (including the membership version indicator) indicating a membership change for the group to other members of the group. Propagating the metadata may include sending a log record containing the metadata to the other replicas to be appended to their respective logs. Once the membership change becomes durable, it may be committed. A replica attempting to become the master of a replica group may determine that another replica in the group has observed a more recent membership version, in which case logs may be synchronized or snipped, or the attempt may be abandoned.

Abstract: A method and a system for implanting a handshake between a source cluster having files replicated to a destination cluster, the system comprising: a source cluster having a plurality of nodes and replication manager; and a destination cluster having a plurality of nodes, a replication manager and single port manager which run on each node of the destination cluster, wherein the replication managers of the source and destination clusters are configured to replicate all files and processes on the nodes of the source cluster to the nodes of the destination cluster, wherein all replicated files and processes register with the single port manager, and wherein the single port manager is configured to communicate with the source cluster via a single port and to provide descriptors of the required replicated files and processes via a kernel.

Abstract: Technologies are provided for determining an identity of a hardware device that transmitted an error message via a communication bus. A chipset of the communication bus can be configured to transmit an interrupt to an interrupt handler in response to receipt of the error message. The interrupt handler can be configured to determine an identity of the hardware device based on the contents of the error message. The interrupt handler can be configured to transmit a notification to an error remediation service, wherein the notification is associated with the identity of the hardware device. The remediation service can be configured to use the identity of the hardware device to perform one or more error remediation operations. In at least some embodiments, the interrupt handler is configured to store the identifier in a memory and the error remediation service is configured to retrieve the identifier from the memory.

Abstract: Certain embodiments provide an image processing apparatus including an image processing circuit configured to perform image processing on continuously captured image data frame by frame, a failure diagnosis processing circuit configured to diagnose a failure of the image processing circuit, and a failure diagnosis control circuit configured to control whether to perform failure diagnosis at an arbitrary frame.

Abstract: Provided is a security system or the like with which security can be improved. A security system according to one embodiment of the present invention is provided with: a packet reception means that receives a request from an intruding device that is attempting intrusion; a dummy resource characteristic information storage means that stores characteristic information for a plurality of virtual dummy resources; a dummy response generation means that generates a dummy response on the basis of the characteristic information in response to the request directed to the dummy resource; a dummy response transmission control means that controls a request end flag, which indicates the presence/absence of untransmitted dummy resources, on the basis of a timer value; and a dummy response transmission means that, on the basis of the request end flag, transmits the dummy response to the intruding device that transmits the request.

Abstract: Herein is disclosed an integrated input/output (“I/O”) processing system, comprising an I/O port, configured to receive I/O data and to deliver the I/O data to one or more processors; one or more processors, further comprising a first processing logic and a second processing logic, wherein the one or more processors are configured to deliver the received I/O data to the first processing logic and to the second processing logic, and wherein the first processing logic and the second processing logic are configured to redundantly process the I/O data; and a comparator, configured to compare an output of the first processing logic and an output of the second processing logic.

Abstract: One or more techniques and/or computing devices are provided for determining whether to perform a switchover operation between computing nodes. A first computing node and a second computing node, configured as disaster recovery partners, may be deployed within a computing environment. The first computing node and the second computing node may be configured to provide operational state information (e.g., normal operation, a failure, etc.) to a cloud environment node state provider and/or cloud persistent storage accessible through a cloud storage service. Accordingly, a computing node may obtain operational state information of a partner node from the cloud environment node state provider and/or the cloud storage service notwithstanding a loss of internode communication and/or an infrastructure failure that may otherwise appear as a failure of the partner node. In this way, the computing node may accurately determine whether the partner node has failed.

Abstract: Provided is a security system or the like with improved security.

Abstract: Example implementations relate to automatic diagnostic mode to identify a potential cause of a boot problem of a system. In an example, the automatic diagnostic mode iteratively isolates subsystems of the system in coordination with a baseboard management controller. For each iteration of subsystem isolation, a system boot is executed while a subsystem is isolated. The system boot is monitored against a watchdog timer of the baseboard management controller to determine if the system boot is successful. If the system boot is successful, the isolated subsystem is marked as a potential cause of the boot problem of the system. If the system boot is unsuccessful, the automatic diagnostic mode continues to iteratively isolate the subsystems.

Abstract: Techniques are disclosed for enabling the migration of data with minimized impact on consumers of the data. A data migration agent updates pointers to active data locations and coordinates a migration from a first data resource to a second data resource so that seamless migration may be carried out. A data access layer of a distributed computing environment can take advantage of the pointers and metadata written by the data migration agent to serve requests to resources of the distributed computing environment so that read availability is available regardless of migration status.

Abstract: A fault detection system on a circuit can detect a fault on the same circuit without using a duplicate circuit. A test signal can be generated based on an input signal, and the input signal and test signal can be sent through the circuit and the resulting signals can be compared to determine if any fault is present. In an embodiment, a function can be applied to bits of the input signal and bits of the test signal such that when the signals are compared after passing through the processing block that is to be tested, if the variation between the signals is above a predetermined amount, it can be determined that a fault has occurred. In other embodiments, a first function can be applied to the input signal, and a second function can be applied to the test signal, and the resulting outputs can be compared.

Abstract: A data processing system and methods for operating the same are disclosed. The method includes detecting a fault by comparing output signals from a first processing core and a second processing core, entering a safe mode based upon detecting the fault, completing transactions while in the safe mode, and determining whether the fault corresponds to a hard error. Based upon the fault corresponding to a hard error, one of processing cores is identified as a faulty core. The faulty core is inhibited from executing instructions and the other processing core is allowed to execute instructions.

Abstract: Disaster recovery is provided for Software Defined Network Attached Storage where the data backup is implemented using asynchronous remote data replication. An asynchronous replication facility is created between a primary storage array and a backup storage array. User filesystems being handled by a virtual data mover (VDM) and a configuration filesystem describing the location of the user filesystems on the primary storage array are replicated on the remote data facility to the backup storage array. During failover, all filesystems associated with the asynchronous remote data facility are failed over from a primary storage system associated with the primary storage array to a backup storage system associated with the backup storage array. Where an individual filesystem or individual VDM is to be failed over to the backup storage system, a separate asynchronous replication remote data facility is created to separately replicate data for the aspect to be individually failed over.

Abstract: The present invention relates to a data processing system and a method to process maritime software application as well as software updates on a ship comprising a main hardware-sever and a subordinate hardware-server with multiple maritime applications wherein the subordinate server and the main sever may change their respective role and function.

Abstract: Disaster recovery is provided for Software Defined Network Attached Storage where the data backup is implemented synchronous data replication. A synchronous replication remote data facility is created between a primary storage array and a backup storage array. User filesystems being handled by a virtual data mover (VDM) and a configuration filesystem describing the location of the user filesystems on the primary storage array are replicated on the remote data facility to the backup storage array. Individual filesystems, individual VDMs, or groups of VDMs may be selectively failed over from the primary storage array to the backup storage array.

Abstract: An apparatus to implement functional safety control logic (FSCL) in an autonomous driving system comprises a field-programmable gate array (FPGA) comprising logic elements to be partitioned into a first section to implement one or more safety cores and a second section to implement one or more non-safety cores, a memory to couple to the safety core or to the non-safety core, and a trusted execution environment (TEE) to couple to a remote administrator via a network and to apply a configuration received from the remote administrator to the FPGA. The safety core is to function as an active agent for FSCL during operation, and the non-safety core is to function as a failover agent during operation, and wherein the non-safety core is to perform a liveliness check on the safety core to monitor for a failover and to take over as the active agent in the event of a failover.

Abstract: A method of determining whether parametric performance of an inertial sensor has been degraded comprises: recording first data output from an inertial sensor; then recording second data output from the inertial sensor; comparing the first data output with the second data output; and determining whether the parametric performance of the inertial sensor has been degraded based on the comparison between the first and second data output.

Abstract: Disclosed is a high data integrity processing system (“HDIPS”) that includes a first processing device and a triple voted processing (“TVP”) device in signal communication with the first processing device. The first processing device has a high radiation resistance and includes a processor, a cache memory, and a computer-readable medium (“CRM”). The CRM has encoded thereon computer-executable instructions to cause the processer to execute a periodic first integrity check on the first processing device producing a first integrity result, which is transmitted to the TVP device. The TVP device includes firmware having encoded thereon machine instructions to, simultaneously with the periodic first integrity check, cause the TVP device to execute a second integrity check producing a second integrity result, compare the first integrity result with the second integrity result, and power reset the first processing device if the first integrity result does not match the second integrity result.