Abstract: Conventional semiconductor devices are problematic in that an operation cannot be continued in the event of a failure of one of CPU cores performing a lock step operation and, as a result, reliability cannot be improved. The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core and the second CPU core respectively diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnose result.

Abstract: Technology described herein includes an arrangement whereby a hardware-based solution is implemented to enable mirroring of NVRAM data in a master server directly to NVRAM in a sleeper server. Both the master server and sleeper server implement a like motherboard unit, which is configured to implement the mirroring technology. That is, the roles of master and sleeper may be reversed. The master server includes a hardware module that monitors (but does not affect) NVRAM operations at the master server, and replicates those operations via a high speed communications link, such as a fiber optic link, to the sleeper server. The term “high speed communications link” refers to a link with at least 2.5 gigabit speed, and preferably at least 5 gigabit speed. The sleeper server is configured to, when in sleeper mode, suspend control of its own NVRAM module. Instead, the NVRAM module is controlled by a module that is configured to receive NVRAM operations via the fiber optic link, and apply those operations.

Abstract: A system and method are provided for controlling mastership among multiple devices in a fault tolerant manner. The devices may be configured to transmit and receive redundant heartbeat signals to indicate the mastership state of the device. The signals may operate in a plurality of configurations including active-master, ready and not-ready. By detecting the signal configuration sent from the other devices, each device is capable of managing its own transitions into and out of mastership in order to ensure that there is one and only one device functioning as master.

Abstract: Disclosed is a storage system that suppress occurrence of a bottleneck in the storage system, efficiently uses a bandwidth of hardware, and achieves high reliability. A storage system includes a storage apparatus that stores data, a controller that controls data input/output with respect to the storage apparatus, and an interface that couples the storage apparatus and the controller. The storage apparatus has a plurality of physical ports that are couples to the interface. The controller logically partitions a storage area of the storage apparatus into a plurality of storage areas and provides the plurality of storage areas, or allocates the plurality of physical ports to the logically partitioned storage areas.

Abstract: An information processing system includes a first storage apparatus that includes first storage regions accessible by first virtual machines disposed in a first physical machine, and a second storage apparatus that includes second storage regions accessible by second virtual machines disposed in a second physical machine, wherein, when the second virtual machines execute first processing executed by the first virtual machines, the second storage apparatus stores first information in which information for identifying virtual machines that execute the first processing among the second virtual machines and information for identifying storage regions accessed by the identified virtual machines during the execution of the first processing among the second storage regions are associated with each other, and the first storage apparatus reconfigures a configuration of the first storage regions to be same as a configuration of a storage region corresponding to the first information among the second storage regions.

Abstract: Provided is a method for repairing one or more defective memory cells of a semiconductor memory device by a system management interrupt and a basic input/output system service routine. In the method, when an error has occurred in data read from the semiconductor memory device, the system management interrupt is generated to invoke the basic input/output system service routine. During execution of the basic input/output system service routine, a repair task is performed to one or more defective memory cells causing a read error in the semiconductor memory device using spare memory cells.

Abstract: An information processing device includes a processing unit, a control unit, and a monitoring unit. The processing unit executes an OS. The control unit controls an I/O device connected to the processing unit, and obtains, from the processing unit, management information about the I/O device. The monitoring unit monitors a boot-up state of the OS based on the management information obtained by the control unit.

Abstract: A technique for operating a group of virtual machines (VMs) includes utilizing a checkpoint procedure to maintain secondary VMs to assume tasks of primary VMs within a cluster in the event of failover. On failover of a first one of the primary VMs, a first one of the secondary VMs assumes the tasks from the checkpoint immediately preceding a failover event. Each of the primary VMs is connected to receive data from remaining ones of the primary VMs via an internal bus and process the data on receipt. Checkpoints for the primary VMs are synchronized. For each of the primary VMs, release to the external bus of data generated on the basis of received internal bus data is prevented until a subsequent checkpoint has occurred. On failover of one of the primary VMs, all of the primary VMs are directed to initiate failover to an associated one of the secondary VMs.

Abstract: A semiconductor storage device includes at least one memory from among a primary memory, a mirror memory storing data corresponding to data stored in the primary memory, and a buffer memory; and a controller that controls the at least one memory so as to store data in the at least one memory and read data from the at least one memory.

Abstract: A semiconductor integrated circuit pertaining to the present invention comprises a plurality of storage elements for storing and holding an input signal, a majority circuit that outputs a result of a majority decision of outputs from the plurality of storage elements; an error detector circuit that detects a mismatch among the outputs of the plurality of storage elements and outputs error signals; and a monitor circuit that monitors the error signals from the error detector circuit, wherein the monitor circuit, based on the error signals, orders a refresh action that rewrites data for rectification to a storage element in which an output mismatch occurs out of the plurality of storage elements and, if rewrite and rectification by the refresh action are unsuccessful, sends a notification to an external unit or process.

Abstract: A processing apparatus, comprising at least a first processing unit and a second processing unit, is proposed. The first processing unit comprises a set of first stateful elements, the second processing unit comprises a set of second stateful elements. A set of synchronization data lines may connect the first stateful elements to the second stateful elements in a pairwise manner. A control unit may control the first processing unit, the second processing unit and the synchronization data lines so as to copy the states of the first stateful elements in parallel via the synchronization data lines to the second stateful elements in response to a synchronization request. A method of synchronizing the processing units is also proposed.

Abstract: An information processing system, computer readable storage medium, and method for supporting resilient execution of computer programs. A method provides a resilient store wherein information in the resilient store can be accessed in the event of a failure. The method periodically checkpoints application state in the resilient store. A resilient executor comprises software which executes applications by catching failures. The method uses the resilient executor to execute at least one application. In response to the resilient executor detecting a failure, restoring application state information to the at least one application from a checkpoint stored in the resilient store, the resilient executor resuming execution of the at least one application with the restored application state information.

Abstract: An information processing system, computer readable storage medium, and method for supporting resilient execution of computer programs. A method provides a resilient store wherein information in the resilient store can be accessed in the event of a failure. The method periodically checkpoints application state in the resilient store. A resilient executor comprises software which executes applications by catching failures. The method uses the resilient executor to execute at least one application. In response to the resilient executor detecting a failure, restoring application state information to the at least one application from a checkpoint stored in the resilient store, the resilient executor resuming execution of the at least one application with the restored application state information.

Abstract: Managing a network connection of a switch. Software configuration information relating to the network connection of the switch is obtained, wherein the information specifies at least one VLAN connecting to the switch and a plurality of uplinks to be shared. According to the software configuration information, the plurality of uplinks is assigned to the at least one VLAN to form a corresponding connection relationship, in which relationship, each VLAN corresponds uniquely to one uplink from the plurality of uplinks. The hardware connection between the at least one VLAN and the plurality of uplinks on the hardware layer of the switch is set according to the corresponding connection relationship. Shared links may be formed in the switch, which links have multiple uplinks with redundancy, all in active status.

Abstract: In accordance with the present disclosure, a scalable and modular rack-level power infrastructure is described. The power infrastructure may include a power distribution unit (PDU), which receives alternating current (AC) power from an external power source. The PDU may be coupled to a busbar and output DC power to the busbar. The busbar may be coupled to a server within a rack-server system and provide DC power to the server. Additionally, the infrastructure may include a battery back-up unit (BBU) element coupled to the busbar. The BBU element may charge from and discharge to the busbar.

Abstract: A multi-channel control system includes a first primary control microprocessor and a second primary control microprocessor operable to control a device, and a first secondary control microprocessor and a second secondary control microprocessor operable to control the device. Each of the first and second primary control microprocessors and the first and second secondary control microprocessors are arranged as an independent control channel.

Abstract: Techniques for processing requests are described. A first thread is selected for execution. Only a single thread is allowed to execute at a time. Each thread is associated with a queue of requests to be processed by the thread. A first request is selected from the queue of first thread that performs first processing to service the first request. A service time classification for the first request is determined in accordance with criteria that includes a runtime determination of what resource(s) are used in servicing the first request. It is determined, in accordance with the service time classification, whether to allow the first thread to continue execution and process a second request from the queue of the first thread. If the first thread is allowed to continue execution, second processing is performed by the first thread to service the second request. Otherwise, a second thread is selected for execution.

Abstract: A method for prioritizing First Failure Data Capture (FFDC) data for analysis. The method comprising identifying FFDC data in response to receiving an error message, the FFDC data comprising at least one of: a computer system event which may lead to system failure; a computer system event led to system failure; a computer system condition which may lead to system failure; a computer system condition which led to system failure; determining a relevancy rank for each data value in the FFDC data based on the error message received and a probability a given data value is relevant in resolving a cause of the error message; and sending, in order of relevancy, the data values of the FFDC data to a second server.

Abstract: An arithmetic processing apparatus includes: first and second core groups each including cores, a first to an Nth (N is plural) caches that process access requests from the cores, and an intra-core-group bus through which the access requests from the cores are provided to the first to Nth caches; and a first to an Nth inter-core-group buses each provided between the first to Nth caches in the first and second core groups respectively. The first to Nth caches in the first core group individually store data from a first to an Nth memory spaces in a memory, respectively. The first to Nth caches in the second core group individually store data from an N+1th to a 2Nth memory spaces, respectively. The first to Nth caches in the first core group access the data in the N+1th to 2Nth memory spaces, respectively, via the first to Nth inter-core-group buses.

Abstract: An information handling system and method allows implementation of fault-tolerant storage subsystems using multiple storage controllers not themselves originally designed to support the redundancy of such fault-tolerant storage subsystems. In accordance with one embodiment, uncommitted data is efficiently and rapidly replicated across multiple commodity storage controllers, enabling faster and less expensive fault-tolerant storage subsystems. A redundant storage controller system can improve the efficiency of data replication while providing failure protection against controller failure. A redundant storage controller system using shared memory commonly accessible to the storage controllers can be enhanced to replicate data within host memory regions to protect against non-volatile memory failure. In accordance with at least one embodiment, an efficient data replication mechanism can be provided between storage controllers using off-the-shelf hardware.

Abstract: Example methods, apparatus and articles of manufacture to migrate virtual machines are disclosed. A disclosed example method includes identifying via a processor a first virtual machine to be migrated from a first host to a second host to improve a performance of the first virtual machine, determining that a frequency threshold associated with the first virtual machine will not be exceeded if the first virtual machine is migrated, determining a reliability rating for the first virtual machine, and migrating the first virtual machine to the second host based on the frequency threshold and the reliability rating.

Abstract: A method for handling failure in a networked virtualization environment having distributed virtual machine management.

Abstract: Techniques for placing a first fiber channel (FC) switch into maintenance mode in a virtualized computing environment in which each data store is connected to at least one host computing system via at least two FC switches are described. In one embodiment, a first active input/output (I/O) path from a data store to a host computing system via the first FC switch is identified. Further, a path change is initiated from the data store to the host computing system via any other FC switch coupled to the data store and the host computing system.

Abstract: In one embodiment, a computer-implemented method includes the step of communicatively coupling with an application-server local area network (LAN). The physical servers are discovered in the application-server LAN. The applications running in one or more physical servers in the application-server LAN are discovered. The application data and the application metadata are captured. The application data and the application metadata are parsed. The unique data blocks of the application data and the application metadata are identified. The unique data blocks are uploaded to a cloud-computing platform. It is determined that the one or more physical servers running the application data and the application metadata is no longer available in the application-server LAN. A cloud-based appliance in the cloud-computing platform is placed in an operational state. An application associated with the application data and the application metadata is identified.

Abstract: A method of controlling an apparatus including a processor including a plurality of cores, the method includes, when a number of the cores to be activated is M, determining whether or not a first power consumed by the M activated core is within a range of a second power to be consumed when the number of the cores to be activated is M+N, and when the first power is out of the range of the second power, prohibiting to increase the number of the cores to be activated from M to M+N.

Abstract: Methods of analyzing malware and other suspicious files are presented, where some embodiments include analyzing the behavior of a first malware sample on both a virtual machine and a physical computing device, the physical device having been booted from a secondary boot source, and determining whether the behavior of the malware sample was different on the virtual machine and the physical computing device. In certain embodiments, a notification indicating that the behavior was different may be generated. In other embodiments, a malware analysis computing device that is configured to receive a base hard drive image may be network booted, and the behavior of the malware sample on the malware analysis computing device may be analyzed. In certain embodiments, a malware-infected hard drive image may then be copied off the malware analysis computing device.

Abstract: A method is disclosed for performing LDPC decoding, specifically layered min-sum decoding using a Tanner graph including check nodes (CN) and variable nodes (VN). Messages passed between nodes are quantized in a non-uniform manner. Values below a threshold are uniformly quantized whereas values above the threshold are non-uniformly quantized. A corresponding inverse-quantization is also defined.

Abstract: Each CM includes an interface unit, a first detection unit, and a reset control unit. The interface unit is configured to be connected to a communication channel and control communication using the communication channel. The first detection unit is configured to detect an abnormality in an inter-CM path including the interface unit of the CM, to which the first detection unit belongs, the interface unit of the other CM, and the communication channel. The reset control unit is configured to retract the other CM and reset the interface unit of the one CM in a case where an abnormality of the other CM side is detected by the first detection unit. Accordingly, even in a case where a suspicious control unit in which an abnormality has occurred is erroneously specified, the maintenance of the suspicious control unit can be performed with the operation being continued.

Abstract: A method and system permit a backup entity of a redundant apparatus of a communication system that shares control of hardware resources or other network resources with an active entity to indirectly determine a status of the active entity based upon behavior and reaction to actions it takes in connection with resources it shares control of with the active entity. Such a method and system permit the backup entity to deduce the state of the active entity without having any a hardware connection or other communication connection with the active entity.

Abstract: An access point IHS group controller failure notification system includes access point IHSs connected to a network and members of an access point IHS group. A first access point IHS group controller for the access point IHS group is also coupled to the network. The first access point IHS group controller detects a failure issue associated with its imminent failure and, in response, creates an imminent failure message that includes an identifier for the first access point IHS group controller. The imminent failure message may also include timing information that indicates when the first access point IHS group controller will again be available, and/or a second identifier for a second access point IHS group controller that is available for controlling the access point IHS group. The first access point IHS group controller then sends the imminent failure message through the network to each of the plurality of access point IHSs.

Abstract: Embodiments of a system and method for triggering an event in a hardware abstraction layer (HAL) are generally described herein. In some embodiments, the HAL can include unarchitected hardware or software that can be used to, for example, facilitate instruction emulation and debug; enable protection of model specific resources, instructions, and behaviors; redirect, resteer, or substitute instructions; and provide a framework for additional capabilities and features.

Abstract: An error correcting system applied to a server, the server comprising a central processing unit, the central processing unit configured to send a warning signal when the central processing unit generates error. The error correcting system includes a programmable logic device, a baseboard management controller coupled to the programmable logic device, and a basic input output system coupled to the baseboard management controller. The programmable logic device is configured to detect the warning signal and send an interrupt signal to the baseboard management controller after the warning signal is detected. The baseboard management controller is configured to send a notification signal to the basic input output system after receiving the interrupt signal. The basic input output system is configured to retrieve the error and correct the error after receiving the notification signal.

Abstract: Method and apparatus for dynamic Node healing in a Multi-Node environment. A multi-node platform controller hub (MN-PCH) is configured to support multiple nodes through use of dedicated interfaces and components and shared capabilities. Interfaces and components may be configured to be used by respective nodes, or may be configured to support enhanced resiliency as redundant primary and spare interfaces and components. In response to detecting a failing or failing primary interface or component, the MN-PCH automatically performs failover operations to replace the primary with the spare. Moreover, the failover operation is transparent to the operating systems running on the platform's nodes.

Abstract: A method for detecting errors in hardware including running a transaction on a plurality of cores, wherein each of the cores runs a respective copy of the transaction, synchronizing the transaction on the cores, comparing results of the transaction on the cores, and determining an error in one or more of the cores.

Abstract: A coupling device for connection of one of two servers at a time to a data transmission network as well as to a data transmission network having a coupling device. The device has a first and second terminal for connecting a first and second server and a third terminal for connection to the data transmission network. A switch device is provided having a first switching state where the third terminal is connected to the first terminal and disconnected from the second terminal, and a second switching state, where the third terminal is connected to the second terminal and disconnected from the first terminal. The switch device is adapted to assume a switching state, when it is provided with the energy signal by the power supply, and to assume another switching state, when it is not provided with the energy signal by the power supply.

Abstract: A recovery circuit for a basic input-output system (BIOS) of a computer includes a storage, a platform controller hub (PCH), and a processor. An effective chip select signal is received by a chip selection pin of the storage via a second pin of the processor when a first pin of the processor does not receive any signals, data in the processor is transmitted to the PCH to make the computer boot up, the data in the processor is transmitted to the storage to erase and update data in the storage.

Abstract: A method for enhanced restart of a core dumping application is provided. The method includes stopping a plurality of threads in an address space, except for the thread performing the core dump. Computational segments are remapped to client segments. Each open file descriptor in the address space is closed. The application is terminated and the client segments are flushed to external storage.

Abstract: To facilitate log streaming in a computing cloud, application service providers may dynamically provision one or more named log streams. A file-oriented interface to log streams may be made available to a plurality of virtual computer system instances used to provide the application services. Application service providers may further dynamically provision one or more sets of log stream processing agents arranged in one or more log stream processing graphs. Particular log streams may be assigned to particular log stream processing graphs for real-time processing. Processed log streams and/or associated data may be stored for later inspection. Such provisioning and/or configuration may be performed with a unified Web-based interface.

Abstract: A method and a relevant apparatus for starting a boot program are provided. The method includes: when a boot request is detected, determining whether a first physical block in a NAND flash is a bad block; reading first boot data stored in the first physical block if the first physical block is not a bad block; determining whether the read first boot data has a data error; re-reading the first boot data from a first backup block when the read first boot data has a data error; determining whether the first boot data that is re-read from the first backup block has a data error; when the first boot data that is re-read from the first backup block has no data error, continuing to process other boot data that needs to be read to start the boot program, until start of the boot program is complete.

Abstract: Methods and systems for performing a shared computing task are provided. The method includes configuring a shared computing task among a plurality of computing nodes each executing an application for performing the shared computing task; generating intermediate data by each of the plurality of computing nodes during a mapping process for performing the shared computing task; capturing the intermediate data for each of the plurality of computing nodes; storing the intermediate data for each of the plurality of computing nodes at a key-value data store at a shared storage device that enables searching for the intermediate data using a key-value pair; and using the key-value pair to obtain the intermediate data when needed for a reduce process of the shared computing task.

Abstract: A method and system protects switching in a network element. At least one data signal at the client entity is received, wherein the signal flow through server entity via the client entity. A configuring protection group on at least one client entity is served by at least two server entity, wherein the protection group includes at least one work entity and at least one protect entity. A plurality of supplement client entities of client entity is created such that at least one of the supplement client entity flows over one server entity and checking the entities for a fault to raise alarm to their respective controllers. The controller includes at least one server layer protection controller and at least one client layer protection controller.

Abstract: In an automation system, a control device processes measured values received from automation components and generates control values for the, or for individual, automation components and/or other automation components. In order to shorten down times when replacing an existing control device, the new control device is tested during operation of the existing control device, for which purpose the measured values and control values are wirelessly transmitted to the new control device and the control values generated by the device are compared to the control values generated by the existing control device. After the test, the control values generated by the new control device are output to the automation components instead of the control values generated by the existing control device.

Abstract: There is provided an inter-bus communication interface device capable of efficiently performing transfer of data between a plurality of devices connected to different buses, respectively. When communication data is transmitted, a first device writes the communication data into a buffer, whereas when communication control information is transmitted, the first device writes the communication control information into a register. A control circuit passes the communication data stored in the buffer to a second device, and passes the communication control information stored in the register to a second device.

Abstract: It is disclosed a method for protecting a computer network against a failure. The method comprises: identifying a number of possible failures which might occur within the computer network, the number of possible failures comprising at least one possible failure; and, based on detected availability of resources in the computer network, determining a protection state of the computer network allowing to circumvent the possible failure and dynamically updating the determined protection state based on changes of the detected availability. The method further comprises, upon occurrence of the failure, if the occurred failure corresponds to the possible failure, bringing the computer network into an operative protection state corresponding to the determined and dynamically updated protection state.

Abstract: First data to be written which is output from a function module (2) is supplied to a built-in memory (3) and a first buffer memory (11), and second data to be written which is output from the function module (2) is supplied to the built-in memory (3) and a second buffer memory (12). The first and second FIFO memories (13, 14) select and store data items having a predetermined number of outputs from a plurality of first and second output data items which are sequentially output from the first and second buffer memories (11, 12), and do not select other data items. A comparator (15) compares the data items having the predetermined number of outputs which are selected and are output by the first and second FIFO memories (13, 14) with each other.

Abstract: We describe a fault-tolerant power semiconductor switching device control system (100), the control system comprising: a coordinating control system (110); and a plurality of switching device controllers (120) each coupled to said coordinating control system and each configured to control a respective power semiconductor switching device (130); wherein said coordinating control system is configured to send real time switching control data to said switching device controllers to control switching of said power semiconductor switching devices, and to receive real time acknowledgement data from said switching device controllers; wherein a said switching device controller is configured to receive said real time switching control data from said coordinating control system, to control a said power semiconductor switching device responsive to said real time switching control data, and to provide said real time acknowledgement data confirming said switching device control to said coordinating control system; and wher

Abstract: Systems and methods are provided that enable seamless access and control of hardware device resources through a common, device-independent interface without the need for device-specific drivers. For instance, system and methods are designed to expose capabilities/functions of hardware devices as web-based services which can be invoked to provide specific services based on the capabilities of the hardware devices.

Abstract: A method for managing fault messages (m) of a motor vehicle by a monitoring computer of a motor vehicle, the monitoring computer including a step (E1) of receiving a fault message (m), a filtering step (E3) in which the method executes a step (E4) of storing the fault message (m) in a temporary storage memory (TMP) in case of positive filtering and a step (E5) of storing the fault messages (m) in a dynamic storage memory (DYN).

Abstract: Systems and methods for reducing problems and disadvantages associated with traditional approaches to providing redundancy for a management controller are provided. A method may include executing, by a hypervisor executing on a management controller, a first guest OS and second guest OS. The method may additionally include executing, by the first guest OS, one or more first management applications for managing one or more information handling resources communicatively coupled to the management controller. The second guest OS may: (i) execute one or more second management applications for managing the one or more information handling resources communicatively coupled to the management controller; (ii) execute one or more monitoring applications for monitoring redundancy status of the first guest OS and the second guest OS; (iii) sleeping the one or more second management applications; and (iv) monitoring, by the one or more monitoring applications, the operability of the first guest OS.

Abstract: A system includes a first application that writes a first plurality of tasks to a first memory buffer; a second memory buffer that receives a copy of the first plurality of tasks; a second application that writes a second plurality of tasks to a third memory buffer; and a fourth memory buffer that receives a copy of the second plurality of tasks. The system further includes a first comparison module that generates a first voting signal based on a first comparison between a first task and a second task. The system further includes a second comparison module that generates a second voting signal based on a second comparison between the first task and the second task. The system further includes a first central processing unit (CPU) that selectively determines whether to de-assert a module health signal based on the first voting signal and the second voting signal.