Abstract: A rapid self-error-check circuit of a computer power supply is disclosed, wherein a computer power supply is installed with a self-detecting device; an LED displaying light and detecting button are exposed on the casing of the power supply; thereby, the normality of the power supply can be detected by pressing a detecting button and then the result is displayed through the colors of the LED displaying light.

Abstract: The system for simplified operating system shutdown enables the execution of the required operating system shutdown sequence without requiring the use of a monitor, keyboard, and mouse. This is accomplished by equipping the printed circuit board with a simple switch and an indicator device to provide the user interface to execute the operating system shutdown process. The user operates the switch, which activates the system for simplified operating system shutdown to initiate the required operating system shutdown process. The system for simplified operating system shutdown activates the indicator device in a first mode to notify the user that the shutdown process is now executing. The system for simplified operating system shutdown generates a message, which message is transmitted to the processor. This message comprises a system call for a shutdown and restart.

Abstract: In a power supply apparatus, a microprocessor automatically performs a stop/restart of power supply to a computer on the basis of a command/parameters input by the computer. A schedule operation monitor circuit monitors whether the schedule operation is normally performed. A microprocessor control unit forcibly executes the schedule operation to perform automatic restoration on the basis of a monitor result of the schedule operation monitor circuit when abnormality occurs in the schedule operation.

Abstract: A method of managing power in an electronic device having at least one connectable component includes determining a total power requirement for the at least one connectable component. The available power level for a power supply connected to the electronic device is determined. The total power requirement is compared with the available power level. The at least one connectable component may draw power from the power supply if the total power requirement is not greater than the available power level.

Abstract: A method and apparatus for detecting a change in the operational status of a first host computer and automatically configuring a second host computer to provide additional computing resources that replace or complement the first host computer. In one embodiment, a controller is provided that is capable of detecting a malfunction or failure of the first computer and automatically configuring a second host computer to replace the first host computer. In another embodiment, the controller is capable of detecting changes in the performance of the first host computer and automatically configuring a second host computer to provide additional computing resources for the first host computer. In a further embodiment, both of these techniques can be used to support an electronic commerce site and provide the electronic commerce site with failsafe operation and virtually unlimited computational resources.

Abstract: A network switch and method of switching are provided, in which first and second signal converters convert electrical signals to optical signals and vice versa. The network switch monitors alarm contacts and power drawn by the first and second signal converters, and switches from one to the other in the case of an alarm condition or power loss. In order to force a corresponding switch at the remote end, power is removed from one of the signal converters in order to force an alarm in the corresponding signal converter at the remote end.

Abstract: A method for restoring integrated circuit devices in an encapsulated array of integrated circuit devices includes the steps of testing the array and applying a voltage signal to pins appearing to be disconnected from an element internal to the array.

Abstract: Methods and apparatus are provided for reserving power in a handheld computer by inducing a sleep mode when the energy supply of the handheld computer reaches a predetermined low level. A software is provided which operates a sleep mode when a device of the handheld computer detects a predetermined low battery voltage. A processor operates the software to place the handheld computer in a low energy-consuming shutdown state in which an interrupt controller operates to mask those interrupt signals thus providing an user with the impression that the device has entered an unresponsive sleep mode. In maintaining the sleep mode, the processor operates such that all input signals that request the handheld computer to power up remain active but so long as the battery voltage remains below a predetermined voltage the interrupt signals to power up selected applications and devices are masked.

Abstract: A basic input output system (BIOS) or equivalently functional circuitry can determine when an invalid shutdown event occurred (e.g., power loss) and subsequently, whether a false remote system wake event is received by the computer system and allow processing to bypass wakeup processing to avoid false wakeup commands received from components of the computer system such as LAN cards and modems. A computer system employing false wakeup command functionality is further claimed along with medium storing means for preventing wakeup processing when a false wakeup command is received.

Abstract: A communication system (100) includes a network, a first application running on a first Host computer system (First Host) (102) coupled to the network, and a second application running on a second Host computer system (Second Host) (122) coupled to the network. The first application issues an Extended PING command (300) for sending an Extended ECHO message (380) from the First Host (102) into the network and directed to the second application in the Second Host (122). The second application in the Second Host (122), in response to receiving the Extended ECHO message (380), issues an Extended PING command (300) for sending an Extended ECHO reply message (380) into the network and directed to the first application to measure the full loop-back network latency of communicating a message application-to-application across the network.

Abstract: An IDE interface adapter is constructed to include a box, and a circuit board mounted in the box, the circuit board including a first connector having 36 pins for receiving the 36-pin connector of an IDE interface device, a second connector having 50 pins for receiving the 50-pin connector of a mobile rack, a first power adapter, and a selector switch connected in series to the first power adapter, wherein the selector switch is shifted to alternatively connect the second connector to the first connector or the first power adapter, enabling the second connector to receive a working voltage from the first connector or the first power adapter.

Abstract: An integrated circuit includes secure logic that requires protection. Secure assurance logic protects the secure logic. The secure assurance logic includes a plurality of protection modules that monitor the occurrence of insecure conditions. Each protection module monitors a different type of insecure condition. Each protection module asserts an alarm signal when an associated insecure condition is detected. The alarm signals asserted by the plurality of protection modules are stored.

Abstract: A disk array controller reliably improves performance in RAID configurations without the need for a battery backup. Write completion interrupts are queued until a write cache flush has been performed and are then sent to a host system. States of ranges of disk addresses (activity bins) are stored in nonvolatile storage elements associated with the ranges. The states allow rebuild times to be reduced after power failures and drive failures. A range is in a Changing state if at least one of the addresses is the target of a write operation that has been initiated but not completed. The range is in a Stable state if no addresses are the target of an uncompleted write operation. Two additional states are used to identify ranges of disk addresses that have been zeroed or never been written to. The additional states allow substantial reductions in RAID volume creation times.

Abstract: A system and method for monitoring a distributed fault tolerant computer system. A hardware counter mechanism (e.g. a countdown counter) is reset repeatedly by a software reset mechanism during normal operation, thereby preventing the counter mechanism from reaching a count indicative of the existence of a fault. A unit provides a signal to a bus indicative of the status (ON or OFF) of the unit. A management subsystem defines a configuration for the distributed fault tolerant computer system. The management subsystem is responsive to status signals on the bus and selectively reconfigures a stored representation in response to changing status signals on the bus.

Abstract: A method and system for protecting user data during power failures on a network-computer-class data processing system is provided. The network-computer-class data processing system is integrated with a power supply having an early power fail warning signal to ensure that unsaved changes to user data files are saved before a complete power failure strikes the data processing system. As a user employs one or more applications to create or modify data files, a table of file changes is created for each user data file that is opened by the user. This table is kept in non-volatile media, preferably on the user's network computer but possibly on a server located on a network connected to the network computer if the network computer lacks non-volatile memory. The entire contents of the table are saved to non-volatile storage in the time interval between the early power fail warning signal going active and the power completely failing.

Abstract: A system and method for utilizing a topology detector to capture visual information comprises a topology detector that propagates a detection pulse towards a target object using a transmitter module, and then senses wave segments of the detection pulse with a sensor array as the wave segments are reflected back toward the topology detector. The topology detector may then generate contour values that correspond to localized areas of the target object. A detection manager may then access the contour values to responsively generate and store topology values that may be mapped to respective pixel values of a set of captured image data that represents the target object.

Abstract: A sub-net operation with increased availability and reduced power consumption is achieved in a bus system with a plurality of stations (10, 11, 12) which are coupled to one another via a system of conductors (13, 14). Each of the stations includes a transceiver (21) and a control unit (30). The stations are switched from a quiescent state to a standby state in response to the reception of a first wake-up signal and selected stations are switched to a normal operating state upon reception of a second wake-up signal, whereby stations are selected.

Abstract: A multiprocessor computer includes a processor disabling scheme which disables a processor that has been designated to boot the computer but fails to boot the computer. For computers having voltage regulator modules (VRMs) to power each processor, a control device directs a VRM associated with the failed boot processor to cease supplying power in response to the processor's failure. For computers without VRMs, a transistor controls the delivery of power from the power supply to each respective processor. If a designated boot processor fails to boot the system, the control device turns off the appropriate transistor to disable the failed processor.

Abstract: An electronic control unit includes a first microprocessor monitoring the operation of a second microprocessor and has a monitoring operation blocking unit for preventing the second microprocessor from being reset by the first microprocessor while the second microprocessor is loading from a memory thereof so that even when a control program is loaded into the monitoring microprocessor before one is loaded into the monitored microprocessor, the control program can be loaded with certainty. Each microprocessor executes a control program stored in the memory, and when a predetermined reloading condition has been established, executes a loading process for receiving load data transmitted thereto from outside into the memory.

Abstract: Circuitry for protecting a first electrical system when connected to a second electrical system via a bus which provides a current-carrying signal to the first electrical system and includes a reset signal which is monitored by the second electrical system. The circuitry includes a capacitor connected to the current-carrying signal of the bus. A first switch is electrically connected between a node of the capacitor and a ground point. The first switch is closed when the first electrical system is powered-up and open when the first electrical system is powered down. A second switch is electrically connected between the reset signal of the bus and the ground point. The second switch closes due to the energy accumulated by the capacitor when the first switch is open.

Abstract: A structure including volatile memory devices that are used by the host computer system as the storage media. The volatile memory devices include volatile memory device back up systems to provide power to both the volatile memory and non-volatile memory in the event of power failure. The volatile memory devices also connect directly to an expansion bus of the host computer system, such as a PCI bus. Therefore, the volatile memory devices of the invention include a high-speed path to the host computer system and the volatile memory devices of the invention are faster than prior art devices, use less power and are lower cost.

Abstract: A power management method for a computer system is provided, which is not affected by a problem with the power and needs a shorter time for the computer system to resume from the suspended state. In the method, when the computer system resumes from the suspended state, if a power controller for controlling the power has not been initialized, it is determined that no interruption of the AC power occurred, and the computer system resumes the previous state based on the data stored in the main memory, while if the power controller has been initialized, it is determined that an interruption of the AC power occurred, and the data stored on the hard disk is read out and the computer system resumes the previous state based on the readout data.

Abstract: In one embodiment of a method for recovering from a computer system lockup condition, an interrupt is generated to the computer system's operating system notifying the operating system of the lockup condition. An operating system interrupt handler is then executed. The interrupt handler performs at least one step to attempt to cure the lockup condition. If the interrupt handler fails to cure the lockup condition, the interrupt is regenerated to the operating system notifying the operating system of the lockup condition. The interrupt handler is then re-executed in response to the regeneration of the interrupt, with the interrupt handler performing a further step in attempting to cure the lockup condition.

Abstract: Methods and apparatus are described for providing a time-based warning indicating that the energy capacity of a primary energy source of a battery-powered computer has discharged to a low level, and using residual energy of the primary energy source to perform at least one pre-cutoff function. The time-based warning ensures that the warning is provided in a timely manner by overcoming problems caused by analog to digital converter voltage measurement accuracy limitations and flat battery operating voltage versus discharge curves. The primary energy source can be a rechargeable battery, which can also be the sole energy source for the computer. The battery provides power to operate the computer until the battery voltage discharges to the cutoff voltage. The methods and apparatus provide advantages because they reserve the residual energy in the battery to perform at least one pre-cutoff function within a first duration before the battery discharges to the cutoff voltage.

Abstract: A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The DRDRAM Specification suggests that the DRDRAM be put in the STBY state with no banks active. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.

Abstract: A backup control system comprises a control package, a file package including a battery monitor and a flip-flop circuit, and a back board having a return wire which provides connection/disconnection of the monitor terminal of the monitor. The monitor checks a voltage of the monitor terminal at all times and outputs a reset signal to the flip-flop circuit when the voltage of the monitor terminal becomes lower than a reference voltage. The return wire connects the monitor terminal to the power line when the file package is connected to the connection board, and disconnects the monitor terminal from the power line when the file package is removed from the connection board. The flip-flop circuit stores one of a set state and a reset state, and changes in state from the set state to the reset state when the reset signal is received from the monitor.

Abstract: A method and system for performing a task in an intrinsically safe environment using an intrinsically safe, integrated module located on the safe side to convey signals to and from a field device on the hazardous side. The integrated module is configurable in order to suit the electrical characteristics and requirements of the field device. Preferably, the integrated module is software configurable, in that the module can be configured by a command signal without using switches. Furthermore, the integrated module is configurable in order to control the field device in performing the task. The integrated module includes an input/output module which is electrically connected to the field device through a Zener barrier or a galvanic isolation barrier, and a power supply to power the field device through a Zener barrier.

Abstract: The present invention relates to a method and apparatus for ensuring fault detection and system recovery in a multiprocessor computing system. This system comprises a multitude of processing element modules, input/output processor modules and shared memory modules. Each module within the system includes an identical period sanity timer capable to reset the module once a predetermined limit count is reached. If a global clear signal is not received from the operating system scheduler by all modules prior to the expiry of the sanity timers, a system-wide reset is effected. Each processing element module within the system further includes a watchdog timer capable to reset the module once a predetermined limit count is reached. If a process is not run by the operating system scheduler on the processing element before the expiry of the watchdog timer, effectively clearing the watchdog timer, the processing element is reset and removed from service.

Abstract: In an information storage apparatus including an uninterruptible power supply (UPS), a sequence of operation from when a power failure occurs to when power of the UPS is turned off is automatically accomplished completely without human power to thereby guarantee user data. For this purpose, the apparatus includes a disk array, a host, and a plurality of UPSs to supply power to the disk array and the host. The UPSs monitor a state change of power on a host side by a host ac control line or an SCSI unit to sequentially execute processing in an order of processing of host termination, processing for cache flush of the disk array, processing of host UPS termination, processing of disk array termination, and processing for termination of disk array UPS. Between the UPSs and the Host and between the UPSs and the disk array, there is provided an interlocking control signal to monitor current states thereof so as to control the respective operations.

Abstract: A data processing system is provided with an electronic key for remote designation of the computer system into a service, secure, or normal/run mode of operation. Such a remote designation is enabled when a physical or manual key is set to a normal/run mode of operation. Setting of the electronic key to a service mode permits remote access to the system for maintenance or debug operations.

Abstract: Methods and associated apparatus for generating and maintaining a unique identity for an enclosure in a storage system. Where an enclosure compliant with storage industry standards is to maintain a unique identity, methods of the present invention are operable to coordinate use of redundant devices within the enclosure that serve, among other functions, to store and report the unique identity of the enclosure. The redundant devices (i.e., environmental service cards or modules) assure that the enclosure identity remains unique among such enclosures despite hot or cold swaps of the redundant devices among the several enclosures. A change number portion of the unique identity value stored in each of the redundant devices is updated (i.e., incremented) each time a change in the configuration of redundant devices is detected by the devices. An incumbent one of the redundant devices reports the unique identity for the enclosure in response to attached system requests.

Abstract: An initializer that responds to change in a power supply potential level, for generating an initialize signal to initialize a circuit to a select state, the initializer includes a power-on reset circuit that switches between an active and a powered-down state, and is for generating the initialize signal. The initializer also includes a wake-up circuit that monitors the power supply potential level and switches the power-on reset circuit from the powered-down state to the active state when selected change in the power supply potential level occurs.

Abstract: In an electronic control apparatus having a one-chip microcomputer and a power output circuit, a voltage abnormality detecting circuit is provided to detect whether an output voltage of each power output circuit is set to a voltage in a predetermined range. A current abnormality detecting circuit is also provided to detect that a current flowing into each power output circuit is in an excessive current condition or in a low current condition. The microcomputer is reset when the detected output voltage or the detected current is abnormal.

Abstract: A programmable logic device having redundant sets of logic blocks which are capable of being enabled or disabled. The programmable logic device includes a plurality of sets of logic blocks, a plurality of routing resources and a programming circuit. Good logic blocks are enabled and fully operational when programmed. Nonfunctional logic blocks are disabled, powered off and invisible to the programming software. Each set of logic blocks has a corresponding routing resource. The routing resource corresponding to an enabled set of logic blocks is capable of being configured to provide input and output data paths for the enabled set of logic blocks. The routing resource corresponding to a disabled set of logic blocks is capable of being configured to bypass the disabled set of the logic blocks. The programming circuit stores the configuration data for the routing resources and is capable of providing the configuration data to a routing resource that corresponds to an enabled set of logic blocks.

Abstract: A system for effecting a shutdown of a networked information handling system automatically determines the time interval required for the information handling system to reach a safe shutdown by continually calculating the time interval necessary to store all volatile information to non-volatile locations and shut down the system. In order to calculate the time interval, heuristics may be determined for various operating systems, applications, application environments, etc. Integration of the system of the present invention may be determined by a particular condition, configuration, and/or environment at any given period of time, and may, for example, be incorporated in environments such as a UPS (Uninterruptable Power Supply) environment or a fault tolerant CPU (Central Processor Unit) shutdown environment.

Abstract: An integrated reliability enhancement device for providing high reliability operation of a personal computer is preferably embodied in an add-in card for insertion into a bus slot of the personal computer. The add-in card includes monitoring circuitry for detecting an array of events associated with operational failure of the computer including failure of a cooling fan, out-of-range temperature fluctuations within the computer housing, out-of-range deviations in power supply input voltage, out-of-range deviations in power supply output voltage, and out-of-range deviations in line current consumption by the computer. Upon detection of one of the events, data associated with the failure is written into an add-in card memory which is accessed periodically by application software of the host computer.

Abstract: A disc storage system having a host computer interface adapted to coupled to a host computer, a disc storage medium having a disc surface and a spindle motor coupled to the disc adapted to rotate the disc. A transducer is positioned for reading and writing data on the disc surface. The system further includes a volatile memory write cache and a non-volatile memory write cache adapted to store data during a power loss. A method is also provided for storing data prior to writing the data in a non-volatile memory cache in a disc storage system.

Abstract: A computer system includes a monitor having a universal serial bus (USB) interface for connecting with a base system. Multiple button and LED controls are conveniently placed on a front bezel of the monitor. As the buttons are actuated, commands are passed to the base system via the USB. An on-screen display button causes an application to be launched on the base system for modifying screen attributes stored in a monitor controller in the monitor. A USB controller in the monitor updates the monitor controller via the USB. A multifunction audio dial is toggled by a bezel button between volume, bass and treble functions. The USB controller is also operable to provide a sustain a blinking LED even while the base system is in a sleep mode. LEDs on the front bezel indicate monitor and base system power status.

Abstract: An apparatus for sampling a power supply current value for performing frequency analysis of the power supply current flowing in an integrated circuit with a test signal applied to the integrated circuit has a power supply generating a prescribed supply of power for the integrated circuit (DUT: device under test), a current detection means for observing the power supply current value supplied from the power supply to the DUT, a test signal generation means for generating a prescribed test signal to be applied to an input/output terminal other than a power supply terminal of the DUT and for generating a test signal application signal during application of the test signal to the DUT, a sampling means for sampling the power supply current value signal, a sampling time determining means for instructing the sampling means with regard to the start and end timing for sampling, based on the test signal application signal, a sampling data storage means for storing data sampled by the sampling means, a Fourier transform

Abstract: A computer monitoring device is provided which ensures safe operation, even when a power supply voltage supplied to a microcomputer decreases and causes the microcomputer to enter an abnormal state. When the power supply voltage decreases, the power supply circuit is switched to an auxiliary power supply which supplies power to a microcomputer monitoring circuit and signal processing circuit via a diode. The microcomputer monitoring circuit in turn provides a reset signal for the computer so that it can continue to operate, which ensures safe operation of the computer. The computer monitoring device is particularly useful in a power window system for a vehicle.

Abstract: A method and circuit is provided for safeguarding the data stored in a CMOS RAM (Complementary Metal-Oxide Semiconductor Random Access Memory) unit in a computer system, such as an IBM-compatible personal computer (PC), when the battery unit used to power the CMOS RAM unit is below working level. By this method and circuit, when the PC is powered off, the current power level of the battery unit is detected to see whether it is below working level; if yes, the main power of the PC is turned on; then the data currently stored in the CMOS RAM unit are moved to a backup-data storage unit such as the hard disk; and after this, the main power is turned off again. At the next time the PC is powered on, the data currently stored in the backup-data storage unit are moved back to the CMOS RAM unit; and after this, a message is displaying on the monitor screen requesting the user to replace the CMOS RAM battery with a new one.

Abstract: A system and method for preventing damage to media files within a digital camera comprise a power manager for detecting power failures, an interrupt handler for responsively incrementing a counter device and a removable memory driver for performing memory access operations, evaluating the counter device to determine whether a power failure has occurred during the memory access operation and for repeating the memory access operation whenever a power failure has occurred during the memory access operation.

Abstract: A method and apparatus for maintaining a determinate operational state for a controller is provided that involves supplying an input voltage to the controller via a main power supply and periodically supplying a voltage step pulse to the controller in addition to the input voltage being supplied to the controller by the main power supply so that the voltage step pulse does not affect the controller's operational state when that state is determinate and so that the voltage step pulse will cause the controller to enter a reset mode when its state is indeterminate because of a low input voltage level being supplied via the main power supply. The voltage step pulse is continuously and periodically supplied to the controller via a low voltage reset circuit regardless of the voltage level being supplied to the controller via the main power supply.

Abstract: A method of managing data in a flash EEPROM memory array allows all data to be recovered after power loss except new data in a sector in which the data content is being changed when power is lost. The method includes providing a block data structure and a plurality of sector data structures in each block of a flash EEPROM memory array, each data structure storing an indication of the operating state of the block or an associated physical sector of the array; changing the indication stored in the block data structure or the sector data structure when the operating state of the block or the associated sector changes; detecting the indication stored in the block data structure and the sector data structures when power is restored to a system which has lost power; and managing the flash EEPROM memory array depending on the indications detected.

Abstract: An FeRAM array replaces ROM, PROM, EPROM, and/or EEPROM in a programmable controlling device and thus provides non-volatile memory cells for code stores, data stores, registers (including peripheral registers), state machines and microcode (if included) in the device. The programmable controlling device contains a processor and non-volatile ferroelectric memory cells as well as a ferroelectric memory array. The array has a code store that holds a program to control the processor, a data store that stores temporary data from the processor, and one or more registers that hold data being manipulated by the processor. The code store, data store and registers are memory mapped onto the non-volatile ferroelectric memory array. The state machines and peripheral registers are made of ferroelectric memory cells. The programmable controlling device may also include microcode that cooperates with the processor to change the function of the processor.

Abstract: A component powered by a first power supply activates a driving signal. The driving signal indicates that both a second power supply voltage has a magnitude greater than a reference voltage and an enable signal is active. A driver transfers the output signal when the driving signal is active. In a multi-processor computer system implementation, each of two processor cores are independently supplied power by each of two core power supplies while a single I/O power supply supplies power to the I/O rings of both processors. Each processor includes a bus isolation circuit to prevent its respective processor from loading the system bus in the event that a core power supply fails.

Abstract: An initializer that responds to change in a power supply potential level, for generating an initialize signal to initialize a circuit to a select state, the initializer includes a power-on reset circuit that switches between an active and a powered-down state, and is for generating the initialize signal. The initializer also includes a wake-up circuit that monitors the power supply potential level and switches the power-on reset circuit from the powered-down state to the active state when selected change in the power supply potential level occurs.

Abstract: A storage device that can reduce the backup operation time by shortening the backup path. The storage device having a memory unit and a memory control unit that controls access to the memory unit includes a backup storage medium; and a backup control unit for implementing an access control under which data in the memory unit is read out via the memory control unit when data in the memory unit is backed up and the readout data is written as backup data into the backup storage medium. The storage device is suitable for use in information processing systems such as parallel computing systems.

Abstract: A technique allowing a terminal device located in a remote place to protect data existing on an information processing system and then control an electric source of the information processing system is provided. An information processing system according to the present invention includes a service processor for discriminating an order issued by a terminal device located in a remote place, an electric source control circuit for controlling connection or disconnection of an electric source in response to an electric source connection or disconnection order issued by the service processor, and an electric source unit for conducting connection or disconnection of an electric source in response to an electric source connection or disconnection order issued by the electric source control circuit.

Abstract: Accompanied by turning on power, power ON reset pulse from a power ON reset generation circuit is input to CPU and a fail determining circuit. After receiving the power ON reset pulse, the fail determining circuit intentionally outputs a fail detection signal. The CPU intentionally stops output of PRUN signal after confirming that fail detection signal. WDT confirms that output of the PRUN signal from the CPU is stopped in a predetermined time interval T and outputs PRUN abnormality signal. A reset pulse generation circuit confirms that PRUN abnormality signal is supplied from the WDT and outputs a reset pulse. A fail determining circuit receives a reset pulse and stops output of fail detection signal. When the fail determining circuit stops output of the fail detection signal, the CPU determines that the WDT, the reset pulse generation circuit and the fail determining circuit are in normal state.