Additional Processor For In-system Fault Locating (e.g., Distributed Diagnosis Program) Patents (Class 714/31)
  • Patent number: 10419564
    Abstract: A method, computer program product, and system includes a processor(s) in a first computing environment obtaining, from a computer system in the first environment, a system message indicating an issue in the computer system. The processor(s) evaluate the message to determine details of the issue and determine recommended action(s) to remedy the issue. The processor(s) generate a notification comprising the action(s), which include calls to portions of the computer system and the notification comprises respective selection options to trigger the processor(s) to execute each of the one or more recommended actions in the first environment. The processor(s) transmit the notification to a computing node in a second computing environment to communicate to a computing device in that environment. The processor(s) receive a response indicating selection of a respective selection option. The processor(s) translate the option into a recommended action and issue calls in the recommended action to the computer system.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: September 17, 2019
    Assignee: International Business Machines Corporation
    Inventors: Wilhelm Mild, Omar-Qais Noorshams, Pradeep Parameshwaran, Guenter Vater, Robert Vaupel, Mariia Zrianina
  • Patent number: 10409450
    Abstract: A system and method for creating a visual perspective of operational information that facilitates rapid decision making. The system and method merges existing data sources from any number of computer-fed external data sources through an applications server to display data set in easily recognizable, repeatable images (tiles) uniquely designed for a user's application. The system and method create visual perspectives of data that accelerate decision-making and problem solving processes by displaying repeatable images (tiles) that display performance results verses expected performance criteria in high-volume, intuitive displays. The system and method utilizes facet searching to assist in refining the displayed images (tiles) to display a system status to the user.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: September 10, 2019
    Inventors: Kerry Gilger, Dan Katrencik, Aashish Gandhi
  • Patent number: 10387814
    Abstract: An event wizard server includes at least one processor that executes the event wizard server application that bidirectionally communicates event planning data with a user of a client device via a network interface. The event planning data includes: event type menu data, and event type selection data, wherein at least one event type includes a sequential task-oriented event.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: August 20, 2019
    Assignee: Planet Social, LLC
    Inventors: Michelle Stockton, Judith Stuckman, Christine Laramy, Bruce Edward Stuckman
  • Patent number: 10379139
    Abstract: Systems and methods are disclosed for testing circuit modules. A system for testing a circuit module includes a test circuit board configured to interface with a host system, a standard connector implemented on the test circuit board and configured to be attachably coupled to the circuit module, a micro-backplane module configured to be attachably coupled to the circuit module and a micro-backplane module interface connector implemented on the test circuit board and configured to be attachably coupled to the micro-backplane module.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: August 13, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Sohail Mallick, Dmitry Vaysman, Hyun Soo Kim, Brian Hokyee Tse, Hariharan Venkataramani
  • Patent number: 10372570
    Abstract: Embodiments include a method of a test system that comprises a host device and at least one storage device having multiple ports connected to the host device through a multi-port connection, the method comprising: issuing, by a test program at the host device, a first command; generating, by a device driver at the host device, a plurality of second commands in response to the first command; and simultaneously transferring, by the host device, the second commands to each of the at least one storage device.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: August 6, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: KyuYeul Wang
  • Patent number: 10318367
    Abstract: A method for detecting computer issues includes identifying a target computer system. A first set of data for a first time period relating an operating metric from the target computer system are received. The operating metric is stored. A second set of data for a second time period relating to the operating metric is received. The first and second sets of data are compared. A difference between the two sets of data is identified. If the difference between the two sets of data is within a range a warning notification is displayed in a graphical user interface. An input is received in the graphical user interface in response to the warning notification being displayed.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: June 11, 2019
    Assignee: United Services Automobile Association (USAA)
    Inventors: Manuel A. Carranza, Chase T. Sekula, Mark S. Moore, Mathew P. Ringer
  • Patent number: 10310970
    Abstract: The present invention relates to a method of testing an application program mounted on a smart device 10 such as a smart phone, a tablet computer or the like, in which a test target application program is automatically tested by a control program installed in the smart device 10, and an effective permission is granted to the control program through a booster 20 combined with the smart device 10. Through the present invention, a test can be automatically conducted without handling a corresponding smart device 10, in which an application program test is conducted, by the user of the smart device 10, and a test on the application program under a variety of conditions can be conducted efficiently and systematically.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: June 4, 2019
    Assignee: RSUPPORT CO., LTD.
    Inventor: Hyungsu Seo
  • Patent number: 10310904
    Abstract: A distributed computing system that executes a set of long-lived jobs is described. During operation, each worker process performs the following operations. First, the worker process identifies a set of jobs to be executed and a set of worker processes that can execute the set of jobs. Next, the worker process sorts the set of worker processes based on unique identifiers for the worker processes. Then, the worker process assigns jobs to each worker process in the set of worker processes, wherein approximately the same number of jobs is assigned to each worker process, and jobs are assigned to the worker processes in sorted order. While assigning jobs, the worker process uses an identifier for each worker process to seed a pseudorandom number generator, and then uses the pseudorandom number generator to select jobs for each worker process to execute.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: June 4, 2019
    Assignee: Dropbox, Inc.
    Inventors: James Cowling, James Turner
  • Patent number: 10303861
    Abstract: The present invention features a system in which dynamic code randomization may be used in concert with enforcement-based mitigation policies to optimally secure a software code. A privileged, external execution context is employed when rewriting (randomizing) the software code. The rewritten code is then reloaded and executed in a less privileged execution context. Finally, the system ensures that the less privileged execution context is authorized to load and execute the code before rewriting.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: May 28, 2019
    Assignee: IMMUNANT, INC.
    Inventors: Andrei Homescu, Stephen J. Crane, Per Larsen
  • Patent number: 10295561
    Abstract: One aspect includes an electronic device that includes a component configured to generate diagnostic information indicative of a fault occurring in the electronic device. The electronic device also includes a persistent display coupled to the component and configured to display the diagnostic information.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: May 21, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel S. Critchley, Timothy F. McCarthy, Roderick G. C. Moore, Jonathan W. Short
  • Patent number: 10261887
    Abstract: A method for assertion debugging may include identifying in signals relating to an execution run of a code a segment of time for which an assertion has failed. The method may also include searching in the signals relating to that execution run, or in signals relating to another execution run of that code, to find one or a plurality of segments of time in which the signals are similar to the signals in the identified segment, for which the assertion was successful.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: April 16, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yonatan Ashkenazi, Nadav Chazan, Maayan Ziv
  • Patent number: 10249351
    Abstract: A memory subsystem is enabled with a write pattern command. The write pattern command can have a different command encoding from other write commands. The write pattern command triggers a dynamic random access memory (DRAM) device to write a data pattern that is internally generated, instead of a bit pattern on the data signal lines of the data bus. The internally generated data pattern can be read from a register, such as a mode register. In response to a write pattern command, the DRAM device provides the write pattern data from the register to the memory array to write. Thus, the memory controller does not need to send the data to the memory device.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Uksong Kang, Christopher E. Cox
  • Patent number: 10157157
    Abstract: Systems and methods for component population optimization are described. In some embodiments, an Information Handling System (IHS) may include a logic circuit and a memory coupled to the logic circuit, the memory having information stored thereon that, upon access by the logic circuit, enable the IHS to: identify a connector provided on a Printed Circuit Board (PCB), wherein the connector is configured to receive a device and to couple the device to a processor; and visually indicate a status of the connector.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: December 18, 2018
    Assignee: Dell Products, L.P.
    Inventors: Chris M. Helberg, Austin Michael Shelnutt, Travis C. North, Edward Douglas Knapton
  • Patent number: 10152432
    Abstract: A support information provisioning system a support device, an external device; and a customer device. The customer device includes an external connector and a remote access controller device that is coupled to the external connector. In situations where the customer device is experiencing at least one customer device issue that prevents the customer device from provisioning support information related to the operation of the customer device, the remote access controller device operates to detect that the external device has been connected to the external connector and, in response, automatically cause new support information about that customer device to be generated. When the external device is subsequently connected to the support device, it may then provide that new support information to the support device for analysis.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: December 11, 2018
    Assignee: Dell Products L.P.
    Inventors: Sundar Dasar, Divya Vijayvargiya, Sanjay Rao, Yogesh Prabhakar Kulkarni
  • Patent number: 10095594
    Abstract: Methods and apparatus to implement communications via a remote terminal unit are disclosed. An example apparatus includes a first central processing unit module to be in communication with a host of a process control system. The example apparatus also includes a first rack including a backplane and a plurality of slots. The plurality of slots includes a master slot to receive the first central processing unit module. The backplane communicatively couples the first central processing unit module to at least one of a first communication module or a first input/output (I/O) module inserted in a second one of the slots. The backplane includes a first communication bus for communication of I/O data and a second communication bus for communication of at least one of maintenance data, pass-through data, product information data, archival data, diagnostic data, or setup data. The first communication bus is independent of the second communication bus.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: October 9, 2018
    Assignee: BRISTOL, INC.
    Inventors: Richard Joseph Vanderah, Robert John Findley
  • Patent number: 10057350
    Abstract: A method, non-transitory computer readable medium, and device that assists with transferring data based on actual size of a data operation includes receiving a data operation from a client computing device. A type of the received data operation is determined and additional memory size associated with the determined type of the received data operation is identified. Next, a non-volatile log file is updated with the identified additional memory size and the determined type of the received data operation.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: August 21, 2018
    Assignee: NetApp, Inc.
    Inventors: Travis Callahan, An Zhu, Sandeep Budanur, Mrinal Bhattacharjee
  • Patent number: 10042737
    Abstract: Recording a replay-able trace of execution of a multi-threaded process includes identifying a trace memory model that defines one or more orderable events that are to be ordered across a plurality of threads of the multi-threaded process. The plurality of threads are executed concurrently across one or more processing units of one or more processors. During execution of the plurality of threads, a separate replay-able trace is recorded for each thread independently. Recording includes, for each thread, recording initial state for the thread, recording at least one memory read performed by at least one processor instruction executed by the thread that takes memory as input, and recording a least one orderable event performed by the thread with a monotonically increasing number that orders the event among other orderable events across the plurality of threads.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: August 7, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Jordi Mola
  • Patent number: 10025690
    Abstract: Described is a computer-implemented method of reordering condition checks. Two or more condition checks in computer code that may be reordered within the code are identified. It is determined that the execution frequency of a later one of the condition checks is satisfied at a greater frequency than a preceding one of the condition checks. It is determined that there is an absence of side effects in the two or more condition checks. The values of the condition checks are propagated and abstract interpretation is performed on the values that are propagated. It is determined that the condition checks are exclusive of each other, and the condition checks are reordered within the computer code.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: July 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takuya Nakaike, Takeshi Ogasawara
  • Patent number: 10015072
    Abstract: An automated network test system includes an integrated network switch connected to a network under test. The network switch includes a first and second plurality of network switch ports. The network switch further includes a physical layer engine coupled to the first plurality of network switch ports. The network switch also includes at least one processor having a plurality of processing cores that can each asynchronously execute a test execution context and a test engine having a plurality of dynamically configurable function modules. The test engine is coupled to the second plurality of network switch ports, the physical layer engine and at least one processor. The test engine is configured for automatic testing of the network under test.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: July 3, 2018
    Assignee: NetScout Systems, Inc.
    Inventors: Larry Cantwell, Steve Schmidt, Flex Houvig, Bill Higgins
  • Patent number: 9990244
    Abstract: A technique includes receiving an alert indicator in a distributed computer system that includes a plurality of computing nodes coupled together by cluster interconnection fabric. The alert indicator indicates detection of a fault in a first computing node of the plurality of computing nodes. The technique indicates regulating communication between the first computing node and at least one of the other computing nodes in response to the alert indicator to contain error propagation due to the fault within the first computing node.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: June 5, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Greg B Lesartre, Dale C Morris, Russ W Herrell, Blaine D Gaither
  • Patent number: 9946592
    Abstract: Provided are a computer program product, system, and method for dump data collection in accordance with one embodiment of the present description, in which a variable number of data dump components are selected from a set of data dump components. Each component contains a portion of an available dump data and has associated therewith a component collection time to collect the dump data associated with the component. A determination is made as to whether a total component collection time for the selection of data dump components exceeds a predetermined maximum. The dump data contained in the selection of data dump components is collected if the total component collection time for the selection of data dump components does not exceed the predetermined maximum. Other aspects of dump data collection management in accordance with the present description are described.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: April 17, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis A. Rasor, Juan J. Ruiz
  • Patent number: 9934134
    Abstract: System, method, and non-transitory computer-readable medium for generating a test scenario template from runs of test scenarios run on software systems belonging to different organizations, including: clustering the runs to clusters comprising similar runs of test scenarios; selecting from the clusters a certain cluster comprising a first run of a first test scenario and a second run of a second test scenario belonging to different organizations. At least 95% of values used in the first run of the first test scenario are provided automatically by a test script. And generating a test scenario template representing the certain cluster, wherein the test scenario template identifies a transaction used in the first and second runs, and possible values for running the transaction.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: April 3, 2018
    Assignee: Panaya Ltd.
    Inventors: Yossi Cohen, Mati Cohen, Nurit Dor, Dror Weiss
  • Patent number: 9875094
    Abstract: A method for upgrading microcode in a multi-module storage system may include selecting a first module from two or more modules and operating the first module using an upgraded microcode. The method may include monitoring the performance of the first module by a second module of the two or more modules and rendering an indication of performance of the first module. Further, the method may include determining whether the indication of performance of the first module is greater than or equal to a performance metric.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: January 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Juan A. Coronado, Lee C. LaFrese, Lisa R. Martinez
  • Patent number: 9852302
    Abstract: A human-machine chatting system facilitates real-time two-way communications between a user and a machine. During operation, the system monitors performance of a machine, runs a chat application on behalf of the monitored machine, and determines whether a user is authorized to access performance information associated with the monitored machine. In response to the user being authorized to access the performance information, the system allows the user to obtain the performance information via the chat application.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: December 26, 2017
    Assignee: VMware, Inc.
    Inventor: Raja Rao Dv
  • Patent number: 9842486
    Abstract: System and method for establishing configuration parameters for a comprehensive user interface of an alarm system. An exemplary embodiment of a configuration system in accordance with the present disclosure includes a plurality of alarm system workstations, each alarm system workstation having a set of configuration parameters associated therewith, a client workstation, and a user interface broker operatively connected to each of the alarm system workstations and the client workstation, wherein the user interface broker is configured to aggregate data from the alarm system workstations and to present such aggregated data at the client workstation using the comprehensive user interface. The user interface broker is further configured to facilitate designation of one of the alarm system workstations as a main workstation, whereupon the configuration parameters of the designated main workstation are applied to the comprehensive user interface.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: December 12, 2017
    Assignee: TYCO FIRE & SECURITY GMBH
    Inventors: J. R. Mario Boisclair, Joseph Piccolo, III, Dennis A. McEvoy, Mary Winna Fox, Kirill Alexandrov
  • Patent number: 9842017
    Abstract: Device health metrics may be collected and aggregated on a device before sending to a server for further aggregation. The method may include determining a crash has occurred on a device, and recording the crash and information corresponding to the crash in buffer storage on the device. The method may also include recording a crash type, a crash time, an identification of a component that caused the crash and a state of the device when the crash occurred. The method may also include grouping two or more crash events based on the crash type, generating device health metrics data including metadata corresponding to the two or more crash events, storing the device health metrics data in the buffer storage on the device, and sending the device health metrics data along with device identification information to a server for further aggregation.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: December 12, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Yuzhi Zhang, Rafael Camargo, David Junwei Tse, Tianhe Wang, Biju Balakrishna Pillai, Maulik Jayesh Pandey, Melissa Sue Erickson, Tianwei Liu, Cyrille Habis
  • Patent number: 9817686
    Abstract: A system includes a first computing device comprising a virtual machine (VM), a second computing device, and a third computing device coupled to the first and second computing devices. The third computing device includes a management module configured to migrate the VM from the first computing device to the second computing device. The management module is also configured to create a first signature of data associated with the VM stored by the first computing device over a first period of time and create a second signature of data associated with the VM stored by the first computing device over a second period of time. The management module is further configured to compare the first signature and the second signature throughout the migration process to determine whether the data has been altered and generate an alert when a difference between the first signature and the second signature is detected.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: November 14, 2017
    Assignee: The Boeing Company
    Inventor: Richard Matthew Lemanski
  • Patent number: 9811450
    Abstract: A tester instruction generation unit generates a tester instruction for terminals of a plurality of devices connected to a tester based on an instruction of a user program and causes an instruction storage unit to store the tester instruction. A transfer mode setting unit sets a transfer mode to either a successive transfer mode or a batch transfer mode, based on the number of tester instructions in the instruction storage unit or an instruction of the user program. A transfer control unit transmits the tester instruction in the instruction storage unit to the tester in accordance with the set transfer mode.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: November 7, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yukikazu Matsuo, Yasuyuki Tanaka, Masaru Sugimoto, Kyosaku Nobunaga
  • Patent number: 9811345
    Abstract: Utilizing computing resources under a disabled processor node, including: identifying a disabled processor node, the disabled processor node representing a computer processor that is not being utilized for general purpose computer program instruction execution; identifying one or more computing resources that can be accessed only by the disabled processor node; and enabling a portion of the disabled processor node required to access the one or more computing resources.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: November 7, 2017
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventor: Douglas W. Oliver
  • Patent number: 9798649
    Abstract: This disclosure involves debugging code for resource-constrained intelligent devices contemporaneously with executing object code on the intelligent device. For example, object code is transmitted to a radio device. A program counter entry is provided from the radio device to a computer via a communication link contemporaneously with a pause in execution of the object code at the radio device. A correspondence between the program counter entry and a portion of assembly code, which was used to generate the object code, is identified and is used to generate a list of additional program counter entries for pausing the object code's execution. The list is provided from the computer to the radio device and is used to pause the object code's execution at the radio device. Log data is provided from the radio device to the computer for display after pausing the object code's execution at one of these program counter entries.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: October 24, 2017
    Assignee: Landis+Gyr Innovations, Inc.
    Inventors: John Bettendorff, Tribhuwan Chandra Kandpal
  • Patent number: 9779559
    Abstract: An abnormality monitoring circuit of an ECU includes a microcomputer, a reset circuit that resets the microcomputer, a monitor circuit that monitors the operation of the microcomputer, and an output circuit that activates an external actuator. The monitor circuit has an abnormality decision signal output section that outputs an abnormality decision signal to the output circuit when not being able to confirm that an output of a normal monitor signal of the microcomputer has occurred within an abnormality decision time. The monitor circuit has a reset decision signal output section that outputs a reset decision signal to the reset circuit when not being able to confirm that an output of the normal monitor signal of the microcomputer has occurred within a BIST (Built In Self Test) completion time of the microcomputer and a reset decision time set to a time longer than the abnormality decision time.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 3, 2017
    Assignees: DENSO CORPORATION, ADVICS CO., LTD.
    Inventors: Shinichi Shimono, Kazuhiro Imoto, Risa Ito
  • Patent number: 9740599
    Abstract: A verification apparatus and method are disclosed for testing a device or system which is operable in a number of states through which it can transition in a multiplicity of different sequences. The method and apparatus disclosed include a set of functional modules which correspond to the states of the device or system under test and which may be activated in a large number of pseudorandom sequences. Each time a module of the verification apparatus is activated it causes the device or system under test to transition to the corresponding state. Thus, when the functional modules of the verification apparatus are activated in a given sequence, the corresponding states of the device or system under test are called in the same sequence.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: August 22, 2017
    Assignee: RANDOMIZE LIMITED
    Inventor: Giles Thomas Hall
  • Patent number: 9741084
    Abstract: A method and system for providing remote access to data for display on a client computer via a computer network is provided. A first and second server computer connected to a computer network execute a first and second server remote access program, respectively, for communicating with an associated first and second application program. The client computer, which is also connected to the computer network, executes a client remote access program for simultaneously communicating with the first and second server remote access programs via a first and second communication link. The first and second server remote access programs determine first and second presentation data indicative of an application state of the first and second application programs. The client remote access program receives the first and the second presentation data and determines display data in dependence thereupon for substantially simultaneously displaying the first and the second presentation data.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: August 22, 2017
    Assignee: Calgary Scientific Inc.
    Inventors: Colin J. Holmes, Pierre Lemire, Glenn Lehmann
  • Patent number: 9734033
    Abstract: A method and system are provided for implementing functional verification including generating and running constrained random irritator tests for a multiple processor system and for a processor core with multiple threads. Separate tests are generated, a main test for one thread, and an irritator test for each other thread in the configuration. The main test and each irritator test are saved and randomly mixed then combined together again, where the main thread is not forced to be generated with any particular irritator.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: August 15, 2017
    Assignee: International Business Machines Corporation
    Inventors: Olaf K. Hendrickson, Yugi Morimoto, Michael P. Mullen, Michal Rimon
  • Patent number: 9723610
    Abstract: A device for transmitting data to a network includes a source subsystem and a communication subsystem. The source subsystem generates a first data packet that includes first timing information that is based on a time that the first data packet is generated. The first timing information is generated responsive to a first timing generator included in the source subsystem. The communication subsystem is coupled to the source subsystem via one or more abstraction layers and is configured to modify the first data packet to generate a modified data packet for transmission to the network. The modified data packet includes the first timing information and second timing information that is based on a time that the modified data packed is transmitted. The communications subsystem includes a second timing generator that is linked to the first timing generator through the one or more abstraction layers to generate the second timing information.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: August 1, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Khosro Mohammad Rabii, Vijay Naicker Subramaniam, Alireza Raissinia, Fawad Shaukat, Shivakumar Balasubramanyam
  • Patent number: 9716520
    Abstract: An integrated standard-compliant data acquisition device includes an electrically insulating package including a plurality of conductive leads and an integrated circuit (IC) disposed within the electrically insulating package and electrically coupled to at least some of the plurality of conductive leads. The IC includes a first multiplexer (MUX), a second MUX, a third MUX, an analog-to-digital converter (ADC), a plurality of registers, a fourth MUX, control logic, and communication circuitry. In operation, a first circuit value under a first condition can be determined and stored, a second circuit value under a second condition can be determined and stored, and the decision as to whether there is a fault condition can be mad by comparing the first circuit value and the second circuit value.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: July 25, 2017
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Bryan A. Mueller, Erik S. Wheeler, Mark R. Plagens, Urs Mader
  • Patent number: 9613901
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of planes vertically stacked over a substrate. Each plane includes one or more cell mats. Each cell mat includes lower lines, upper lines crossing the lower lines, and variable resistance elements positioned in intersection regions of the lower lines and the upper lines, respectively. Lower contacts are coupled to the lower lines, respectively, and, in a plan view, overlap with a boundary region between half of the upper lines and the other half number of the upper lines. Upper contacts are coupled to the upper lines, respectively, and overlap with a boundary region between a half number of the lower lines and the other half number of the lower lines. One cell mat of an upper plane is vertically stacked over a lower plane to overlap with two adjacent cell mats of the lower plane.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: April 4, 2017
    Assignee: SK HYNIX INC.
    Inventors: Seung-Hwan Lee, Hyun-Jeong Lee
  • Patent number: 9606847
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for detecting and reporting errors in a machine check environment. A processing device includes an error monitoring module, which detects an error corresponding to data associated with execution of an instruction by the processing device and determines whether the error occurs on portion of the data that affects a result of the instruction. The processing device further enables error detection when it is determined that the error occurs on the portion of the data that affects the result of the execution of the instruction.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: March 28, 2017
    Assignee: Intel Corporation
    Inventors: Jesus San Adrian Corbal, Dennis R. Bradford, Rohan Sharma
  • Patent number: 9594818
    Abstract: A system and method can support subnet management in a network environment. One or more inactivated switches can be included in a subnet, wherein each of the inactivated switches is associated with an empty set of known secret keys. A subnet manager (SM) in a dry-run mode can perform one or more dry-run operations on the one or more inactivated switches, before activating the one or more inactivated switches.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: March 14, 2017
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Bjørn Dag Johnsen, Dag Georg Moxnes, Line Holen, Kurt Tjemsland
  • Patent number: 9594526
    Abstract: When a failure occurs in a storage device, a backup unit specifies LUNs of a copy source and a copy destination to an operation volume for which a process is not taken over to another storage device and instructs to perform a copy. When a copy processing unit in the storage device receives a copy process to be performed in the operation volume, the copy processing unit performs the copy process by using the specified LUNs of the copy source and the copy destination. If an error occurs without the copy process being taken over to another storage device due to the occurrence of a failover, the backup unit acquires the LUNs of two volumes of a copy pair and the volumes each constituting each of cluster pairs. Then, the backup unit again performs the copy process by using the acquired LUNs.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: March 14, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Akio Yamaguchi, Makoto Yashiro, Yuki Tamura, Hajime Kondo
  • Patent number: 9455401
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of first lines extending in a first direction, a plurality of second lines extending in a second direction crossing the first direction, a resistance variable layer interposed between the first lines and the second lines, a tunnel barrier layer interposed between the resistance variable layer and the first lines, and an intermediate electrode layer interposed between the resistance variable layer and the tunnel barrier layer. The tunnel barrier layer and the intermediate electrode layer overlap with at least two neighboring intersection regions of the first lines and the second lines.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: September 27, 2016
    Assignee: SK HYNIX INC.
    Inventors: Wan-Gee Kim, Kee-Jeung Lee, Hyung-Dong Lee
  • Patent number: 9442788
    Abstract: A system on chip (SoC) includes a system bus; a plurality of intellectual properties (IPs) outputting bus signals via the system bus; and one or more checkers disposed to correspond to at least some of the plurality of IPs, wherein the checker includes: a first environment setting register for setting information about a check target and list, on which a bus protocol check operation will be performed, wherein the setting may be variable according to an access from outside via the system bus; and a check logic receiving the bus signal and performing a bus protocol check operation on a signal included in the bus signal according to the information set in the first environment setting register.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: September 13, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Deum-Ji Woo, Yong Je Lee, Young-Jun Kwon
  • Patent number: 9401004
    Abstract: One embodiment of the present invention sets forth a technique for tracking and filtering state change methods provided to a graphics pipeline. State shadow circuitry at the start of the graphics pipeline may be configured in different modes. A track mode is used to capture the current state by storing state change methods that are transmitted to the graphics pipeline. A passthrough mode is used to provide different state data to the graphics pipeline without updating the current state stored in the state shadow circuitry. A replay mode is used to restore the current state to the graphics pipeline using the state shadow circuitry. Additionally, the state shadow circuitry may also be configured to filter the state change methods that are transmitted to graphics pipeline by removing redundant state change methods.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: July 26, 2016
    Assignee: NVIDIA Corporation
    Inventors: Jerome Francis Duluk, Jr., Jesse David Hall, Patrick R. Brown, Gregory Scott Palmer, Eric S. Werness
  • Patent number: 9384109
    Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: July 5, 2016
    Assignee: TEXAS INSTRUMENTS DEUTSCHLAND GMBH
    Inventors: Shrey Bhatia, Christian Wiencke, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch
  • Patent number: 9377955
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of planes vertically stacked over a substrate. Each plane includes one or more cell mats. Each cell mat includes lower lines, upper lines crossing the lower lines, and variable resistance elements positioned in intersection regions of the lower lines and the upper lines, respectively. Lower contacts are coupled to the lower lines, respectively, and, in a plan view, overlap with a boundary region between half of the upper lines and the other half number of the upper lines. Upper contacts are coupled to the upper lines, respectively, and overlap with a boundary region between a half number of the lower lines and the other half number of the lower lines. One cell mat of an upper plane is vertically stacked over a lower plane to overlap with two adjacent cell mats of the lower plane.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: June 28, 2016
    Assignee: SK HYNIX INC.
    Inventors: Seung-Hwan Lee, Hyun-Jeong Lee
  • Patent number: 9348537
    Abstract: Ascertaining command completion in flash memories is disclosed. An exemplary aspect includes eliminating the software lock and the outstanding requests variable and replacing them with a transfer request completion register. The transfer request completion register may be mapped to the universal flash storage (UFS) Transfer Protocol (UTP) Transfer Request List (UTRL) slots. The controller of the host—a hardware component—may set the bit in the transfer request completion register on transfer request completion at the same time the doorbell register is cleared. After this bit has been read, the bit in the transfer request completion register is cleared.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: May 24, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Dolev Raviv, Tatyana Brokhman, Maya Haim, Assaf Shacham
  • Patent number: 9348735
    Abstract: Selecting a transaction for a certain user based on similarity of a profile of the certain user to profiles of users belonging to different organizations involves executing the following: receiving activity data obtained by monitoring activity of the users on software systems; identifying transactions executed by the users on the software systems; generating profiles of the users, based on the transactions, indicating transactions executed by the users; receiving a profile of the certain user, which indicates transactions executed by the certain user; and selecting, based on similarity of at least some of the profiles of the users to the profile of the certain user, a certain transaction that was executed by a user with a similar profile to the profile of the certain user.
    Type: Grant
    Filed: December 28, 2013
    Date of Patent: May 24, 2016
    Assignee: Panaya Ltd.
    Inventors: Yossi Cohen, Mati Cohen, Nurit Dor, Dror Weiss
  • Patent number: 9348717
    Abstract: The disclosed embodiments relate to systems and methods for coordinating management of a shared disk storage between nodes. Particularly, a messaging protocol may be used to communicate notifications regarding each node's perception of the shared storage's state. The nodes may use the messaging protocol to achieve consensus when recovering from a storage device failure. Some embodiments provide for recovery when localized failures, such as failures at an adapter on a node, occur.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: May 24, 2016
    Assignee: NETAPP, INC.
    Inventors: Todd Mills, Suhas Urkude, Kyle Sterling, Atul Goel
  • Patent number: 9317404
    Abstract: System, method, and non-transitory medium for generating a test scenario template involving the steps of monitoring users belonging to different organizations to identify runs of test scenarios run on software systems belonging to the different organizations; clustering the runs to clusters of similar runs; selecting a certain cluster from the clusters; and generating, based on runs belonging to the certain cluster, a test scenario template. The template may represent the certain cluster and identify a transaction used in runs belonging to the certain cluster, and possible values for running the transaction.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: April 19, 2016
    Assignee: Panaya Ltd.
    Inventors: Yossi Cohen, Mati Cohen, Nurit Dor, Dror Weiss
  • Patent number: 9251039
    Abstract: Debugging capabilities for software running in a cloud-computing environment are disclosed. A controller identifies which machines in the cloud are running instances of software to be debugged. An agent is deployed onto the machines in the cloud to facilitate communication with the developer's machine. When the developer wants to debug software on the agent's machine, the agent downloads and installs a monitor onto the machine. The agent configures the machine for remote debugging via the monitor. A security mechanism ensures that only authenticated developers can access the monitor and the remote machine for debugging. A controller automatically determines which machines can be debugged, updates a list of processes available for debugging on the machines, and identifies how to connect a developer's debugging client to the machines. The controller permits remote debugging only upon request from an authenticated developer and only for those processes that the developer is permitted to debug.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: February 2, 2016
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Sung Hon Wu, Lubomir Birov, Anthony Crider, Jeffrey Young