Abstract: A checking system is described for determining whether a component is thread safe in the course of interacting with two or threads in a client environment. The checking system uses a manual, automatic, or semi-automatic technique to generate a test. The checking system then defines a set of coarse-grained observations for the test, in which the component is assumed to exhibit linearizability when interacting with threads. The set of coarse-grained observations may include both complete and “stuck” histories. The checking system then generates a set of fine-grained observations for the tests; here, the checking system makes no assumptions as to the linearizability of the component. The checking system identifies potential linearizability errors as those entries in the set of fine-grained observations that have no counterpart entries in the set of coarse-grained observations. The checking system may rely on a stateless model checking module to perform its functions.

Abstract: A method and apparatus of stopping a functional block of an integrated circuit (IC) for debugging purposes is disclosed. In one embodiment, an IC includes a number of functional units accessible by an external debugger via a debug port (DP). During a debug operation, a power controller in the IC may power down a functional unit. When the functional unit is powered off, a first register may be programmed. Responsive to the programming of the first register, a first signal may be asserted and provided to the functional unit. When power is restored to the functional unit, operation of the functional unit may be halted prior to execution of instructions or other operations, responsive to the signal.

Abstract: An automated regression testing intermediary configured to accept a first set of automated test instructions from an application testing tool. A data structure comprising predefined fields is configured so when a test instruction is received from the application testing tool, a command will be used to identify at least one field of the data structure that will be populated with a parameter test instruction. A library of generic target automated test instructions is provided. Each generic test instruction has a form and format different from the received test instruction. The intermediary is configured to select generic target automated test instructions from the library and populate selected generic target automated test instructions with parameters obtained from the data structure such that the resulting created target-specific automated test instructions can be used to regression test the application under test.

Abstract: A system and method is shown that includes a processor operatively connected to a memory, the processor to include a memory controller to control access to the memory. The system and method also includes a service processor, co-located on a common board and operatively connected to the processor and the memory, the service processor to include an additional memory controller to control access to the memory as part of a checkpoint regime.

Abstract: A staggered execution environment is provided to safely execute an application program against software failures. In an embodiment, the staggered execution environment includes one or more probe virtual machines that execute various portions of an application program and an execution virtual machine that executes the same application program within a time delay behind the probe virtual machines. A virtualization supervisor coordinates the execution of the application program on one or more probe virtual machines. The probe virtual machines are used to detect and correct software failures prior to the execution virtual machine encountering them. The virtualization supervisor embargos output data in order to ensure that erroneous data is not released which may adversely affect external processes.

Abstract: A high speed data processing system is described comprising first and second data processing modules and first and second data checking modules. The first and second data processing modules are each arranged to perform substantially the same processing steps on data received at said data input, with each providing an output. The first and second checking modules are arranged to compare the outputs of said first and second data processing modules and to output an error signal indicative of whether or not said first and second data processing modules have performed substantially the same processing steps. The first and second checking modules are located on physically separate devices. In some arrangements a third checking module is provided, which checking module may be physically separated from each of said first and second checking modules.

Abstract: Some embodiments of a system and a method to perform distributed healthchecking in a cluster system have been presented. For instance, a distributed healthchecking manager executable on a centralized server in a cluster system can assign nodes of the cluster system to at least some of the nodes for healthchecking. Then the distributed healthchecking manager may monitor the nodes performing healthchecking for reports of one or more failed nodes.

Abstract: A computer usable program product for accelerating recovery in an MPI environment is provided in the illustrative embodiments. A first portion of a distributed application executes using a first processor and a second portion using a second processor in a distributed computing environment. After a failure of operation of the first portion, the first portion is restored to a checkpoint. A first part of the first portion is distributed to a third processor and a second part to a fourth processor. A computation of the first portion is performed using the first and the second parts in parallel. A first message is computed in the first portion and sent to the second portion, the message having been initially computed after a time of the checkpoint. A second message is replayed from the second portion without computing the second message in the second portion.

Abstract: Systems, methods, apparatus and software can implement a flexible I/O fence mechanism framework allowing clustered computer systems to conveniently use one or more I/O fencing techniques. Various different fencing techniques can be used, and fencing mechanism can be customized.

Abstract: The present invention relates generally to process control systems and devices and, more particularly, to an apparatus for and a method of implementing redundant controller synchronization for bump-less failover during normal and mismatch conditions at the redundant controllers. The redundant controllers are configured to transmit state information of the process control areas of the primary controller to the backup controller that is necessary for synchronizing the redundant controllers but is not typically transmitted to other devices during the performance of process control functions. Synchronization messages are transmitted from the primary controller to the backup controller each time one of the control areas executes to perform process control functions.

Abstract: A plurality of processing cores, are central storage unit having at least memory connected in a daisy chain manner, forming a daisy chain ring layout on an integrated chip. At least one of the plurality of processing cores places trace data on the daisy chain connection for transmitting the trace data to the central storage unit, and the central storage unit detects the trace data and stores the trace data in the memory co-located in with the central storage unit.

Abstract: An embodiment of the present invention may provide a method and system for event notification, performance and/or risk assessment based on mission impact that may be due to actual and/or potential info-structure disruptions. In one embodiment of the present invention, one or more network event messages may be received from a source or multiple sources. An operational mission impacted by a network event may be identified based on a received network event message and mapping with an operational architecture task identifier associated with the impacted operational mission and an element identifier associated with a source element.

Abstract: Systems and methods for providing automated problem reporting in elements used in conjunction with computer networks are disclosed. The system comprises a plurality of elements that perform data migration operations and a reporting manager or monitor agent which monitors the elements and data migration operations. Upon detection of hardware or software problems, the reporting manager or monitor agent automatically communicates with elements affected by the problem to gather selected hardware, software, and configuration information, analyzes the information to determine causes of the problem, and issues a problem report containing at least a portion of the selected information. The problem report is communicated to a remote monitor that does not possess access privileges to the elements, allowing automated, remote monitoring of the elements without compromising security of the computer network or elements.

Abstract: A remote diagnostic system and method based on device data classification. Device diagnostic data with respect to a device can be acquired and a conditional probability look up table can be constructed for each fault code associated with the device diagnostic data by a classification module. A score function can then be created by summing the conditional probabilities and an occurrence of the fault code can be mapped to a service call category with a numerically highest score function. The fault occurrence data in association with a number of time stamps and device identifiers can be stored in a data warehouse. The occurrence of fault code can be matched with respect to a solution set which can be automatically dispatched to a customer via a communications link.

Abstract: An automation process verifies that a test bed includes a set of devices specified by at least one script which are to be executed by the automation process on the test bed. The test bed is locked and the set of devices is allocated to the automation process. Performance data collection and logging for the set of devices is started and the at least one script is executed on the set of devices. After executing the at least one script, the set of devices is de-allocated and the test bed is unlocked. A notification is generated indicating that the at least one script has been executed.

Abstract: Proposed are a disk array system and a traffic control method with which reliability can be improved by preventing system shutdown. A disk array system comprises a controller for controlling data I/O to and from a backend unit; a plurality of expanders provided in the backend unit and connected to the controller by way of a tree-structure topology; a plurality of storage devices provided in the backend unit and each connected to the corresponding expander; and a control unit for controlling the controller on the basis of an I/O request from a host device. The disk array system is configured such that the controller notifies the control unit of a link fault that has occurred in the backend unit, and the control unit, when supplied with the link fault notification from the controller, restricts issuance of I/O requests from the host device or restricts receipt of I/O requests sent from the host device as necessary.

Abstract: A scenario creating apparatus which creates a scenario for verifying operation of an information processing system in which a plurality of servers including a database server are connected, includes a collector that collects messages transmitted and received between the plurality of servers, when operation of the information processing system is being verified by a terminal apparatus that performs verification of operation; an association unit that associates the collected messages with each other; a sorter that sorts work models in ascending order of time at which access is made to the database server, the work models each being a group of the associated messages; and a scenario creating unit that creates the scenario on the basis of the sorted work models.

Abstract: A processor and memory system includes memory, a table of exceptions, and a processor. The memory includes a plurality of memory blocks. The table of exceptions identifies at least one of the plurality of memory blocks that includes an expected error. The processor diagnoses a security fault based on data stored in at least one of the plurality of memory blocks and the table of exceptions.

Abstract: A method and system for accelerating recovery in an MPI environment are provided in the illustrative embodiments. A first portion of a distributed application executes using a first processor and a second portion using a second processor in a distributed computing environment. After a failure of operation of the first portion, the first portion is restored to a checkpoint. A first part of the first portion is distributed to a third processor and a second part to a fourth processor. A computation of the first portion is performed using the first and the second parts in parallel. A first message is computed in the first portion and sent to the second portion, the message having been initially computed after a time of the checkpoint. A second message is replayed from the second portion without computing the second message in the second portion.

Abstract: A system and method is disclosed for testing emulation boards in a hardware emulation environment. In one embodiment, test files can be maintained that identify a list of test commands. Such a list can be easily changed without recompiling. In another embodiment, the list of commands can be read by a first server. The commands can be passed (e.g., sequentially) to a second server associated with one or more emulator boards. The second server can ensure that the commands are executed on the specified emulator boards for testing the emulator boards. In yet another embodiment, a user can request a series of tests to be executed. The tests can be included in a list of test names. Each test name can correspond to a list of test commands associated with the test name. Thus, a first server can read a test name, read a file of test commands associated with the test name and pass the test commands to a second server to ensure the test commands are executed.

Abstract: A method utilizes a virtual flight recorder to harvest a subset of events being collected by an active system tracing facility during operation of a computer system. The virtual flight recorder is “virtual” from the sense that it is not specifically instrumented into a component with which the virtual flight recorder is associated, which eliminates the burden on developers to specifically instrument components of interest, and minimizes the impact on system performance as a result of performance metric collection.

Abstract: An exemplary method facilitates automatic recovery upon failure of a server in a network responsible for replying to user requests. Periodic heartbeat information is generated by a first group of servers responsible for replying to user requests. The heartbeat information provides an indication of the current operational functionality of the first group of servers. A second group of servers determines that one of the first servers has failed based on the periodic heartbeat information. The second group of servers is disposed in communication channels between users and the first group of servers. One of the second group of servers receives a message containing a request from a first user having the one of the first group of servers as a destination. One of the second group of servers determines that the message is part of an ongoing dialog of messages between the first user and the one of the first group of servers.

Abstract: A staggered execution environment is provided to safely execute an application program against software failures. In an embodiment, the staggered execution environment includes one or more probe virtual machines that execute various portions of an application program and an execution virtual machine that executes the same application program within a time delay behind the probe virtual machines. A virtualization supervisor coordinates the execution of the application program on one or more probe virtual machines. The probe virtual machines are used to detect and correct software failures prior to the execution virtual machine encountering them. The virtualization supervisor embargos output data in order to ensure that erroneous data is not released which may adversely affect external processes.

Abstract: An interface unit is provided in a JTAG test and debug procedure involving a plurality of processor cores. The interface unit includes a TAP unit. A switch unit is coupled to the interface unit and switch units are coupled to each of the plurality of processor/cores. When the processor/cores have advanced power management systems, a sleep inhibit signal can be applied to the processor/core state machine preventing the state machine from entering a lower power state. The parameters of the processor/core can be tested to determine when the test and debug procedures can be implemented. When the (power) parameters are to low to permit test and debug, the test and debug unit can provide a command forcing the state machine into a state for which test and debug procedures can be implemented.

Abstract: A computer apparatus includes a first processor, a second processor, and a main memory. The computer apparatus further includes a memory-diagnostic unit, a diagnostic-program loading unit, and a defective-function identifying unit. The memory-diagnostic unit causes the second processor to execute a memory-diagnostic program to diagnose the main memory, and identifies a defective area in the main memory. The diagnostic-program loading unit loads a processor-diagnostic program for diagnosing a plurality of functions of the first processor into an area of the main memory other than the defective area identified by the memory-diagnostic unit. The defective-function identifying unit causes the second processor to execute the processor-diagnostic program loaded by the diagnostic-program loading unit, and identifies a defective function that is disabled from the functions of the first processor.

Abstract: A micro controller includes an input and output unit having a reset terminal, a plurality of input terminals, and a test enable terminal, a test mode setting unit which allocates a first input terminal of the plurality of input terminals to a test clock terminal and allocates the remaining N input terminals to L test terminals, in response to a signal output from the input and output unit, and a processor which controls the input and output unit and the test mode setting unit. The test mode setting unit includes M flip-flops which receives a test clock signal from the first input terminal, a test signal from the N input terminals, and a test enable signal from the test enable terminal, and a decoder which decodes a signal output from the M flip-flops and determines whether or not to allocate the N input terminals to the L test terminals.

Abstract: A method of monitoring a network is disclosed and includes receiving an enrollment message at a heartbeat manager from a heartbeat agent associated with a first application stored at a first network entity. The method also includes automatically associating a heartbeat interval with the first application based at least partially on the enrollment message. In another embodiment, a system of monitoring a network is disclosed and includes a network entity having processing logic and memory accessible to the processing logic. The memory stores an application including a heartbeat agent portion having instructions executable by the processing logic to enroll with a heartbeat management server communicating with the network entity and including a heartbeat monitor including instructions to subscribe to notifications indicating an operational status of an application residing at a second network entity.

Abstract: A method includes determining a rule lookup key for a computer system to be diagnosed, retrieving a diagnostic rule set associated with the rule lookup key, and executing the diagnostic rule set on the computer system. The computer system may include a computer and peripherals arranged in a configuration, and the diagnostic rule set executed on the computer system may be based on changes in configuration or behavior attributes of the computer system.

Abstract: The present invention relates to a remote control (160) operates fail-safe. The remote control comprises a safety filter (150) in order to provide a fail save operation. The present invention also relates to an adjustable patient table (100) comprising a fail-safe wireless remote control for controlling an actuator to adjust the table.

Abstract: Method and system of error logging. At least some of the illustrative embodiments are methods including detecting assertion of an error pin by a processor system, (comprising at least a main processor and a chipset, the assertion of the error pin an indication to reboot the processor system) the detecting by a reset circuit, notifying a management processor (distinct from the main processor) that the error pin is asserted (the notifying by the reset circuit), writing to a plurality of registers in the chipset (the writing by the management processor), de-asserting a reset pin of the main processor, and then executing by the main processor an error-handling code to generate an error log.

Abstract: Results of field testing of portions of a distributed system such as a Broadband Communications System from a testing device to a controller which downloads programmed test protocols and sequences thereof to the separate testing device over a wired or wireless link and thereafter can be used to control the testing device as well as display test results and provide analysis of the test results and suggest procedures to technical personnel. The controller then can transmit the test data to a central facility or distribution hub in substantially real-time together with work performance data where full technical analysis can be performed. The test data and results of analysis can then be distributed as desired such as to a management analysis facility to support improvement of efficiency of the system and the operation thereof.

Abstract: A data processing system 2 is provided with multiple processors 4, 6 which can operate in either a split-mode in which each processor executes its own program flow or a locked-mode in which the processors execute the same program flow. Debug circuitry 8, 10 is associated with each of the processors. In an emulation-locked mode of operation, one of the processors 4 is active and its respective debug circuitry 8 is active to update the debug state data so as to debug the locked mode code. At the same time, the second processor 6 is held inactive and its state is maintained as well as the debug state data of the debug circuitry 10 within that inactive processor. This maintains the debug state data of the processor 6 across entry and exit to the locked mode of operation.

Abstract: A test system 100 that can accept a plurality of plug-in electronic cards in Xi Slots 126 or PXI slots 134 is described. The test or source measure switching system 100 includes a sequencer or sequence engine 130 which is fully capable of executing opcode instructions having potentially indefinite completion times and monitoring multiple asynchronous inputs simultaneously without interrupts. The sequencer 130 is sequential and deterministic to approximately ten microsecond resolution.

Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. In particular, the techniques and systems relate to design instrumentation circuitry that facilitates the analysis, diagnosis and debugging of the hardware designs. A HDL design instrumentation circuitry embedded within an electronic system comprises one or more probe circuits to allow storage of signal values of the electronic system upon predetermined events, one or more breakpoint registers to specify the predetermined events, and one or more trigger processing units to control the storage of signal values upon the detection of the predetermined events by the breaking registers. The present design instrumentation circuitry permits monitoring the electronic system at speed, facilitating the analysis diagnosis and debugging by giving detailed and accurate information about the operation of the electronic system.

Abstract: A method and system for transmitting data corresponding to at least one endpoint device problem in a packet communications network is described. Specifically, an endpoint device detects at least one problem that pertains to the endpoint device. The endpoint device then generates data pertaining to the endpoint device problem. Lastly, the endpoint device then transmits the data detailing that endpoint device problem to the packet communications network.

Abstract: Methods and apparatuses for on-line testing for decode logic are presented. In one embodiment, a processor comprises translation logic to decode an instruction to micro-operations and extraction logic to determine first information about numbers of occurrences of fields in the micro-operations. In one embodiment, the processor further comprises verification logic to indicate whether the decoding results of the instruction are accurate based at least on the first information.

Abstract: A technique is disclosed for distributed runtime diagnostics in hierarchical parallel environments. In one embodiment, a user is allowed to configure, during runtime, a processing element on which to perform diagnostics, an algorithm for the processing element to execute, a data set for the algorithm to execute against, a diagnostic function for the processing element to execute, a condition for executing the diagnostic function, and visualization parameters for memory local to the processing element. As a result, runtime diagnostics can be performed with sufficient degree of control and customization to aid debugging in a hierarchical parallel environment.

Abstract: A method for safeguarding data stored in a memory of a data storage system includes monitoring values of a subset of environmental variables associated with the data-storage system and updating a portion of a table containing values of environmental variables associated with the data-storage system. The table includes values for environmental variables that are not in the subset of environmental variables monitored. The values of the environmental variables are then inspected. On the basis of the inspection, a condition in which there exists a high-risk of data loss is determined.

Abstract: Methods and systems for remotely debugging a software program are provided. The methods and systems make use of a debugger application executing on a host computer and configured to communicate with a debugger module executing on a target computer via a distributed computing network, such as the Internet.

Abstract: In an embodiment, a method is provided for tracking a test. In this method, a test session identifier is transmitted to a test system. The test session identifier identifies a particular test session. A test of a component is triggered at the test system, and this test provides test results, which are received from the test system. The test results include the test session identifier, which allows the tests to be associated with the particular test session.

Abstract: The present invention discloses a method for accessing a target disk and a system for expanding disk capacity. A processing unit of a master disk array sends a command or data to a PCIe switching unit of the master disk array upon receipt of the command or data; the PCIe of the master disk array sends the received command or data to a control unit in a corresponding disk array according to an address of a target disk indicated in the command or data; the control unit in the corresponding disk array sends the received command or data to the target disk that is directly connected to the control unit. The present invention also discloses a master disk array and a slave disk array.

Abstract: A system for validating communications between a plurality of processors is disclosed. The system includes a plurality of loop back paths, and each of the loop back paths is coupled to a corresponding one of the plurality of processors. In addition, each loop back path is configured to attenuate one of a plurality of signals transmitted from each of the corresponding ones of the plurality of processors so as to generate a plurality of loop back signals. A plurality of signal transmission paths are configured to carry a corresponding one of the plurality of signals from one of the plurality of processors to another of the plurality of processors, and a plurality of comparators compare the plurality of loop back signals to the plurality of transmission signals so as to enable the validity of each of the plurality of signals to be assessed.

Abstract: A system and method is shown that includes a processor operatively connected to a memory, the processor to include a memory controller to control access to the memory. The system and method also includes a service processor, co-located on a common board and operatively connected to the processor and the memory, the service processor to include an additional memory controller to control access to the memory as part of a checkpoint regime.

Abstract: An apparatus maintenance system and method are provided. The apparatus maintenance system includes an apparatus including a first control part, and a second control part connected to the first control part and a maintenance-data management server managing maintenance data about the apparatus. The second control part downloads the maintenance data from the maintenance-data management server to transfer the downloaded maintenance data to the first control part and transmits a maintenance result transferred from the first control part to the maintenance-data management server.

Abstract: Disclosed is a system for verifying a multimedia player. The system includes a multimedia player, a verification mechanism, a serial number generator, an audio and video data unit and a test mechanism. The multimedia player includes a communication interface and a storage unit. The verification mechanism includes a communication interface connected to the communication interface of the multimedia player. The serial number generator is connected to the communication interface of the verification mechanism. The audio and video data unit is connected to the communication interface of the verification mechanism. The test mechanism is connected to the communication interface of the multimedia player.

Abstract: An instruction converting unit converts the data form of an instruction of an operation received by a receiving unit to the data form of a safety instrumentation system from the data form of a plant control system. An operation carrying out unit receives the instruction of the operation obtained by the instruction converting unit and an original instruction of the safety instrumentation system to carry out the operations, and preferentially carries out the operation of the original instruction of the safety instrumentation system when both the instructions compete with each other.

Abstract: A new service, or new version of an existing service, can be tested using actual production requests and services. A request received by a production service, along with the response generated by the production service, is forwarded to a shadow service. The shadow service forwards the request to the new service, which generates a test response and sends the test response back to the shadow service. The shadow service utilizes a comparison engine operable to compare the responses for significant differences. Any significant differences can be logged, reported on, or added to statistics for the new service being tested.

Abstract: A method of storing data from a plurality of processors comprising the steps of (a) transferring data along a first bus (b) connectable between a first processor and a synchronizing means and operable with a first protocol; (c) synchronizing the synchronizing means with a second processor; and (d) transferring the data along a second bus to a memory of the second processor wherein the second bus is connectable between the synchronizing means and the memory of a second processor and operable with a second protocol.

Abstract: A distributed system checker may check a distributed system against events to detect bugs in the distributed system. The events may include machines crashes, network partitions, and packet losses, for example. The distributed system checker may check a distributed system that can have multiple threads and multiple processes running on multiple nodes. To obtain control over a distributed system, a distributed system checker may insert an interposition layer between a process and the operating system on each node.

Abstract: A method to synchronize Fault Code Memory between at least a first module and a second module in an engine controller unit; each said module in electronic communication with each other and having volatile and non volatile memory; said modules in electronic communication; when compatibility of versions of static fault codes between the modules is established, the first module downloads and saves the static fault code table resident on the second module in nonvolatile memory for access by a diagnostic tool.