Abstract: An on-chip debug emulator is capable of connecting to the target device and the host device for remotely debugging the program in the target device. The on-chip debug emulator contains a debug communication control unit. This debug communication control unit contains a plurality of serial communication circuits, the plurality of serial communication circuits are commonly provided with a clock signal. The debug communication control unit controls communications with the target device based on commands output from the host device. Each of The plurality of serial communication circuits contains a data buffer and serially transmits data stored in the data buffer to and from the target device while synchronized with the clock signal. Namely, the plurality of serial communication circuits communicate in parallel while operating synchronized with the same clock. The on-chip debug emulator can in this way be made utilizing a low-cost microcomputer not containing any parallel communication circuits.

Abstract: Described embodiments provide for end-of-life (EOL) checking for NAND flash devices. An exemplary implementation of a computing environment comprises at least one NAND data storage device operative to store one or more data elements. In the illustrative implementation, the EOL data processing and storage management paradigm allows for the storage of data according using a selected EOL enforcement algorithm that can utilize current and/or historical correction levels. The NAND data storage EOL checking module can be operable to cooperate with one or more NAND data store components to execute one or more selected EOL operations to protect stored data.

Abstract: The present invention provides a control system which is used for a stacked battery of a plurality of battery packs. Each battery pack has a plurality of battery cells coupled in series. The control system is capable of reconfiguring communication among the battery packs in the stacked battery, and comprises a plurality of processors, a plurality of controllers, and a monitoring unit. The processors are coupled to the battery packs. Two adjacent processors among the processors are able to communicate with each other though a first bus. The controllers are coupled to the battery packs. Two adjacent controllers among the controllers are able to communicate with each other through a second bus. The processors are capable of communicating with the controllers through a third bus. The monitoring unit is used for monitoring communications among the plurality of processors and communications among the plurality of controllers.

Abstract: Systems and methods are provided for securing a multicore computer chip with a watchdog processor. In a system with a watchdog process and any number of other processors and components, the watchdog processor monitors bus communications between the second processor and at least one third component. The watchdog processor may be further independently coupled to at least one of the other components so that it can monitor internal operations of such component, thereby acquiring detailed information about the specific operations of at least one component in the system. The watchdog processor can enforce an interaction policy on bus communications between components, as well as enforce an independent security policy on the monitored components.

Abstract: The present invention is directed to the detection of faulty CPU heat sink coupling during system power-up. A method in accordance with an embodiment of the present invention includes: monitoring a slope of a CPU temperature rise from initial system power-up; determining if the slope of the CPU temperature rise exceeds an expected value; and in the case that the slope of the CPU temperature rise exceeds the expected value, indicating an existence of a possible fault (PFA) related to a heat sink coupled to the CPU.

Abstract: Apparatus, systems, and methods disclosed herein may cause an event trigger state machine associated with a programmable on-chip logic analyzer (POCLA) to transition to a programmable state at a programmable number of occurrences of a programmable set of events associated with a first subset of signals on a first subset of input signal paths. States associated with a second subset of signals on a second subset of input signal paths may be stored at a time relative to a transition to the programmable state if a set of storage criteria have been met. Additional embodiments are disclosed and claimed.

Abstract: A method and apparatus are provided to support autonomic computing for system configuration. Common base events (CBEs) are generated and, based upon system configuration, are employed to monitor system resources and to resolve system configuration conflicts prior to an error. A symptom database stores a set of rules for the configuration information. The configurations CBEs for the system configuration are compared with the symptom rules, and any discrepancies between the two elements are communicated to a user prior to an occurrence of an error in the system. Accordingly, an autonomic computer system is provided to support system configuration data.

Abstract: A testing method for testing a touch control device is disclosed. In a controller of the touch control device, a processor executes an operating firmware to realize a touch control function. The testing method includes a host testing device outputting a test requirement command to the controller, the controller outputting data corresponding to an operating stage selected from a plurality of operating stages of executing the operating firmware to the host testing device according to the test requirement command, and the host testing device determining an operating status of the touch device according to data provided by the touch control device.

Abstract: A method for testing at least two arithmetic units installed in a control unit includes: loading of first test data for testing a first arithmetic unit; saving the loaded first test data in a second memory unit of a second arithmetic unit; switching the first arithmetic unit to a test mode, in which a first scan chain of the first arithmetic unit is accessible; reading the first test data from the second memory unit; shifting the first test data which have been read through the first scan chain of the first arithmetic unit switched to the test mode for providing test result data for the first arithmetic unit; checking the provided test result data for plausibility for providing a test result for the first arithmetic unit.

Abstract: Results of field testing of portions of a distributed system such as a Broadband Communications System from a testing device to a controller which downloads programmed test protocols and sequences thereof to the separate testing device over a wired or wireless link and thereafter can be used to control the testing device as well as display test results and provide analysis of the test results and suggest procedures to technical personnel. The controller then can transmit the test data to a central facility or distribution hub in substantially real-time together with work performance data where full technical analysis can be performed. The test data and results of analysis can then be distributed as desired such as to a management analysis facility to support improvement of efficiency of the system and the operation thereof.

Abstract: A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.

Abstract: A test system and a test method thereof. The test system includes an electronic device and a test device. The electronic device includes a plurality of output interfaces and provides a corresponding test signal via the output interfaces according to a group of operation commands. The test device includes a transforming unit, a multiplexer unit, a processor unit and a plurality of test interfaces which are respectively coupled to the output interfaces. The transforming unit transforms the test signals received via the test interfaces. The multiplexer unit selects the transformed test signals. The processor unit controls the multiplexer unit to select one of the transformed test signals, and determines whether the transformed test signal being selected conforms a predetermine condition for generating a test result signal. The processor unit controls the communication unit to transmit the test result signal to the electronic device according to the test result signal.

Abstract: A debug device of embedded systems is provided. The embedded system includes an embedded processor for reading a bootloader from a flash memory through a data flash interface. The debug device includes a memory transmission interface, a dada storage module, a data control module and a display module. The memory transmission interface is configured to couple the data flash interface for receiving data to the data storage module. The data control module determines whether the data stored in the data storage module is data from a data bus or from the data flash interface according to whether a data control signal of the data flash interface has been triggered. The display module displays the data of the data storage module.

Abstract: An apparatus comprising a processor and an internal memory. The processor may be configured to test an external memory using (i) a netlist and (ii) a testing program. The internal memory may be configured to store the testing program. The testing program may be downloadable to the internal memory independently from the storing of the netlist.

Abstract: A monitoring side core has an input protection part including an access checking part and an address information storage part. Address information of a count RAM area and an access prohibiting mode to the address are stored in the address information storage part in advance by CPU. The access checking part determines whether an address to be accessed through a first communication path by a monitored side core and an access mode are coincident with the stored address and the stored access prohibiting mode. When the coincidence is determined, the access of the monitored side core to the count RAM area of the monitoring side core is prohibited.

Abstract: A complex user-facing computer application often has run-time dependencies on other computer applications. The other computer applications may, in turn, have run-time dependencies on still other applications. A supporting application might run on multiple hosts and a particular host might be chosen by a higher-level application in order to meet requirements such load balancing or reliability. In order to facilitate intelligent choices by higher-level applications in the system, each server in the system is responsible for generating a performance capability or health score that reflects the health of local components and the health of all servers on which the given server has a direct run-time dependency. A particular server's generated health score is advertised to any other server that has a direct run-time dependency on the particular server. Decisions about which of alternative lower-level servers to use in a servicing a client request are made using a routing or hop-at-a-time approach.

Abstract: Methods and systems are provided for detecting temporal relationships that are uniquely associated with a selected root cause. The method comprises identifying error codes associated with a root cause, wherein each error code comprises a plurality of event indicators and temporal data describing when the event indicator was generated, analyzing each of the error codes to detect a combination of event indicators that is associated with error codes corresponding to the selected root cause and to a non-selected root cause, and detecting a temporal relationship involving the combination of event indicators, wherein the temporal relationship is uniquely associated with error codes corresponding to the selected root cause.

Abstract: For a control apparatus to be boundary scan testable even when running, including processor cores in an operator to be capable of self-repairing a troubling part, an operator (2) has processor cores (2a, 2b) connected to a boundary scan bus (12), and adapted to mutually diagnose opponent processor cores for troubles, by boundary scan testing each other in a time-dividing manner.

Abstract: A method uses an integrated circuit having a debug status register. The integrated circuit is for being debugged by a hardware debugger external to the integrated circuit and has a processing unit for executing debug software. The debug status register is coupled to the processing unit and is for being coupled to the hardware debugger. The method includes updating the debug status register with hardware status flags arising from running the hardware debugger and software status flags arising from running the debug software. The method further includes masking locations in the debug status register where the hardware status flags are located from being read by the debug software while allowing the hardware status flags and the software status flags to be read by the hardware debugger. This is particularly useful in using the hardware debugger in debugging the debug software.

Abstract: A method includes providing an integrated circuit having a plurality of debug resources. The debug resources are usable exclusively for debug operations. The debug operations include operations directed by debug software executed by the integrated circuit and operations directed by external debug hardware which is external to the integrated circuit. The method further includes enabling availability of a first portion of the debug resources for use by the debug software, where a second portion of the debug resources are committed for exclusive use by the external debug hardware. The first portion is exclusive of the second portion. The method includes performing operations directed by the debug software using at least one debug resource of the first portion of the debug resources and operations directed by the external debug hardware using at least one debug resource of the second portion of the debug resources.

Abstract: A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

Abstract: In particular embodiments, a monitoring processor may receive an interrupt from status monitoring logic associated with a monitored processor that has experienced an error. Interrupt logic at the monitoring processor may interrupt the monitored processor to initiate a standby mode of operation in the monitored processor. Core dump logic at the monitoring processor may retrieve a core dump from a memory associated with the monitored processor via a communication channel connecting the monitoring processor to the monitored processor or to the memory. Other embodiments are disclosed and claimed.

Abstract: A method and system comprises creating a test case that is dependent upon known sequences and executing the test case on an originating processor until it reaches a known point. The method further includes executing the test case on a different processor to perform an action and informing the originating processor that the action was taken. The action is verified as being occurred with the originating processor.

Abstract: In one embodiment, a quantum detector is provided to detect a vulnerability measure for a processor based on a processor metrics each associated with operation of a processor structure during a quantum, along with a controller to control an error mitigation unit based on the vulnerability measure. Other embodiments are described and claimed.

Abstract: A fault location estimation system includes single-fault-assumed diagnostic unit nodes; error-observation node basis candidate classification unit; inclusion fault candidate group selection unit; inter-pattern overlapping unit; and multiple-fault simulation checking unit.

Abstract: It is possible to suppress a CPU showing signs of unstable operation before the OS starts. A micro program acquires error CPU information (which cannot be recognized directly by the micro program) from the service processor immediately before the termination of the micro program and making a request for suppression of the CPU showing signs of unstable operation according to the acquired error CPU information. The service processor suppresses the CPU showing signs of unstable operation before the OS starts.

Abstract: A diagnostic and service logic program for a programmable logic controller (PLC) is provided in parallel with the main machine logic program. The diagnostic and service logic program has the same functionality as the main machine logic program, but can be modified and operated independently of the main machine logic program for testing and debugging a faulty main machine logic program. The PLC can be switched between programs for testing and debugging.

Abstract: A system and method for performing circuit simulation is described. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked. Mechanisms are provided that allow for viewing, measurement or other manipulation of signals at specific locations in a circuit design for simulation, such as parameters that include observation points which are implemented using probes. One approach to executing a measurement is via a controllable and flexible control statement, which in one embodiment is the “run” statement. Improved interfaces for viewing, controlling, and manipulating simulations and simulation results are also provided.

Abstract: Disclosed is a design structure for an apparatus for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structure that links the functional debug logic elements. Each functional debug logic element is specifically dedicated to a function of its corresponding core, wherein the functional debug logic elements generate a table of function-specific system events. The system events are function-specific with respect to an associated core, wherein the system events include transaction events, controller events, processor events, interconnect structure arbiter events, interconnect interface core events, high speed serial link core events, and/or codec events.

Abstract: The present invention is a smart card device that can be debugged and software developed using at least one interrupt endpoint without adding an additional port. At least one memory stores a debug monitor program and instructions for completing smart card transactions. An interface is defined by a plurality of communication pipes and respective endpoints, including at least one interrupt endpoint. A microprocessor is operatively connected to the interface and memory and configures the interrupt endpoint as a debug port for debugging and software development using the debug monitor program.

Abstract: An electronic system comprises a processor, a diagnostic port, and a switching circuit, including a switch connected between the diagnostic port and the processor, for enabling and disabling the diagnostic port and for restricting access to contents of the electronic system prior to enabling the diagnostic port. A method for operating the electronic system is also included.

Abstract: A processor and memory system includes memory, a table of exceptions, and a processor. The memory includes a plurality of memory blocks. The table of exceptions identifies at least one of the plurality of memory blocks that includes an expected error. The processor diagnoses a security fault based on data stored in at least one of the plurality of memory blocks and the table of exceptions.

Abstract: A test system includes a debugging system and a system under test (SUT). The debugging system includes a debugging processor that couples to an SUT processor in the SUT via a memory mapping interface bus therebetween. In one embodiment, the debugging processor operates as a master to conduct test operations on the SUT via the memory mapping interface bus. The debugging processor and the SUT processor operate together in a cluster mode to provide non-invasive debugging of the (SUT) while the SUT executes application software in a real time environment.

Abstract: An apparatus and system are disclosed for performing a storage device maintenance operation. A management module receives a command through an interconnection module configured as a non-blocking switch. The management module performs a maintenance operation on a storage device through the interconnection module in response to the command. In addition, the management module may receive queries on the status of the maintenance operation through the interconnection module and report the status of the maintenance operation through the interconnection module.

Abstract: A computing machine comprises an electronic circuit operable to perform a function, a programmable integrated circuit such as an FPGA, and a processor. The processor is operable to detect a failure of the electronic circuit and to configure the programmable integrated circuit to perform the function of the electronic circuit in response to detecting the failure. Alternatively, the computing machine comprises a hardwired pipeline operable to perform a function and a processor operable to detect a failure of the pipeline and to perform the function in response to detecting the failure. By allowing a first type of circuit (e.g., an FPGA) to take over for a failed second type of circuit (e.g., a processor), such a computing machine can be fault-tolerant without having redundant versions of each component, and may thus be less expensive and smaller than computing machines of comparable computing power.

Abstract: A multi-function system comprising a plurality of peripherals having different levels of susceptibility to environmental events, at least one event detector configured to detect environmental events, a controller coupled to receive an event detected signal from the at least one event detector, a communication interface communicatively coupling the controller and each peripheral that includes an internal central processing unit, and a dedicated control interface communicatively coupling the controller and the plurality of peripherals. The controller is configured to control circumvention procedures of each peripheral via the dedicated control interface based on the detected event and the level of susceptibility of the peripheral.

Abstract: A testing device for testing a motherboard is provided to include a server, a client terminal computer, a debug card and a receiving device. The server is connected to the client terminal computer, for inquiring test results. The debug card is attached to the motherboard, for getting test data. The receiving device connecting with the debug card transmits the test data to the server via a network. A testing method for testing a motherboard is provided to include the following steps: a debug card getting the test data from the motherboard; sending the test data to a receiving device, the receiving device transmitting the test data to a server, the server collating and analyzing the test data; and a client terminal computer inquiring test results via the server.

Abstract: In a method for the controlled execution of a program (26), the program (26) being intended for a virtual machine (VM, VM?), on a portable data carrier, wherein the data carrier has a processor that executes at least a first and a second virtual machine (VM, VM?), the program (26) is executed both by the first and by the second virtual machine (VM, VM?). If, during execution of the program (26), a difference is found between the operating state of the first virtual machine (VM) and the operating state of the second virtual machine (VM?), execution of the program is aborted. A data carrier and a computer program product exhibit corresponding features. The invention provides a technique for the controlled execution of a program, which technique prevents security risks due to an attack or a malfunction of the data carrier.

Abstract: An apparatus is provided for performing testing of at least a portion of a system under test via a Test Access Port (TAP) configured to access the system under test. The apparatus includes a first processor for executing instructions adapted for controlling testing of at least a portion of the system under test via the TAP, and a second processor for supporting an interface to the TAP. The first processor is configured for detecting, during execution of the test instructions, TAP-related instructions associated with control of the TAP, and propagating the TAP-related instructions toward the second processor. The second processor is configured for receiving the TAP-related instructions detected by the first processor and processing the TAP-related instructions. The first processor is configured for performing at least one task contemporaneously with processing of the TAP-related instructions by the second processor. An associated method also is provided.

Abstract: A method, system and computer readable medium for on-chip testing is presented. In one embodiment, the method, system or computer readable medium includes identifying which LBIST channels of a plurality of LBIST channels do not contribute to a particular test and excluding from that particular test each LBIST channel that does not contribute to that particular test.

Abstract: Technologies disclosed herein can be used to diagnose defects on die having both scan chain and system logic defects, including in situations where the presence of one or more faults in the system logic potentially obscures the detectability of one or more faults in the scan chains (or channels) and vice versa. At least some embodiments employ an iterative approach where at least some scan chain faults are identified, these chain faults are used to identify system logic faults, and then additional chain faults are identified using the system logic faults and vice versa. Failing bits can be partitioned into at least two groups: failing bits determined as being caused by system logic failures, and failing bits determined as being possibly caused by chain defects, system logic defects, or the compound effects of both types of defects.

Abstract: A method includes retrieving a group test parameter determined based on test results associated with a plurality of integrated circuit devices. A particular integrated circuit device is tested using a test program and the group test parameter.

Abstract: A digital complex machine in accordance with the present invention is set so as to notify a manager of device information thereof by E-mail. It is also particularly set so as to convert device information into attached data and to transmit a device information mail containing the attached data to a server of the manager. In other words, since transmitting device information in the attached data format that is less possibly perceived by the third party, the digital complex machine is capable of suppressing leakage of device information.

Abstract: According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storage locations for the cache, a detector to measure a thermal environment of the processor, and circuitry to raise an operating voltage of the processor if the actual number of unreliable storage locations exceeds the acceptable number of unreliable storage locations, and if the thermal environment is acceptable.

Abstract: A system and method for self-test of an integrated circuit are disclosed. As one example, an integrated circuit is disclosed. The integrated circuit includes a digital signal processing chain, a random sequence generator coupled to an input of the digital signal processing chain, and a checksum calculator coupled to an output of the digital signal processing chain.

Abstract: The present invention offers an advanced control software verification technology, particularly, an assertion-based verification technology, by providing a control microcomputer verification device and vehicle-mounted control device that exhibit improved verification efficiency. Assertion-based verification is performed with a verification device that has a hardware configuration in which the verification device is independent of a CPU core of a microcomputer but operates in parallel with the CPU core of the microcomputer, which sequentially executes control software. The hardware to be employed to achieve the above purpose is a finite state machine based on microprogrammed control. An interrupt factor is branched immediately before an interrupt controller for the microcomputer and used as a transition input. When an abnormal transition is detected, a warning is output to the microcomputer as an interrupt or output to the outside in the form of a signal.

Abstract: Systems, methods, apparatus and software can be implemented to provide a debugger agent, either separate form or integrated into the script-based testing platform, to coordinate the selection, activation, and or/operation of debuggers suitable for a particular unit and program under test. Such a debugger agent can provide run time monitoring and debugging activities where previously not possible. The debugger agent is generally independent agent, in that it can work with a variety of types of test scripts, test script handlers, programming languages, and debuggers without customization. Moreover, implementation generally needs no code instrumentation.

Abstract: A programmable memory built-in self-test circuit and a clock switching circuit thereof are provided. The memory built-in self-test circuit is able to provide more self-test functions preset by a user, simplify the redundant circuit in the prior art and reduce chip area and lower the cost by means of an instruction decoder and a built-in self-test controller. The present invention also provides some peripheral control circuits of a memory. The control circuits occupies less area and enables the memory to be tested more flexibly. The present invention further provides a clock switching circuit enabling a chip to be correctly tested under different clock speeds, which benefits to advance the testability and the analyzability of the memory embedded in a chip and thereby increase fault coverage.

Abstract: A system on chip processor, that is, a semiconductor integrated circuit in which a processor, a cache memory and the like are integrated into one chip, includes a test controller, and a trace memory. The test controller generates test control signals in response to test flag signals generated from a processor. The trace memory stores a transmission data signal between the processor and a cache memory, a device under test, in response to the test control signals. Since the trace memory is provided within the integrated circuit, an operation of the device under test, which is configured in the integrated circuit, can be tested without disassembling the integrated circuit even after the integrated circuit is completely manufactured.

Abstract: A semiconductor testing device includes: a data memory which stores a test program, said test program generating a test command for testing a plurality of functions within one function area of a plurality of function areas of a semiconductor device, said test command being generated for said function area; a first area generation part which generates first data, said first data identifying one function area of said plurality of function areas, said plurality of functions of said one function area being tested; a main control part which generates said test command based on said test program and said first data and transmits said test command to said semiconductor device; a second area generation part which receives a first result, said first result being returned from said semiconductor device based on a first test in accordance with said test command and generates a second result based on said first result, said second result showing a pass or failure of said first test corresponding to said function area; an