Address Error Patents (Class 714/53)
  • Patent number: 10489241
    Abstract: A system and method for detecting writes of data to errant locations in storage arrays. Address information and information redundant with address information is encoded and stored in proximity with data. Upon reading the stored data, the corresponding address information is decoded and compared to the address of the intended read. A mismatch indicates a possible write to an errant location.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: November 26, 2019
    Assignee: ARTERIS, INC.
    Inventor: Xavier van Ruymbeke
  • Patent number: 10372902
    Abstract: One embodiment provides an accelerator circuitry. The accelerator circuitry includes accelerator processor circuitry; accelerator memory circuitry; processor trace (PT) decoder circuitry and control flow integrity (CFI) checker circuitry. The PT decoder circuitry is to at least one of receive and/or retrieve PT data from a host device. The PT decoder circuitry is further to extract a target instruction pointer (TIP) packet from the PT data and to decode the TIP packet to yield a runtime target address. The CFI checker circuitry is to determine, at runtime, whether a control flow transfer of an indirect branch instruction to the runtime target address corresponds to a control flow violation based, at least in part, on control flow (CF) information (info) stored to an accelerator CF info store.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Salmin Sultana, Ravi L. Sahita
  • Patent number: 10134487
    Abstract: A memory device may include a memory cell array, a bloom-filter circuit, a cache memory circuit, and a selecting circuit. The bloom-filter circuit may be configured to output a determination result signal that indicates that there is a possibility that a received address is one of failed addresses corresponding to failed cells of the memory cell array. The cache memory circuit may be configured to, store the failed addresses and a first set of data corresponding to the respective failed addresses, and configured to, when the determination result signal indicates a possibility, provide a comparison result signal by determining whether received address coincides with one of the failed addresses. The selecting circuit may be configured to output either first data of the first set of data or second data of the memory cell array corresponding to the received address based on determination result signal and comparison result signal.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: November 20, 2018
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SNU R&DB FOUNDATION
    Inventors: Sang-Hyuk Kwon, Young-Hoon Son, Jung-Ho Ahn
  • Patent number: 9870283
    Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: January 16, 2018
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Craig E. Hampel
  • Patent number: 9811429
    Abstract: The present invention provides a microcontroller which can continue operation even at the time of a failure without making a memory redundant to suppress increase in chip area. The microcontroller includes three or more processors executing the same process in parallel and a storage device. The storage device includes a memory mat having a storage region which is not redundant, an address selection part, a data output part, and a failure recovery part. The address selection part selects a storage region in the memory mat on the basis of three or more addresses issued at the time of an access by the processors. The data output part reads data from the storage region in the memory mat selected by the address selection part. The failure recovery part corrects or masks a failure of predetermined number or less which occurs in the memory mat, the address selection part, and the data output part.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: November 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyasu Kanekawa, Hitoshi Arimitsu, Takashi Yasumasu, Hideki Matsuyama
  • Patent number: 9645926
    Abstract: It is provided a storage system, comprising a storage device for storing data and at least one controller for controlling reading/writing of the data from/to the storage device. The at least one controller each includes a first cache memory for temporarily storing the data read from the storage device by file access, and a second cache memory for temporarily storing the data to be read/written from/to the storage device by block access. The processor reads the requested data from the storage device in the case where data requested by a file read request received from a host computer is not stored in the first cache memory, stores the data read from the storage device in the first cache memory without storing the data in the second cache memory, and transfers the data stored in the first cache memory to the host computer that has issued the file read request.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: May 9, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Takada, Akira Yamamoto, Hiroshi Hirayama
  • Patent number: 9570194
    Abstract: A fuse test mode detection device is disclosed, which relates to a technology for improving detection efficiency of a fuse test mode. The fuse test mode detection device includes: a fuse unit configured to scan a plurality of fuses in a boot-up operation, and output fuse data; a counter configured to count the fuse data in response to a clock signal; a decoding unit configured to output a decoding signal for controlling a fuse test mode in response to an output signal of the counter; an encoder configured to encode the output signal of the decoding unit, and output a code signal; and a comparator configured to compare the fuse data with the code signal, and output a comparison signal.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: February 14, 2017
    Assignee: SK HYNIX INC.
    Inventor: Hong Ki Moon
  • Patent number: 9543043
    Abstract: A method for testing an array fuse block of a semiconductor apparatus may include a series of operations for testing an array fuse block of the semiconductor apparatus as a test program is executed. The series operations may include the following steps: generating a test source file containing information for accessing the array fuse block; generating a test vector using the test source file; extracting repair confirmation information by performing a simulation using the test vector; extracting a repair confirmation information expected value from the test source file; and determining a pass or fail by comparing the repair confirmation information to the repair confirmation information expected value.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: January 10, 2017
    Assignee: SK HYNIX INC.
    Inventor: Jae Seok Kang
  • Patent number: 9460811
    Abstract: A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: October 4, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: George M. Braceras, Albert M. Chu, Kevin W. Gorman, Michael R. Ouellette, Ronald A. Piro, Daryl M. Seitzer, Rohit Shetty, Thomas W. Wyckoff
  • Patent number: 9384123
    Abstract: According to one embodiment, a memory system includes a non-volatile memory, a resource managing unit that reclaims resources associated with the non-volatile memory and increases the resources, when the usage of the resources associated with the non-volatile memory reaches the predetermined amount, a transmission rate setting unit that calculates a setting value of the transmission rate to receive the write data from a host device, and a transmission control unit that receives the write data from the host device and transmits the received write data to the non-volatile memory. The transmission rate setting unit calculates a small setting value when the usage of the resources associated with the non-volatile memory increases. The transmission control unit executes the reception of the write data from the host device at the transmission rate of the setting value, while the resource managing unit reclaims the resources.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: July 5, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshikatsu Hida, Hiroshi Yao, Norikazu Yoshida
  • Patent number: 9329926
    Abstract: A data integrity (DI) protection circuit and method provide overlapping DI protection without increasing memory requirements. Write data parity is checked after write data error correcting code (ECC) check bits are generated, which is stored with the write data in memory without storing the write data parity. A corrupt location cache stores the write address and a write response error is generated when a write data parity error or write address parity error is detected. Read data and read data ECC check bits retrieved from the memory are checked and single bit errors are corrected, while double-bit errors result in a read error response. Read data parity is generated, and the corrected read data and corrected read data ECC check bits are then checked for bit errors. The corrupt location cache is searched for the read address, and a cache hit results in a read error response.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: May 3, 2016
    Assignee: Microsemi Storage Solutions (U.S.), INC.
    Inventors: David Joseph Clinton, Larrie Simon Carr, Manthiramoorthy Ponmanikandan
  • Patent number: 9323608
    Abstract: A method for improving data bus integrity includes a selectable data bus integrity feature that can improve the integrity of a data bus in a memory system. An external controller generates error correction data in response to associated data to be transmitted. The error correction data is divided into multiple data packets and appended to the corresponding data for transmission over the data bus. The memory device can use the ECC data, if the feature is enabled, to attempt to correct the corresponding data and store both the corrected data and the ECC data.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: April 26, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Alberto Troia
  • Patent number: 9306916
    Abstract: A method and a system embodying the method for receiving a remote direct memory access packet comprising an opaque data, a virtual address, and a payload at a virtual network interface card that generated the opaque data; reconstructing a stream identifier by separating the opaque data into an encrypted stream identifier and a first digest; decrypting the encrypted stream identifier; verifying the decrypted stream identifier using the first digest; providing the verified stream identifier to a system memory management unit; and mapping the virtual address and the provided stream identifier by the system memory management unit to a physical address, is disclosed.
    Type: Grant
    Filed: December 25, 2013
    Date of Patent: April 5, 2016
    Assignee: CAVIUM, INC.
    Inventor: Wilson Parkhurst Snyder, II
  • Patent number: 9274946
    Abstract: A computer-implemented method of detecting memory that may be reclaimed from application data objects that are no longer in use. When at least a first virtual memory region is newly committed for heap block storage, a pre-leak detection scan of other virtual memory regions can be performed to identify at least one non-pointer data item in the other virtual memory regions, the non-pointer data item comprising data that corresponds to an address of a memory location within the first virtual memory region, but that is not a memory pointer. A leak detection scan can be performed to identify potential memory pointers, wherein the identified non-pointer data item is excluded from the identified potential memory pointers. A list of leaked heap blocks can be output. Each leaked heap block can exclusively comprise memory locations that do not have a corresponding potential memory pointer.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: March 1, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kirk J. Krauss
  • Patent number: 9170875
    Abstract: A method is described for monitoring a data memory in which an error detection method is used to detect and/or correct incorrect data words stored in memory lines of the data memory, an address of the data memory at which a data word evaluated as incorrect by the error detection method is stored being written to an auxiliary memory and being made available to a checking program.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: October 27, 2015
    Assignee: ROBERT BOSCH GMBH
    Inventors: Bernd Mueller, Carsten Gebauer, Dieter Thoss
  • Patent number: 8977944
    Abstract: In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: March 10, 2015
    Assignee: Cavium, Inc.
    Inventors: Aseem Maheshwari, Michael S. Bertone, Richard E. Kessler
  • Publication number: 20150058683
    Abstract: A first page in a memory unit is programmed with one or more pages of the secondary memory. A first time corresponding to the start of the programming of the first page is recorded. A second time corresponding to the completion of the programming of the one or more pages is recorded. A time difference between the first time and the second time is determined. It is determined if the time difference is greater than a threshold. In response to the time difference being greater than the threshold, a retention based defecting process is for the memory unit is disabled.
    Type: Application
    Filed: August 20, 2013
    Publication date: February 26, 2015
    Applicant: Seagate Technology LLC
    Inventors: Sumanth Jannyavula Venkata, Young-Pil Kim
  • Publication number: 20140351660
    Abstract: Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.
    Type: Application
    Filed: December 13, 2013
    Publication date: November 27, 2014
    Inventors: Eric J. DAHLEN, Glenn J. Hinton, Raj K. Ramanujan
  • Patent number: 8898417
    Abstract: Described herein are methods for accessing a block-based storage device having a memory-mapped interface and a block interface. In one embodiment, an apparatus (e.g., block-based storage device) includes a storage array to store data and a memory-mapped interface that is coupled to the storage array. The memory-mapped interface includes memory-mapped memory space. The memory-mapped interface receives direct access requests from a host to directly access memory-mapped files. The apparatus also includes a block interface that is coupled to the storage array. The block interface receives block requests from a storage driver to access the storage array.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: November 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Sam Post, Jared Hulbert, Stephen Bowers, Mark Leinwander
  • Publication number: 20140331095
    Abstract: This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the channel and configuring the set of field effect transistors to couple the channel with the sub-channel. In the example embodiment, data may be allowed to flow between the memory controller and the location in the memory over the channel and the sub-channel.
    Type: Application
    Filed: July 21, 2014
    Publication date: November 6, 2014
    Inventors: Mario Mazzola, Satyanarayana Nishtala, Luca Cafiero, Philip Manela
  • Patent number: 8793540
    Abstract: Provided is a test apparatus including: an address generator that generates an address of a memory under test; a selector that selects whether to perform bit inversion on the address generated by the address generator before supplying the address to the memory under test; an inversion processing section that outputs the address generated by the address generator after performing bit inversion on the address if the selector has selected in the affirmative, and outputs the address generated by the address generator without performing any bit inversion on the address if the selector has selected in the negative; and a supply section that supplies, to the memory under test, the address having undergone inversion control outputted from the inversion processing section and an inversion cycle signal that indicates whether the address outputted from the inversion processing section is bit inverted or not.
    Type: Grant
    Filed: July 4, 2012
    Date of Patent: July 29, 2014
    Assignee: Advantest Corporation
    Inventor: Takeshi Kawakami
  • Patent number: 8775903
    Abstract: A method is provided for recovering from an uncorrected memory error located at a memory address as identified by a memory device. A stored hash value for a memory page corresponding to the identified memory address is used to determine the correct data. Because the memory device specifies the location of the corrupted data, and the size of the window where the corruption occurred, the stored hash can be used to verify memory page reconstruction. With the known good part of the data in hand, the hashes of the pages using possible values in place of the corrupted data are calculated. It is expected that there will be a match between the previously stored hash and one of the computed hashes. As long as there is one and only one match, then that value, used in the place of the corrupted data, is the correct value. The corrupt data, once replaced, allows operation of the memory device to continue without needing to interrupt or otherwise affect a system's operation.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: July 8, 2014
    Assignee: VMware, Inc.
    Inventors: Carl A. Waldspurger, Dilpreet Bindra, Gregory T. Harmon, Patrick Tullmann
  • Publication number: 20140149808
    Abstract: In one example embodiment, a memory device includes a cell array configured to receive data at an associated address in response to a write command. The memory device further includes a storage unit configured to receive the associated address and the data in response to the write command and output the data to the associated address of the cell array in response to a rewrite command. The memory device further includes a violation determining unit configured to determine violation data, count a number of the violation data and determine data written to the storage unit as the violation data if a storage duration of the written data is less than a write recovery time (tWR).
    Type: Application
    Filed: October 16, 2013
    Publication date: May 29, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong-Young SEO, Chul-Woo PARK
  • Patent number: 8738974
    Abstract: The memory controller writes and reads data in and from a nonvolatile memory. The nonvolatile memory has a plurality of memory cell blocks, each memory cell block includes a plurality of multi-level cells each capable of storing m-bit data (m is a natural number of two or more), a first page to a m-th page are allocated to the respective m bits of the multi-level cell, the memory controller sequentially writes the data to the memory cells from the first page in ascending order, and comprises a backup unit, and when a write command is received from the outside of the memory controller, in a case where a data write destination of the data in the nonvolatile memory is a n-th (n is a natural number of two to m) page of the multi-level cell, and data is already written in the first to (n-1)th pages, the backup unit copies the already written data to a nonvolatile storable backup region.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: May 27, 2014
    Assignee: Panasonic Corporation
    Inventor: Toshiyuki Honda
  • Patent number: 8711417
    Abstract: An information processing apparatus, which includes a storage unit having a plurality of data areas, includes a measurement unit configured to measure a first data access speed in a first data area of the storage unit and a second data access speed in a second data area of the storage unit, and a detection unit configured to detect a defect at the first data area based on difference between the first data access speed and the second data access speed.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: April 29, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Manabu Hada
  • Publication number: 20140082433
    Abstract: A method is disclosed for retrieving the reservation status information of a storage area network (SAN) device, a host transmits a persistent reservation in command with service action setting of ‘read reservation’ to a first LUN, wherein the host is connected to a port of the data storage server to which the LUN belongs. The host receives a message from the LUN. The host determines that the message is a success. The host sends to the LUN a persistent reservation in command with service action setting of ‘read keys’, responsive to a success message. The host determines that the LUN responds with a zero data length. The host determines the LUN is reserved with type 2 reservation, responsive to a determination that the LUN responds with a non-zero data length.
    Type: Application
    Filed: November 20, 2013
    Publication date: March 20, 2014
    Applicant: International Business Machines Corporation
    Inventors: Kiran K. Anumalasetty, Nicholas S. Ham, Purna Chandra Jasti, Sudhir Maddali, Yadagiri Rajaboina, Sanket Rathi
  • Patent number: 8655637
    Abstract: An memory access address comparator includes two comparators comparing an input memory access address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as address size, full or partial overlap, greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit memory access address bus selection. The comparator output may be selectively dependent upon corresponding data matches. The reference addresses, comparison data and control functions are enabled via central processing unit accessible memory mapped registers.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: February 18, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Jose L. Flores, Lewis Nardini, Maria B. H. Gill
  • Patent number: 8572441
    Abstract: Systems and methods for maximizing a number of available states for a version number used for memory corruption detection. A physical memory may be a DRAM comprising a plurality of regions. Version numbers associated with data structures allocated in the physical memory may be generated so that version numbers of adjacent data structures in a virtual address space are different. A reserved set and an available set of version numbers are associated with each one of the plurality of regions. A version number in a reserved set of a given region may be in an available set of another region. The processor detects no memory corruption error in response to at least determining a version number stored in a memory location in a first region identified by a memory access operation is also in a reserved set associated with the first region.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: October 29, 2013
    Assignee: Oracle International Corporation
    Inventors: Darryl J. Gove, Zoran Radovic, Jonathan Adams
  • Patent number: 8564466
    Abstract: To increase the number of analog inputs at low cost, an analog input system includes: one or more analog slave units each connected to a bus to which a CPU unit is connected, and each including an A/D-conversion device converting an analog value outputted by an external device into a first digital value, a buffer memory buffering a second digital value to be transferred to the CPU unit, and a nonvolatile storage device containing specific information of its own unit; and an analog master unit connected to the bus and including an operation section performing operation processing based on the specific information stored in the storage device with the first digital value being used as an input, to calculate the second digital value, the master unit performing on each of the slave input units the operation processing and processing of transferring the calculated second digital value to the buffer memory.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: October 22, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masaru Hoshikawa, Shigeaki Takase
  • Patent number: 8566685
    Abstract: A command control circuit includes a command decoder configured to decode a command and generate an internal command, an error check unit configured to detect an error in the command and an address by using check data and generate an error check signal in response to the detection, and a blocking unit configured to block or pass the internal command in response to first and second states of the error check signal.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: October 22, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Choung-Ki Song
  • Patent number: 8555116
    Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: October 8, 2013
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Craig E. Hampel
  • Patent number: 8458532
    Abstract: A data processing system 2 is provided with multiple processor cores 4, 6, 8, 10 each incorporating a data cache memory 12, 14, 16, 18. A snoop control unit 20 manages coherency between the data values stored within the data caches 12, 14, 16, 18. The snoop control unit 20 incorporates a TAG memory 22. If an error is detected within an entry of the TAG memory 22, then a hit operation is forced to the corresponding storage location one or more of the data caches 12, 14, 16, 18.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: June 4, 2013
    Assignee: ARM Limited
    Inventors: Jocelyn Francois Orion Jaubert, Florent Begon, Melanie Emanuelle Lucie Teyssier
  • Patent number: 8447949
    Abstract: One or more registers used to form an address usable in accessing storage are examined to determine if a zero address event has occurred in forming the address. In response to an indication that a zero address event has occurred in address formation, an alert is provided to the program using the address to access storage.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Robert M. Abrams, Mark S. Farrell, Dan F. Greiner, Christian Jacobi, James H. Mulder, Peter J. Relson, Timothy J. Slegel, Peter K. Szwed
  • Patent number: 8443261
    Abstract: A method is provided for recovering from an uncorrected memory error located at a memory address as identified by a memory device. A stored hash value for a memory page corresponding to the identified memory address is used to determine the correct data. Because the memory device specifies the location of the corrupted data, and the size of the window where the corruption occurred, the stored hash can be used to verify memory page reconstruction. With the known good part of the data in hand, the hashes of the pages using possible values in place of the corrupted data are calculated. It is expected that there will be a match between the previously stored hash and one of the computed hashes. As long as there is one and only one match, then that value, used in the place of the corrupted data, is the correct value. The corrupt data, once replaced, allows operation of the memory device to continue without needing to interrupt or otherwise affect a system's operation.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: May 14, 2013
    Assignee: VMware, Inc.
    Inventors: Carl A. Waldspurger, Dilpreet Bindra, Gregory Harm, Patrick Tullmann
  • Patent number: 8423686
    Abstract: A method and a device for the detection of erroneous or inopportune transactions of any entity of a microprocessor or microcontroller includes programming counters internal or external to the microcontroller, which is configured to count the number of transactions in the target area of the target interface of the microcontroller; count the total number of transactions on the target interface, and verify that the number of transactions outside of the target area of the target interface of the microcontroller is zero. Equality between the number of transactions in the target area of the target interface and the total number of transactions on the target interface of the microcontroller is verified.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: April 16, 2013
    Assignee: Thales
    Inventors: Sébastien Camand, Tarik Aegerter
  • Patent number: 8392798
    Abstract: An apparatus, system, and method are disclosed for validating that correct data is read from a storage device. A hash generation module generates a hash value from a logical address of a read request for a data storage device. A read data module reads, from the data storage device, data identified by the read request and a stored hash value stored with the data. The stored hash value was generated from a logical address for data written to the data storage device. A hash check module verifies that the generated hash value matches the stored hash value read from the data storage device.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: March 5, 2013
    Assignee: Fusion-IO, Inc.
    Inventors: David Flynn, Jonathan Thatcher, John Strasser
  • Patent number: 8381023
    Abstract: A memory system according to the present invention includes, in addition to an computing device, a plurality of first blocks that are provided to store information including user information, and first physical addresses not overlapping one another are assigned to, respectively, and a plurality of second blocks that are provided to store first physical addresses of initial defect blocks out of the plurality of first blocks, respectively, wherein the computing device finds the first physical address corresponding a inputted given logical address, based on a given mirror logical address corresponding to the given logical address, and information stored in the second blocks.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: February 19, 2013
    Assignee: MegaChips Corporation
    Inventor: Shinji Tanaka
  • Patent number: 8352805
    Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: January 8, 2013
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Craig E. Hampel
  • Patent number: 8352439
    Abstract: A method for processing a write instruction for writing data to a database stored on a logical device includes obtaining first and second addresses that specify the location of the data in respective first and second address spaces. A third address corresponding to an expected location of the data record in the first address space is then calculated. On the basis of a comparison between the first address and the third address, a determination is made as to whether to execute the write instruction.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: January 8, 2013
    Assignee: EMC Corporation
    Inventors: Terry Seto Lee, Arieh Don, Xiali He, Philip E. Tamer, Alexandr Veprinsky
  • Patent number: 8347150
    Abstract: A semiconductor memory and a data processing system having hardware for carrying out a method for the improved internal monitoring of addressing circuits in semiconductor memories or in a data processing system, in which logic levels addressing lines are tapped off, the actually selected address or subaddress is represented by additional address bit lines, the actually accessed address/subaddress is recovered using the address bit lines, and the actually selected address/subaddress is compared with the applied address/subaddress, obtained from the additional address bit lines, in order to recognize an error in the addressing circuit.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: January 1, 2013
    Assignee: Continental Teves AG & Co., oHG
    Inventors: Lukusa Didier Kabulepa, Houman Amjadi, Wolfgang Fey, Adrian Traskov
  • Patent number: 8312461
    Abstract: A system includes a virtualized I/O device coupled to one or more processing units. The virtualized I/O device includes a storage for storing a resource discovery table, and programmed I/O (PIO) configuration registers corresponding to hardware resources. A system processor may allocate the plurality of hardware resources to one or more functions, and to populate each entry of the resource discovery table for each function. The processing units may execute one or more processes. Given processing units may further execute OS instructions to allocate space for an I/O mapping of a PIO configuration space in a system memory, and to assign a function to a respective process. Processing units may execute a device driver instance associated with a given process to discover allocated resources by requesting access to the resource discovery table. The virtualized I/O device protects the resources by checking access requests against the resource discovery table.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: November 13, 2012
    Assignee: Oracle America, Inc.
    Inventor: John E. Watkins
  • Patent number: 8307270
    Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: November 6, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kyu-Hyoun Kim, George L. Chiu, Paul W. Coteus, Daniel M. Dreps, Kevin C. Gower, Hillery C. Hunter, Charles A. Kilmer, Warren E. Maule
  • Publication number: 20120278665
    Abstract: Detecting a fault in the operation of a computer having a processor and a memory is taught. Instrumentation code is placed within an application program during compilation, and runtime library routines are modified to support detection of invalid memory accesses. Memory space is divided into application, shadow and unmapped memories. When accessing application memory at an original address, an address in shadow memory is computed by shifting the address and adding an offset. If the value stored at the shadow address indicates that the original address is invalid (e.g., not allocated or already freed), then error reporting code is executed that indicates the type of error and the location and optionally halts the computer. Invalid memory references to heap, stack and global objects in application memory can be detected.
    Type: Application
    Filed: April 23, 2012
    Publication date: November 1, 2012
    Applicant: GOOGLE INC.
    Inventors: Konstantin Serebryany, Derek Bruening
  • Patent number: 8185717
    Abstract: A system includes a processor with a memory map specifying a user mode region with virtual address translation by a memory management unit and a kernel mode region with direct virtual address translation. The processor executes an application in the user mode region where virtual addresses are not unique. A probe receives trace information from the processor. A host system receives the trace information from the probe. The host system includes a data structure associating a process name, a process identification and a set of instruction counters. Each instruction counter is incremented upon the processing of a designated virtual address within the trace information. A profiling module processes information associated with the process name and set of instruction counters to identify a performance problem in the application.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: May 22, 2012
    Assignee: MIPS Technologies, Inc.
    Inventor: Bruce J. Ableidinger
  • Patent number: 8161353
    Abstract: An apparatus, system, and method are disclosed for validating that correct data is read from a storage device. A read request receiver module receives a read storage request to read a data segment of a file or object stored on a data storage device. The storage request includes one or more source parameters for the data segment. The source parameters include one or more virtual addresses that identify the data segment. A hash generation module generates one or more hash values from the virtual addresses. A read data module reads the requested data segment and returns one or more data packets and corresponding stored hash values stored with the data packets. The stored hash values were generated from a data segment written to the data storage device that contains data of the data packets. A hash check module verifies that the generated hash values match the respective stored hash values.
    Type: Grant
    Filed: April 6, 2008
    Date of Patent: April 17, 2012
    Assignee: Fusion-IO, Inc.
    Inventors: David Flynn, John Strasser, Jonathan Thatcher
  • Patent number: 8156385
    Abstract: Embodiments of the invention provide a table-free technique for detecting all temporal and spatial memory access errors in programs supporting general pointers. Embodiments of the invention provide such error checking using constant-time operations. Embodiments of the invention rely on fat pointers, whose size is contained within standard scalar sizes (up to two words) so that atomic hardware support for operations upon the pointers is obtained along with meaningful casts in-between pointers and other scalars. Optimized compilation of code becomes possible since the scalarized-for-free encoded pointers get register allocated and manipulated. Backward compatibility is enabled by the scalar pointer sizes, with automatic support provided for encoding and decoding of fat pointers in place for interaction with unprotected code.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: April 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: Pradeep Varma, Rudrapatna K. Shyamasundar, Harshit J. Shah
  • Patent number: 8122298
    Abstract: Methods and systems for capturing error information regarding a Serial Advanced Technology Attachment (SATA). An initiator device is enhanced in accordance with features and aspects hereof to detect an error condition in operation of the system and to transmit error information to the SATA target device during a soft reset condition applied to the SATA target device. The SATA target device discards all such frames received during the soft reset condition until the initiator device clears the soft reset condition. The error information may be captured for further analysis and debug of the error condition by suitable error analyzer equipment such as a SATA bus analyzer. The initiator device may be a SATA initiator or a Serial Attached SCSI (SAS) initiator using the SATA Tunneling Protocol (STP). Features and aspects hereof may also include a SAS/SATA bridge device coupling a SAS initiator to the SATA target device.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: February 21, 2012
    Assignee: LSI Corporation
    Inventor: Ross J. Stenfort
  • Patent number: 8108736
    Abstract: The present invention determines an incorrect packet from a faulty partition quickly and reliably and prevents the packet from flowing into normal partitions through simple control actions. The multi-partition computer system is a multi-partitioned computer system in which a plurality of nodes are logically divided into a plurality of partition, and each node contained in the partitions includes a packet identification unit which, upon receiving a packet, compares the partition identification information uniquely assigned to own partition against the partition identification information contained in the receive packet, and if these pieces of information do not match each other, judges and discards the receive packet as an incorrect packet.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: January 31, 2012
    Assignee: NEC Computertechno Ltd.
    Inventor: Shusaku Uchibori
  • Patent number: 8099636
    Abstract: A method is disclosed for detecting a memory stack fault. The method may include reserving a memory stack for executing software instructions. The method may also include enabling a debug unit and as the software instructions are execute, utilizing the debug unit to monitor a memory space adjacent to the memory stack. The method may further include identifying a memory stack fault if a write operation to the memory space is attempted.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: January 17, 2012
    Assignee: Caterpillar Inc.
    Inventors: Robert Eugene Tilton, Steven C. Bray, Mark Matthew Hoffman
  • Publication number: 20110296486
    Abstract: Apparatus, systems, and methods may operate to authenticate a desktop client to an identity service (IS), to receive a request, from an application, at the IS via the desktop client for a virtual service internet protocol (IP) address associated with a service. The IS may operate to build a routing token that includes an original physical IP address associated with the service when a policy associated with the IS permits access to the service by a user identity associated with the desktop client. After the routing token is validated, the application may be connected to the service via the desktop client. The application may comprise an e-mail application or a remote control application, such as a virtual network computing (VNC) application. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: May 26, 2010
    Publication date: December 1, 2011
    Inventors: Lloyd Leon Burch, Prakash Umasankar Mukkara, Douglas Garry Earl