Abstract: A data recovery apparatus and method used for a flash memory, which can recover data damaged or lost when power supplied to the flash memory is cut off while data operations are being consecutively performed on at least one data stored in the flash memory. The data recovery apparatus performs a data operation at each of a plurality of consecutive logical addresses, and if the data operations performed at the logical addresses are successful, records a mark value in a last index area of a plurality of consecutive index areas respectively corresponding to the consecutive logical addresses.

Abstract: Addressing error detection systems and methods are disclosed. A target address is written to a memory in an electronic system and subsequently output on an address path through which the memory is addressable. An addressing error is detected by determining whether the target address output on the address path is detected at the memory. Address detection at the memory involves storing the target address, monitoring the address path for the target address, and providing an address detection indication based on whether the target address is detected on the address path. The address detection indication may be provided, for example, by setting a flag in a data structure which is stored in the memory.

Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register.

Abstract: A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, one vector register is loaded with the “add-in” values, and another vector register is loaded with address values of “add to” elements to be gathered from memory into a third vector register. If the vector of address values has a plurality of elements that point to the same memory address, the algorithm should add all the “add in” values from elements corresponding to the elements having the duplicated addresses. An indirectly addressed load performs the “gather” operation to load the “add to” values. A vector add operation then adds corresponding elements from the “add in” vector to the “add to” vector. An indirectly addressed store then performs the “scatter” operation to store the results.

Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card provided with a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM, and a 28 bit 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register.

Abstract: This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, for storing in a second section thereof an extension to each instruction word in the first section. The computer program further includes computer program code for setting a state of at least one page table entry bit for indicating, on a code page by code page basis, whether the code page is partitioned into the first and second sections for storing instruction words and their extensions, or whether the code page is comprised instead of a single section storing only instruction words.

Abstract: A plurality of data packets encoded according to a first protocol are received which encapsulate data encoded according to a second protocol. A first source address is extracted from the packets according to the first protocol, it is determined whether or not the first source address is a substantial duplicate of a known assigned address. If it is a duplicate, a second source address is extracted from the encapsulated data according to the second protocol, and the first source address and said second source address are provided in an enhanced error log so that a system administrator may correct the duplicate assigned address. Enhanced embodiments of the invention included analysis of data encapsulated by a third, fourth and subsequent protocols, and automatic determination of each protocol encoding format.

Abstract: Techniques and apparatus are disclosed for detecting and responding to the malfunction of a host coupled to a communications bus through a bus transceiver.

Abstract: The present invention relates to a method and circuit arrangement for performing an error correction in a memory arrangement in which a redundancy system is used. The addresses of faulty cells are recorded redundantly by applying a corresponding coding. Then, an error correction is applied to the faulty-address information before it is compared to an externally applied address. Thereby, errors due to faulty redundancy addresses can be prevented.

Abstract: A system and method for increasing computing throughput through execution of parallel data error detection/correction and cache hit detection operations. In one path, hit detection occurs independent of and concurrent with error detection and correction operations, and reliance on hit detection in this path is based on the absence of storage errors. A single error correction code (ECC) is used to minimize storage requirements, and data hit comparisons based on the cached address and requested address are performed exclusive of ECC bits to minimize bit comparison requirements.

Abstract: An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit selection of either the program counter address bus or a secondary address bus. The reference addresses and control functions are enabled via central processing unit accessible memory mapped registers.

Abstract: When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is sent to a CPU, while the transaction is finished on the IO bus. To prevent a transaction between IO devices from gaining access to any resource in another logical partition, one access permission bit is provided for each combination of all the IO devices, and the access is permitted only when the bit has a predetermined value. A reset signal is provided by IO slot so that only an IO slot allocated to a specific logical partition can be reset without affecting any other logical partition. A transaction issued from an IO device in one logical partition is prevented from gaining access to a resource in another logical partition, while proper error handling can be performed.

Abstract: A method and associated system and electronic device for evaluating the reliability of a program (401) stored in a storage memory of an electronic device (1) having a processing memory (3b) for processing programs, wherein the program (401) is loaded into the processing memory (3b) for processing, wherein a first determining step determines data about the loading address of the program (401), a modification step searches for a program corresponding to the program (401) in the storage memory (4, 10), wherein if the searched program is found, the program code of the searched program is modified to correspond to the loading of the program in the loading address determined in the first determining step. An examining step examines the conformity of the program loaded in the processing memory and the modified program, wherein the result of the examining step is used in the evaluation of the reliability of the program (401) to be verified.

Abstract: A method of generating a file suitable for programming a programmable logic device. The method generally comprises the steps of (A) generating a programming item from a plurality of parameters that define a program for the programmable logic device, (B) storing the programming item in a programming field of the file in response to generating, and (C) storing at least one of the parameters in a non-programming field of the file.

Abstract: A method of generating a file suitable for programming a programmable logic device. The method generally comprises the steps of (A) generating a programming item from a plurality of parameters that define a program for the programmable logic device; (B) compressing the programming item to present a compressed item; (C) storing the programming item in a programming field of the file in response to generating; and (D) storing the compressed item in a non-programming field of the file in response to compressing.

Abstract: A method for reading data from an information recording medium having a plurality of address regions, includes the steps of: performing a reading operation for all of designated address regions among the plurality of address regions while holding read error information regarding the read error in the case where a read error occurs during reading of data from one of the plurality of address regions; transferring the read data to a data conversion device for converting the read data; and transferring the read error information to the data conversion device.

Abstract: The present invention relates to a storage device controller for controlling the operations of the data storage system. The controller includes error-correcting code (ECC) coding and decoding of data stored on media of the data storage system. A Verify procedure of the present invention is performed which verifies the validity of the data written to the media. The Verify procedure runs continuously until an error is detected or until an external event terminates the procedure. By accessing a range of memory addresses in the media and by resetting an address counter to a start of the range of addresses after a last address of the range has been accessed, the Verify procedure continuously checks the memory locations for errors. The range of addresses may include all of the accessible addresses in the data storage device. Additionally, information on the quality of the media may be collected and used to determine how much the media deteriorates over time.

Abstract: A method for verifying user memory validity which copes with faults generated in the Kernel area by returning an error value, even if the fault is generated by a user buffer address checking function declared as a safeguard function. The user memory verifies validity by simple memory reading/writing functions, thus increasing processing speed. Faults generated in the Kernel area can be processed using the safeguard function. The method can be applied in communication devices and to all OS (Operating System) in which the user address area is the same as the address area of the current process and all processes and tasks are performed on the same address area.

Abstract: A memory subsystem includes a memory controller coupled to a memory module including a plurality of memory chips via a memory bus. The memory controller may generate a plurality of memory requests each including address information and corresponding error detection information. The corresponding error detection information is dependent upon said address information. The memory module may receive each of the plurality of memory requests. An error detection circuit within the memory module may detect an error the address information based upon the corresponding error detection information and may provide an error indication in response to detecting the error.

Abstract: An electronic apparatus has in a CPU core an instruction correcting circuit that includes memory cells, a comparator and a selector. The memory cells store, when initializing the electronic apparatus, a correction address, a correction instruction and a correction enabling bit, which are associated with contents of a read-only memory. The comparator compares an instruction address output from an instruction prefetch stage of the CPU core with the correction address stored in the memory cells. The selector selects either an instruction code read from the instruction address of the read-only memory or the correction instruction stored in the memory cells in response to a compared result of the comparator. The electronic apparatus can correct the ROM data after manufacturing without reducing the number of available interrupts or the operation speed of the CPU.

Abstract: Method and apparatus for managing memory of a data processing system. In one embodiment, memory objects are allocated in response to memory allocation requests. Each object has an associated plurality of addresses. Type-identifier codes are respectively stored in association with the memory objects. Upon detection of a transient memory error at a memory address a recovery action is selected and performed based on the type-identifier code of the object that is associated with the erring memory address.

Abstract: A microprocessor, data processing system, and method are disclosed for handling parity errors in an address translation facility such as a TLB. The microprocessor includes a load/store unit configured to generate an effective address associated with a load/store instruction. An address translation unit adapted to translate the effective address to a real address using a translation lookaside buffer (TLB). The address translation unit includes a parity checker configured to verify the parity of the real address generated by the TLB and to signal the load store unit when the real address contains a parity error. The load store unit is configured to initiate a TLB parity error interrupt routine in response to the signal from the translation unit. In one embodiment, the TLB interrupt routine selectively invalidates the TLB entry that contained the parity error. The load/store unit preferably includes an effective to real address table (ERAT) containing a set of address translations.

Abstract: Memory accesses in a data processing device (14) can be monitored by selecting, from among a plurality of available memory relationships (37, 82), a memory relationship relative to an address of a reference memory location (B2). When a memory access address bears the selected memory relationship relative to the address, an event (24) can be declared.

Abstract: A simultaneous and redundantly threaded, pipelined processor executes the same set of instructions simultaneously as two separate threads to provide fault tolerance. One thread is processed ahead of the other thread so that the instructions in one thread are processed through the processor's pipeline ahead of the corresponding instructions from the other thread. The thread, whose instructions are processed earlier, places its committed stores in a store queue. Subsequently, the second thread places its committed stores in the store queue. A compare circuit periodically scans the store queue for matching store instructions. If otherwise matching store instructions differ in any way (address or data), then a fault has occurred in the processing and the compare circuits initiates fault recovery. If comparison of the two instructions reveals they are identical, the compare circuit allows only a single store instruction to pass to the data cache or the system main memory.

Abstract: Automatic detection or correction of addresses, such as Uniform Resource Locators, that are user-entered may be provided. A code that is associated with an address may be entered when an address is entered. Errors in the address may be detected and corrected based on the code. The code may be determined for an address based on the string of characters comprising that address. Reed-Solomon techniques, checksum determining techniques, or other such techniques may be used to determine a code of an address. A code may be inserted at the end of an address with a number of particular characters placed in between the code and the address to signal that a code is being used. The address, code, and code-distinguishing characters in between the code and the address may be entered by being typed in or scanned in.

Abstract: In a computer which translates instructions from a target instruction set to a host instruction set, a method for determining validity of a translation of a target instruction linked to an earlier translation including the steps of testing a memory address of a target instruction to be executed against a copy of the memory address of the target instruction from which a translation of the target instruction was made, executing the translation if the addresses compare, and generating an exception if the addresses do not compare.

Abstract: Each of a plurality of ROM correction units in a computer system includes a register for storing a subject address of an original instruction group having a bug, a comparator for comparing a current address against the subject address, a selector for selecting the current address or the branch address of a modified instruction group based on the result of the comparison by the comparator, and a flag generator for setting a correction flag when the selector selects the branch address. The computer system recognizes the order of the plurality of ROM correction units based on the correction flag. A plurality of bugs in a program can be modified by respective ROM correction units.

Abstract: A simultaneous and redundantly threaded, pipelined processor executes the same set of instructions simultaneously as two separate threads to provide fault tolerance. One thread is processed ahead of the other thread so that the instructions in one thread are processed through the processor's pipeline ahead of the corresponding instructions from the other thread. The thread, whose instructions are processed earlier, places its uncached reads in a read queue. Subsequently, the second thread places its uncached reads in the read queue. A compare circuit periodically scans the read queue for matching uncached read instructions. If otherwise matching instructions differ in their target address, then a fault has occurred in the processing and the compare circuits initiates fault recovery. If comparison of the two instructions reveals they are identical, the compare circuit allows only a single uncached read instruction to pass to the system main memory.

Abstract: Techniques and apparatus are disclosed for detecting and responding to the malfunction of a host coupled to a communications bus through a bus transceiver.

Abstract: A computerized method for automatically analyzing a core file created by a computer system after an unexpected interrupt. The packages installed on the computer system are determined and patch files of descriptive data for previously identified patches are accessed to create a patch search set including patches configured for use with the installed packages. Patches in the patch search set are scored by assigning points to each patch based on scoring rules, e.g., searching the patch descriptive data for matches between portions of the patch descriptive data and portions of the core file, including bug descriptions. For UNIX™-based kernel core files, the scoring rules involve creating search criteria based on panic types and on panic metric data gathered from the core file. A detailed patch search report is created providing recommendations for each of the scored patches based on the assigned score and identifying patches for installation.

Abstract: A computer system includes instruction fetch circuitry for dispatching fetched instructions to a pipelined execution unit, data memory access circuitry and emulator circuitry for use in debug operations, said emulator circuitry including error indicating circuitry to indicate an error in a data memory access operation, snoop circuitry for snooping memory access operation in said data memory access circuitry, synchronising means for synchronising snooped data memory access addresses with respective program counts for the instructions associated with said access addresses, memory mapped storage circuitry responsive to a data memory access error to indicate the data memory address associated with the error, whereby the emulator circuitry may use the data memory address in a subsequent operation to obtain from the synchronising means the specific program count associated with the memory access operation in which the error occurred.

Abstract: The present invention is related to methods and apparatus that can enhance the reliability of a hard drive by providing a built-in error check in the drive. Conventional hard drives can erroneously seek to an incorrect location on a platter of the hard drive. The erroneous seek corrupts the data stream and is difficult to detect and correct. Embodiments of the present invention can detect a logical block address assigned to a portion of the platter of the hard drive and thereby detect when an erroneous seek has occurred. Upon detection of an error, one embodiment of the present invention can further take corrective action to read from the correct portion of the platter.

Abstract: The present invention relates to a method and system for efficiently identifying errant processes in a computer system using an operating system (OS) error recovery method that identifies if the error caused by the errant process can be recovered and, if so, can recover from the error. The method and system of the present invention operates after standard Error Correcting Code (ECC) and parity check bit methods and systems are unsuccessful in recovering from the error In accordance with an embodiment of the present invention, the method and system includes detecting an error during instruction execution, storing a physical address of an errant process that caused the error, and storing an execution instruction pointer (IP) in an interruption instruction pointer (IIP).

Abstract: Memory about 4 Gbytes is tested using a DOS diagnostics program that remaps memory to a 32-bit addresses. In some embodiments, memory above 3 Gbytes is tested in 1 Gbyte blocks until the end of memory is reached using a physical address extension that extends addresses from 32 bits to 36 bits. Testing is done concurrently by all processors.

Abstract: An adapter program couples a legacy operating system to a driver program of an I/O channel which has an incompatible interface to a native operating system. The adapter program includes a translator which receives legacy control structures from the legacy operating system that represents a legacy I/O instruction. The adapter program also includes an interface to the driver program which simulates the native operating system interface. The adapter program further includes an emulator for performing the I/O instruction by interacting with the driver program thru the simulated native operating system interface.

Abstract: Disclosed is a method, system, program, and data structures for transferring data to a requesting application. A request is received for one or more blocks of data at contiguous addresses in a storage device. Each block of data includes customer data and metadata indicating the address of the block in the storage device and an error checking code that is capable of being used to determine whether the customer data in the block has changed. For each requested block, a determination is made as to whether the address of the block of data in the metadata and the requested address match. Further, for each requested block, an operation is performed on the customer data in the block and the error checking code to determine whether the customer data has changed. The requested block is transferred to the requesting application if the address of the block in the metadata and requested address match and the customer data has not changed.

Abstract: Multi-hit errors in a processor cache are detected by a multi-hit detection circuit coupled to the hit lines of the cache. The multi-hit detection circuit compares pairs of hit signals on the hit lines to determine if any two hit signals both indicate a hit. If multiple hits are detected, an error flag indicating the occurrence of multiple hits is generated.

Abstract: The present invention relates to a storage device controller for controlling the operations of the data storage system. The controller includes error-correcting code (ECC) coding and decoding of data stored on media of the data storage system. A Verify procedure of the present invention is performed which verifies the validity of the data written to the media. The Verify procedure runs continuously until an error is detected or until an external event terminates the procedure. By accessing a range of memory addresses in the media and by resetting an address counter to a start of the range of addresses after a last address of the range has been accessed, the Verify procedure continuously checks the memory locations for errors. The range of addresses may include all of the accessible addresses in the data storage device. Additionally, information on the quality of the media may be collected and used to determine how much the media deteriorates over time.

Abstract: A mechanism for implementing fault tolerant logic in an information storage system is disclosed. The mechanism comprises an inhibit logic which is invoked when the first RUNOUT block of a link sequence is detected. Once invoked, the inhibit logic outputs a disable signal, and so long as the disable signal is asserted, certain control signals are inhibited. These control signals may include a trigger signal, a target match signal, and a miss signal. The disable signal is maintained during the reading of blocks, such as link sequence blocks, in which information corruption is most likely to occur. By doing so, the inhibit logic prevents erroneous signals generated as a result of corrupted information from adversely affecting the operation of the storage system. As a result, the corrupted information is tolerated.

Abstract: An improved fault detection system and method for detecting the occurrence of faults within the addressing logic of a storage device is provided. Data stored to a selected address within a storage device includes a copy of the selected address. During a subsequent read operation, the copy of the address is read from memory and compared to the read address used to perform the memory access. If the addresses are not the same, a potential addressing fault occurred within the control logic of the storage device. The fault detection system is particularly adaptable for use with storage devices having a relatively small number of addressable locations, each containing a relatively large number of bits. According to one embodiment of the invention, the storage device is a General Register Array (GRA) utilized as a queue.

Abstract: A stored data modifier modifies data starting at any arbitrary address on a storage medium that should output a data word with a multi-byte width. A masked ROM outputs a 2N-byte data word starting at an address specified as a multiple of 2N by an address signal. A correspondence detector determines whether or not correspondence is found between a correction address and one of a number 2N of addresses starting at, or preceding, the address specified by the address signal. If the correspondence detector has found the correspondence, a stored data selecting section selectively outputs, on a byte-by-byte basis, either the output of the masked ROM or correction data in accordance with the address signal and the correction address.

Abstract: A method and system for compressing memory address traces based on detecting and reducing the loops that exist in a trace is disclosed. The method and system consists of two steps. In the first step, the trace is analyzed and loops are detected by determining the control flow among the program basic blocks. In the second step, each loop is analyzed to eliminate constant address references, and to apply compiler-like strength reduction on addresses that differ only by a fixed offset between consecutive loop iterations. Addresses that cannot be eliminated using the method and system of the present invention are kept in the trace.

Abstract: A control store unit having a control store address generator able to provide both the normal control store address generation functions, and the BIST/logout address generation functions. In response to a test enable signal, the address generator switches between two modes: a normal mode and a test mode. Under the normal mode, normal control store addresses are generated. Under the test mode, a sequence of BIST/logout addresses are generated that sequentially cycles through the entire control store memory at full CPU speed.

Abstract: Untrusted executable code programs (applets or controls) are written in native, directly executable code. The executable code is loaded into a pre-allocated memory range (sandbox) from which references to outside memory are severely restricted by checks (sniff code) added to the executable code. Conventional application-program interface (API) calls in the untrusted code are replaced with translation-code modules (thunks) that allow the executable code to access the host operating system, while preventing breaches of the host system's security. Static links in the code are replaced by calls to thunk modules. When an API call is made during execution, control transfers to the thunk, which determines whether the API call is one which should be allowed to execute on the operating system.

Abstract: A computer system for diagnosing and isolating faults in the computer system. A first value is written from the processor using the bus a first address within the address space of a diagnostic state machine. The value is latched in a first register and written from the first register to a second address in the memory. By reading a second value from the memory at second address, the processor compares the second value to the first value to indicate an error if they are different.

Abstract: A method and apparatus for performing cache accesses. A comparator is coupled to a cache and a lookup parity bit line to perform error detection.

Abstract: Device selects lines from each I/O device are brought into a PCI host bridge individually so that the device number of a failing device may be logged in an error register when an error is seen on the PCI bus. Until the error register is reset, subsequent load and store operations are delayed until the device number of the subject device may be checked against the error register. If the subject device is a previously failing device, the load/store operation to that device is prevented from completing, either by forcing bad parity or zeroing all byte enables. By forcing bad parity of zero byte enables, the I/O device will respond to the load or store request by activating its device select line, but will not accept store data. Operations to devices which are not logged in the error register are permitted to proceed normally, as are all load store operations when the error register is clear.

Abstract: The present invention provides a memory module having connective terminals and a plurality of random access memories connected through a first set of interconnections to the connective terminals. At least one of the random access memories has at least one defective address. The memory module further has a storage device connected through a second set of interconnections to the connective terminals for storing an information of the at least one defective address so as to allow a processing unit to fetch the information of the at least one defective address from the storage device so that the processing unit is operated to inhibit an access to the at least one defective address.

Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

Abstract: A data storage system wherein a host computer section having host computer processors for processing data is coupled to a bank of disk drives through an interface. The interface includes a plurality of controllers coupled to a bus. Each one of the controllers is adapted to request a data transfer between the bus and an addressed one of the addressable memories. Each such request is transmitted to the addressed one of the memories in bursts. Each one of the bursts in a request has a tag unique to such request. The bursts from one of the requesting controllers to the one of the addressed memories addressed by such one of the controllers are interleaved with bursts of requests from another one of the requesting controllers to the same or another one of the addressed memories addressed by said another one of the controllers. Each one of the addressable memories has a control logic coupled to the bus for receiving the request from the one of the controllers addressing such one of the addressable memories.