State Error (i.e., Content Of Instruction, Data, Or Message) Patents (Class 714/49)
  • Patent number: 10677662
    Abstract: A surveillance platform for the sensing, measuring, monitoring and controlling equipment and environments, such as food storage and retailing environments, data center environments, and other environments in which equipment performance, operating status, and environmental condition monitoring is desirable, is provided. The surveillance platform can facilitate reporting, visualizing, acknowledging, analyzing, calculating, event generating, notifying, trending, and tracking, of operational events occurring within the environment. Such techniques can be used to protect articles such as food articles, medical articles, computing devices and equipment, artifacts, documents, and the like.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: June 9, 2020
    Assignee: MAGNUM ENERGY SOLUTIONS, LLC
    Inventors: Michael E. Giorgi, Jorge E. Saenz
  • Patent number: 10642718
    Abstract: Disclosed is an improved approach to implement testing for distributed computing systems. A switchboard framework is provided that allows tests to be dynamically generated and executed against a system under test.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: May 5, 2020
    Assignee: NUTANIX, INC.
    Inventors: Manan Hemantkumar Shah, Jagpreet Kaur Saigal, Kilol Surjan
  • Patent number: 10635616
    Abstract: Configuration devices in a module. In some embodiments a radio-frequency module includes a serial bus including a first serial data line and a second serial data line. The radio-frequency module also includes a control component coupled to the serial bus and the first switch, the control component configured to determine whether first data is detected on the first serial data line, determine whether second data is detected on the second serial data line, and decode a command based on the first data and second data when the first data is detected on the first serial data line and when the second data is detected on the second serial data line.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: April 28, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Andrew Raymond Chen, Lui Lam, James Henry Ross, Bryan J. Roll, William Gerard Vaillancourt
  • Patent number: 10616267
    Abstract: In one embodiment, a device generates one or more time series of characteristics of client-server communications observed in a network for a particular client in the network. The device partitions the one or more time series into sets of time windows based on patterns present in the characteristics of the client-server communications. The device compares the characteristics of the client-server communications from the partitioned time windows to determine measures of behavioral similarity between the compared time windows. The device provides the measures of behavioral similarity between the compared time windows as input to a machine learning-based malware detector. The device causes performance of a mitigation action in the network when the machine learning-based malware detector determines that the particular client in the network is infected with malware.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: April 7, 2020
    Assignee: Cisco Technology, Inc.
    Inventors: Karel Bartos, Jirí Havelka, Martin Neznal
  • Patent number: 10567542
    Abstract: A data management device includes a buffer and a processor. The processor may select an unprocessed full key and generate a buffer entry based on a difference between an entry of a local snapshot specified by the unprocessed full key and an entry of a previous local snapshot specified by the unprocessed full key. The processor may make a first determination that a lookup key entry associated with the unprocessed full key is different than a lookup key entry associated with a processed full key. The process may add the generated buffer entry to the buffer after processing the buffer in response to the first determination.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: February 18, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Prajakta Balkrishna Ayachit, George Mathew, Ajith Krishnamurthy, Krithika Subramanian
  • Patent number: 10477419
    Abstract: In an embodiment, a method for restoration of MT (Mobile Terminating) CS services in case of failure of a PS Core Network CN entity, referred to as original CN entity, originally identified as to be contacted for a paging request towards a User Equipment UE for said MT CS services, in a mobile communication system, comprises: providing that an alternative CN entity is contacted instead of said original CN entity, and that said alternative CN entity is forced to accept said paging request even if said UE is unknown to said alternative CN entity.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: November 12, 2019
    Assignee: Alcatel Lucent
    Inventor: Bruno Landais
  • Patent number: 10367525
    Abstract: Techniques are disclosed relating to encoding communications. In some embodiments, for different rows of an encoding matrix, the following operations are performed: generate a set of operations for entries in the row, where the set of operations includes respective operations to be performed on the entries for multiplication of the matrix by a vector, propagate values of entries in the encoding matrix into the set of operations, and simplify ones of the set of operations based on the propagated values to generate an output set of operations. In some embodiments, the output sets of operations are usable to encode input data for communication over a medium. In some embodiments, the disclosed techniques facilitate loop unrolling within compiler memory constraints. In some embodiments, an apparatus (e.g., a mobile device) is configured with the output sets of operations.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: July 30, 2019
    Assignee: National Instruments Corporation
    Inventors: David C. Uliana, Newton G. Petersen, Tai A. Ly, Hojin Kee, Adam T. Arnesen, Dustyn K. Blasig, Gandiinaa Gumenjav
  • Patent number: 10241834
    Abstract: An application workload is scheduled for execution by each of one or more processing cores operating in a first mode. Performance metrics for the each of the one or more processing cores and a memory component are monitored, wherein the memory component stores data necessary for the one or more processing cores to carry out instructions to complete the scheduled workload. If performance metrics are greater than a specified threshold, a number of the one or more processing cores handling the scheduled workload is reduced. If the performance metrics are not greater than the specified threshold, whether each of the processing cores of the processor is currently handling a scheduled workload is determined. If each of the processing cores of the processor is currently handling the scheduled workload, the processor is configured to operate in a second mode.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sangram Alapati, Hima B. Nimmagadda, Satish K. Sadasivam
  • Patent number: 10210117
    Abstract: A shared memory computing device optimised for executing realtime software that has at least one interconnect master, a shared memory, N cache modules and M processor cores, where the value of N>=1 and M =N. Each of the N cache modules has a means to implement an update-type cache coherency policy across those N cache modules. Each processor core is assigned a different one of the N cache modules as that processor core's private cache. Furthermore, the memory transfer request latency of non-atomic memory transfer requests issued by each of the M processor cores to the shared memory is not modified by: (a) the memory transfer requests issued by any of the other M processor cores; or (b) the memory transfer requests issued by at least one other interconnect master.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: February 19, 2019
    Inventor: Benjamin Aaron Gittins
  • Patent number: 10135885
    Abstract: A method for performing initial registration is provided. The method includes receiving a server timeout message, the server timeout message including at least a field set to a value equal to a value received during a first registration. The method further includes initiating restoration procedures by performing an initial registration.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: November 20, 2018
    Assignee: BlackBerry Limited
    Inventors: Jan Hendrik Lucas Bakker, Andrew Michael Allen, Adrian Buckley
  • Patent number: 10102070
    Abstract: A purpose is to speed up a write process with a parity update. An information processing system includes storage devices constituting a RAID group, coupled to one bus and communicating with each other. Each of the storage devices includes a device controller and a storage medium for storing data. The storage devices include a first storage device storing old data and a second storage device storing old parity associated with the old data. A first device controller of the first storage device creates intermediate parity based on the old data and new data for updating the old data and transmit the intermediate parity to the second storage device specifying the second storage device storing the old parity associated with the old data, and a second device controller of the second storage device creates new parity based on the intermediate parity and the old parity.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: October 16, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Shimpei Nomura, Akifumi Suzuki, Mitsuhiro Okada, Satoshi Morishita
  • Patent number: 10104671
    Abstract: A wireless communication apparatus for a wireless communication system is described in one example comprising a receiver to receive communication signals, one or more processor to determine, based on the communication signals, that at least two SIM cards are located in one and the same wireless communication device of the wireless communication system, and the one or more processor further to coordinate requests for the at least two SIM cards that are located in the wireless communication device. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: October 16, 2018
    Assignee: Intel IP Corporation
    Inventor: Soumen Chakraborty
  • Patent number: 10037290
    Abstract: A dual-port memory including a first memory array and at least one address decoder. The first memory array includes memory cells and two ports for each of the memory cells. The at least one address decoder generates word line signals for concurrent access to two ports of one or more cells of the memory cells in a same row of the first memory array. Each of the word line signals is generated to perform a read operation. Pulse widths of the word line signals for the read operations are proportional to a ratio of (i) a reference amount of cell current of a cell of a reference memory array to (ii) an amount of cell current of the one or more cells of the plurality of memory cells in a same row of the first memory array.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 31, 2018
    Assignee: Marvell International Ltd.
    Inventors: Peter Lee, Moon-Hae Son, Xinghui Guo
  • Patent number: 9990835
    Abstract: A security system notifies of an alarm situation. The security system has two separate communications paths. When the alarm situation is determined, the security system may select one of the two separate communications paths based on performance, cost, urgency, and other factors.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: June 5, 2018
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventor: John Alson Hicks, III
  • Patent number: 9934301
    Abstract: Methods and systems for efficient file replication are provided. In some embodiments, one or more coarse signatures for blocks in a base file are compared with those coarse signatures for blocks of a revised file, until a match is found. A fine signature is then generated for the matching block, of the revised file and compared to a fine signature of the base file. Thus, fine signatures are not computed unless a coarse signature match has been found, thereby minimizing unneeded time-consuming fine signature calculations. Methods are also provided for determining whether to initiate a delta file generation algorithm, or whether to utilize a more efficient replication method, based upon system and/or file parameters. In accordance with additional embodiments, the lengths of valid data on physical blocks are obtained from physical block mappings for the files, and these lengths and mappings are utilized for delta file generation, to minimize unnecessary signature computations.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: April 3, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Piyush Kumar Srivastava, Madhusudhana Honnuduke Srinivasa Murthy
  • Patent number: 9870249
    Abstract: A virtual computer system includes an external event acquisition controller, an external event storing unit, and a snap shot creating unit. The external event acquisition controller performs control for acquiring an event regarding an external device provided outside a virtual computer which mounts a guest operating system in which an application program is installed. The external event storing unit stores the external event acquired by the external event acquisition controller. The snap shot creating unit creates a snap shot of the guest operating system including the application program after the external event is stored in the external event storing unit.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: January 16, 2018
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Toshiaki Yoshinari, Koji Nishiyama
  • Patent number: 9672939
    Abstract: Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. Therefore, any address at which the bits of read data do not all have the same value may be considered to be faulty. Failure data from the test can therefore be stored in the same array of memory cells that is being tested.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: June 6, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Michael A. Shore
  • Patent number: 9654563
    Abstract: Novel tools and techniques are described for providing remote control of consumer electronics devices, and, more particularly, to tools and techniques for providing virtual remote control of consumer electronics devices that do not have dedicated remote controllers.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: May 16, 2017
    Assignee: Biscotti Inc.
    Inventors: Matthew B. Shoemake, Syed Nadeem Ahmed
  • Patent number: 9536082
    Abstract: Embodiments relate to an isolated program execution environment. An aspect includes receiving, by the isolated program execution environment on a computer comprising a processor and a memory, a request to run a program. Another aspect includes wrapping program code corresponding to the program as a function. Another aspect includes cloning a real global object of the isolated program execution environment to create a fake global object. Another aspect includes passing the fake global object to the function. Another aspect includes executing the function, such that the function executes the program.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: January 3, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony Ffrench, Libra C. Huang, Timothy J. Smith, Chih-Wen Su, Yi-Hong Wang
  • Patent number: 9529855
    Abstract: Systems and methods are disclosed for ingesting data, such as point of interest data. According to certain embodiments, a raw data load transmitted over a network is received from a first data source. The raw data load may comprise a plurality of raw data records, which may be stored in a first database. A first plurality of standard data records previously received from the first data source may be accessed and compared to each of the plurality of raw data records to identify at least one added record. The at least one added record may be compared to a second plurality of standard data records received from a second data source to identify a matching record received from the second data source. The at least one added record may be assigned a key from the matching record. Moreover, the updated information may be sent to an update queue, such that applications may be notified of and receive the updates.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 27, 2016
    Assignee: MapQuest, Inc.
    Inventors: Bryan C. Westhafer, Philip Russo, Marshall B. Matthews, Antony M. Pegg
  • Patent number: 9514064
    Abstract: A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: December 6, 2016
    Assignee: Synopsys, Inc.
    Inventors: Pranab Bhooma, Carlos Basto, Kulbhushan Kalra
  • Patent number: 9465653
    Abstract: A computing system can provide user interfaces and back-end operations to facilitate review and invalidation of executed jobs. The system can provide an interface that allows the operator to review quality-control information about a completed job. Once the operator identifies a job as invalid, the operator can be presented with further options, such as whether to invalidate only the reviewed job or the job and all its descendants. The operator can also review antecedent jobs to an invalid job (e.g., in order to trace the root of the problem) and can selectively invalidate antecedent jobs.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: October 11, 2016
    Assignee: Dropbox, Inc.
    Inventors: Shaunak Kishore, Karl Dray
  • Patent number: 9442801
    Abstract: An example device includes a first error corrector to perform platform error correction based on a stride length. A memory includes a second error corrector that is to perform on-memory error correction that is to be disabled for platform error correction.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: September 13, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Melvin K. Benedict, Lidia Warnes
  • Patent number: 9390053
    Abstract: For a user terminal connected to one of cache devices distributed in a network and receiving contents, terminal access information including terminal address information about the user terminal and identification information of the cache device is stored and managed. If a content retransmission request message of the user terminal is detected at other cache device, this is regarded as a handover of the user terminal. This allows a simple detection of handover that occurs during content transmission.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: July 12, 2016
    Assignee: SK TELECOM CO., LTD.
    Inventors: Jong Min Lee, Kyung Jun Lee, Young Jae Shim
  • Patent number: 9383993
    Abstract: In an illustrative embodiment of a process for software version recommendation, a computer receives information representative of a software instance at a target machine, analyzes the received information using a set of predefined rules and a set of available updates metadata associated with a particular updates agent and target machine to identify information pertinent to a combination of a respective target machine associated with the particular updates agent. The computer, responsive to a determination to send the identified information as a recommendation to the respective target machine, sends the recommendation to the combination of the respective target machine associated with the particular updates agent.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: July 5, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Leho Nigul
  • Patent number: 9383992
    Abstract: In an illustrative embodiment of a process for software version recommendation, a computer receives information representative of a software instance at a target machine, analyzes the received information using a set of predefined rules and a set of available updates metadata associated with a particular updates agent and target machine to identify information pertinent to a combination of a respective target machine associated with the particular updates agent. The computer, responsive to a determination to send the identified information as a recommendation to the respective target machine, sends the recommendation to the combination of the respective target machine associated with the particular updates agent.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: July 5, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Leho Nigul
  • Patent number: 9379892
    Abstract: A system and method for securing processing devices includes a police bridge disposed in one or more data busses between a central processing and input/output peripherals, components or components. The police bridge is suitably disposed between northbridge logic and southbridge logic. Alternatively, or in addition to such placement, a police bridge is suitably place between southbridge logic and super I/O logic. A police bridge is suitably a system-on-chip or fixed or programmable hardware. The police bridge monitors or controls its associated bus to determine whether acceptable data, with an associated certificate in other embodiments, is being communicated and signaling is generated accordingly.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: June 28, 2016
    Assignee: Toshiba America Electronic Components, Inc.
    Inventor: Rakesh Sethi
  • Patent number: 9361114
    Abstract: Managing interrupts in a computing environment includes executing an instruction, deriving an interrupt mask value based at least in part on the instruction being executed, performing a masking operation involving the interrupt mask value and at least one pending interrupt to determine whether a pending interrupt is allowable, and in the event that the pending interrupt is allowable, performing the interrupt.
    Type: Grant
    Filed: December 6, 2005
    Date of Patent: June 7, 2016
    Assignee: Azul Systems, Inc.
    Inventors: Gil Tene, Scott Sellers, Jack Choquette, Michael A. Wolf
  • Patent number: 9330027
    Abstract: A system employs a white list of authorized transactions to control access to system registers. In an embodiment, the white list is loaded into filter registers during system boot. Routing logic monitors a logical interconnect fabric of the system for register access requests. The routing logic parses source, destination information from a request to index the white list. If the white list includes an entry corresponding to the processing entity indicated in the source information and the register indicated in the destination information, the routing logic will permit the requested access.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 3, 2016
    Assignee: Intel Corporation
    Inventors: Julien Carreno, Derek Harnett, Gordon J. Walsh
  • Patent number: 9311210
    Abstract: In some embodiments, a method includes receiving, at a data collection module implemented in at least one of a memory or a processing device, from a processing system, an observation value for a variable. The observation value of the variable is associated with operation of the processing system at a time. The method further includes computing a deviation value of the variable from a baseline value at the time based on the observation value. The method further includes computing a stableness value of the variable at the time based on the baseline value and a variance of the variable during a time period including the time. The method further includes transmitting an indication of the processing system as operating with a fault in response to the deviation value meeting a first criterion and the stableness value meeting a second criterion.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: April 12, 2016
    Assignee: VIVIDCORTEX, INC.
    Inventor: Baron Schwartz
  • Patent number: 9270734
    Abstract: The disclosure provides a download method and system based on a Management Data Input/Output (MDIO) interface, wherein the download method based on the MDIO interface comprises: a master device informing a slave device of using the MDIO interface to start downloading data packets in batches; the master device transmitting data packets in batches to the slave device by using an MDIO frame, wherein the MDIO frame comprises: a data packet address field and/or a data packet serial number field, wherein the data packet address field is used to indicate a relative address of one data packet in the slave device, and the data packet serial number field is used to indicate a location of said one data packet in multiple data packets; the slave device judging that a received data packet is a last data packet of a current batch transmission from the master device, and finishing a current batch download.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: February 23, 2016
    Assignee: ZTE CORPORATION
    Inventors: Yun Zhang, Yu Fang
  • Patent number: 9261559
    Abstract: This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: February 16, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 9253039
    Abstract: A device management system includes an accommodation apparatus, a network device, and a device management apparatus. The accommodation apparatus includes a plurality of storage spaces. Each of the plurality of storage spaces is capable of storing an electronic device. The network device is connected to an electronic device accommodated in the accommodation apparatus. The device management apparatus includes a processor. The processor obtains connection information when a first electronic device is newly placed in the accommodation apparatus. The connection information indicates an expected connection point in the network device. The first electronic device is to be connected to the network device at the expected connection point with a cable. The processor identifies an actual connection point at which the network device has been connected to the first electronic device with the cable. The processor determines, based on the connection information, whether the actual connection point is appropriate.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: February 2, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Hiroyoshi Kodama
  • Patent number: 9203433
    Abstract: A decoder 5 applies decode processing to N input data in parallel to generate K decode data. An S/P converter 6 outputs N input data applied in series to decoder 5 through first lines L1-L64 dividedly over several times. A P/S converter 7 receives through second lines R1-R60 the K decode data from decoder 5 dividedly over several times to output in series the K decoded data to an external source.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: December 1, 2015
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Takashi Maehata
  • Patent number: 9171155
    Abstract: A malware detection rule is evaluated for effectiveness and accuracy. The detection rule defines criteria for distinguishing files having a characteristic of interest from other files lacking that characteristic, for instance, malicious files vs. benign files. The detection rule is applied to a set of unknown files. This produces a result set that contains files detected from among the set of unknown files as having the at least one characteristic of interest. Each file from the result set is compared to at least one file from a set of known files having the characteristic to produce a first measure of similarity, and to at least one file from a set of known files lacking the characteristic to produce a second measure of similarity. In response to the first measure of similarity exceeding a first similarity threshold, the detection rule is deemed effective. In response to the second measure of similarity exceeding a second similarity threshold, the detection rule is deemed inaccurate.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: October 27, 2015
    Assignee: KASPERSKY LAB ZAO
    Inventors: Alexey M. Romanenko, Ilya O. Tolstikhin, Sergey V. Prokudin
  • Patent number: 9146791
    Abstract: In accordance with one aspect of the present description, an indication that a communication failure reported in a predetermined time interval is more likely the result of a software failure than a hardware failure may be made if the number of communication links reporting a communication failure in the predetermined time interval exceeds a communication link failure threshold, and the number of communication link devices such as nodes or communication paths which have been implicated as causing a communication failure, exceeds an implicated device threshold. Other features and aspects may be realized, depending upon the particular application.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: September 29, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Todd C. Sorenson, Liang Hua Wu
  • Patent number: 9122596
    Abstract: A method begins by tracking age related failure levels of memory devices within the storage unit. The method continues by maintaining a data location table that maps a range of DSN addresses allocated to the storage unit to the memory devices and further records storing of encoded data slices having specific DSN addresses within the memory devices. The method continues, when the age related failure level for a memory device compares unfavorably to a first failure level threshold, by determining to reassign a portion of DSN addresses assigned to the memory device. The method continues by identifying a second memory device having a corresponding age related soft failure level comparing favorable to the first failure level threshold. The method continues by reassigning the portion of the DSN addresses from the memory device to the second memory device and updating the data location table.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: September 1, 2015
    Assignee: Cleversafe, Inc.
    Inventors: Gary W. Grube, Timothy W. Markison
  • Patent number: 9118351
    Abstract: A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: August 25, 2015
    Assignee: Infineon Technologies AG
    Inventors: Antonio Vilela, Rainer Faller, Michael Goessel, Simon Brewerton, Glenn Ashley Farrall, Neil Stuart Hastie, Boyko Traykov, David Addison, Klaus Oberlaender, Thomas Rabenalt
  • Patent number: 9092352
    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: July 28, 2015
    Assignee: RAMBUS INC.
    Inventors: Yuanlong Wang, Frederick A. Ware
  • Patent number: 9047192
    Abstract: A system and method for optimizing redundant output verification, are provided. A hardware-based store fingerprint buffer receives multiple instances of output from multiple instances of computation. The store fingerprint buffer generates a signature from the content included in the multiple instances of output. When a barrier is reached, the store fingerprint buffer uses the signature to verify the content is error-free.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 2, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vilas Sridharan, Sudhanva Gurumurthi
  • Publication number: 20150149836
    Abstract: A recoverable and fault-tolerant CPU core and a control method thereof are provided. The recoverable and fault-tolerant CPU core includes first, second, and third arithmetic logic circuits configured to perform a calculation requested by the same instruction, a first selector configured to compare calculation values output from the first, second, and third arithmetic logic circuits by the same instruction, determine as a normal state when two or more of the calculation values are the same, and if not, determine as a fault state, and a register file configured to record the calculation value having the same value, when determining as the normal state in the first selector.
    Type: Application
    Filed: November 19, 2014
    Publication date: May 28, 2015
    Inventors: Young Su KWON, Jin Ho HAN, Kyung Jin BYUN
  • Patent number: 9021315
    Abstract: Architectures and techniques for uploading virtual machine (VM) images to a network-accessible computing platform from a client device while simultaneously performing error detection of the VM images at the client device. One technique can include transmitting a request from the client device to upload VM images. The technique can further include receiving an application from the computing platform and using the application to reconstitute the VM images from a first stream at the client device while performing error detection. The technique also includes using the application to upload the VM images from a second stream at the client device to the computing platform while performing the error detection.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: April 28, 2015
    Assignee: Amazon Technologies, Inc.
    Inventors: Bashuman Deb, Avichai M. Lissack
  • Patent number: 8990641
    Abstract: In a data processing system, a selection is made, based at least on addresses of previously detected errors in a memory subsystem, between at least a first timing and a second timing of data transmission with respect to completion of error detection processing on a target memory block of the memory access request. In response to receipt of the memory access request and selection of the first timing, data from the target memory block is transmitted to a requestor prior to completion of error detection processing on the target memory block. In response to receipt of the memory access request and selection of the second timing, data from the target memory block is transmitted to the requestor after and in response to completion of error detection processing on the target memory block.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Gollub, Benjiman L. Goodman, Sujatha Kashyap, Eric E. Retter, Yuen C. Tschang
  • Patent number: 8990643
    Abstract: In a data processing system, a selection is made, based at least on addresses of previously detected errors in a memory subsystem, between at least a first timing and a second timing of data transmission with respect to completion of error detection processing on a target memory block of the memory access request. In response to receipt of the memory access request and selection of the first timing, data from the target memory block is transmitted to a requestor prior to completion of error detection processing on the target memory block. In response to receipt of the memory access request and selection of the second timing, data from the target memory block is transmitted to the requestor after and in response to completion of error detection processing on the target memory block.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Gollub, Benjiman L. Goodman, Sujatha Kashyap, Eric E. Retter, Yuen C. Tschang
  • Publication number: 20150074456
    Abstract: Versioned memories using a multi-level cell (MLC) are disclosed. An example method includes comparing a global memory version to a block memory version, the global memory version corresponding to a plurality of memory blocks, the block memory version corresponding to one of the plurality of memory blocks. The example method includes determining, based on the comparison, which level in a multi-level cell of the one of the plurality of memory blocks stores checkpoint data.
    Type: Application
    Filed: March 2, 2012
    Publication date: March 12, 2015
    Inventors: Doe Hyun Yoon, Jichuan Chang, Naveen Muralimanohar, Robert Schreiber, Paolo Faraboschi, Parthasarathy Ranganathan
  • Publication number: 20150067412
    Abstract: In one embodiment, the present invention includes a method for handling a request received in an agent designed in accordance with a peripheral component interconnect (PCI) specification using PCI Express™ semantics. More specifically, responsive to determining that the agent does not support the request, an unsupported request detection register of the agent can be updated, and a response sent from the agent to indicate that the agent does not support the request. Other embodiments are described and claimed.
    Type: Application
    Filed: October 1, 2014
    Publication date: March 5, 2015
    Inventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Rohit R. Verma
  • Patent number: 8972775
    Abstract: Memory devices and/or methods of managing memory data errors are provided. A memory device detects and corrects an error bit of data read from a plurality of memory cells, and identifies a memory cell storing the detected error bit. The memory device assigns a verification voltage to each of the plurality of first memory cells, the assigned verification voltage corresponding to the corrected bit for the identified memory cell, the assigned verification voltage corresponding to the read data for the remaining memory cells. The memory device readjusts the data stored in the plurality of memory cells using the assigned verification voltage. Through this, it is possible to increase a retention period of the data of the memory device.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong June Kim, Jae Hong Kim, Jun Jin Kong, Kyoung Lae Cho
  • Patent number: 8972813
    Abstract: An apparatus and a method for Automatic Repeat reQuest (ARQ) feedback in a wireless communication system are provided. A method for the ARQ feedback at a receiving end includes when receiving an ARQ block from the transmitting end, checking for error in the ARQ block, when the ARQ block has no error, initializing and driving a timer used for determining whether to perform the ARQ feedback according to reception of a next ARQ block, when receiving the next ARQ block without error before the timer expires, initializing and driving the timer, and when the timer expires, performing the ARQ feedback in relation to at least one ARQ block received without error.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Bin Chang, Taori Rakesh, Agiwal Anil
  • Patent number: 8966327
    Abstract: A buffer integrated circuit device. The device comprising an output driver formed on the substrate member, the output driver having at least a command bus and an address bus. The device has a protocol and parity checking block (“Block”). The device has a table configured in the block. The table is programmable with a plurality of timing parameters. The device has a memory state block coupled to the table and a command history table coupled to the table to process protocol information for all commands that pass through the Block. The buffer integrated circuit device utilizes the protocol checking functionality to prevent failure propagation and enables data protection even in the case of host memory controller failure or system-level failure of any signal or signals on the command, control and address bus from the host memory controller to the buffer integrated device.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: February 24, 2015
    Assignee: Inphi Corporation
    Inventor: David Wang
  • Patent number: RE46348
    Abstract: A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: March 21, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Gopinath Balakrishnan, Luca Fasoli, Tz-Yi Liu, Yuheng Zhang, Yan Li