Abstract: Methods and systems for capturing error information regarding a Serial Advanced Technology Attachment (SATA). An initiator device is enhanced in accordance with features and aspects hereof to detect an error condition in operation of the system and to transmit error information to the SATA target device during a soft reset condition applied to the SATA target device. The SATA target device discards all such frames received during the soft reset condition until the initiator device clears the soft reset condition. The error information may be captured for further analysis and debug of the error condition by suitable error analyzer equipment such as a SATA bus analyzer. The initiator device may be a SATA initiator or a Serial Attached SCSI (SAS) initiator using the SATA Tunneling Protocol (STP). Features and aspects hereof may also include a SAS/SATA bridge device coupling a SAS initiator to the SATA target device.

Abstract: The present invention determines an incorrect packet from a faulty partition quickly and reliably and prevents the packet from flowing into normal partitions through simple control actions. The multi-partition computer system is a multi-partitioned computer system in which a plurality of nodes are logically divided into a plurality of partition, and each node contained in the partitions includes a packet identification unit which, upon receiving a packet, compares the partition identification information uniquely assigned to own partition against the partition identification information contained in the receive packet, and if these pieces of information do not match each other, judges and discards the receive packet as an incorrect packet.

Abstract: A method is disclosed for detecting a memory stack fault. The method may include reserving a memory stack for executing software instructions. The method may also include enabling a debug unit and as the software instructions are execute, utilizing the debug unit to monitor a memory space adjacent to the memory stack. The method may further include identifying a memory stack fault if a write operation to the memory space is attempted.

Abstract: Apparatus, systems, and methods may operate to authenticate a desktop client to an identity service (IS), to receive a request, from an application, at the IS via the desktop client for a virtual service internet protocol (IP) address associated with a service. The IS may operate to build a routing token that includes an original physical IP address associated with the service when a policy associated with the IS permits access to the service by a user identity associated with the desktop client. After the routing token is validated, the application may be connected to the service via the desktop client. The application may comprise an e-mail application or a remote control application, such as a virtual network computing (VNC) application. Additional apparatus, systems, and methods are disclosed.

Abstract: A method for detecting an error in a home network while a network-compatible device is newly added to the home network, the home network having a modem configured to be connected to the Internet, a home gateway connected between the modem and the home network, the method for detecting the error comprising employing address resolution protocol and detecting the error in the home network due to filtering based on MAC addresses is disclosed. The disclosed subject matter can be used for diagnosis of problems in the home network that can arise due to filtering based on Media Access Control addresses by the home gateway.

Abstract: A method and an apparatus for preventing a basic input/output system (BIOS) from failing to enter a boot program are adapted to solve the problem that when a central processing unit (CPU) executes a first instruction after a computer is powered on, a start address to be executed is erroneously set as another corresponding start address, resulting in that a BIOS cannot enter a boot program. In the method of the present invention, a jump instruction is written to the corresponding start address, so as to enable an execution instruction to jump to a boot block of the BIOS when the start address is erroneously set in the computer, thus performing a normal boot operation.

Abstract: A failure management method for a computer including a processor, and a memory connected to the processor, and in which the processor containing a memory protection function, executes a first software program and a second software program monitoring the operation of the first software program, and the second software program retains error information including address information and access-related information; and the method implemented by the by the second software program includes a step for detecting the occurrence of errors in the memory; and a step for prohibiting access to the address of the memory where the error occurred, and monitoring the access state; and a step for executing the failure processing when accessing by the first software program of the address of the memory where the error occurred was detected.

Abstract: A system and method for fast detection of cache memory hits in memory systems with error correction/detection capability is provided. A circuit for determining an in-cache status of a memory address comprises an error detect unit coupled to a cache memory, a comparison unit coupled to the cache memory, a results unit coupled to the comparison unit, and a selection unit coupled to the results unit and to the error detect unit. The error detect unit computes an indicator of errors present in data stored in the cache memory, wherein the data is related to the memory address. The comparison unit compares the data with a portion of the memory address, the results unit computes a set of possible in-cache statuses based on the comparison, and the selection unit selects the in-cache status from the set of possible in-cache statuses based on the indicator.

Abstract: An electronic design automation (EDA) tool for and method of optimizing a placement of process monitors (PMs) in an integrated circuit (IC). In one embodiment, the EDA tool includes: (1) a critical path/cell identifier configured to identify critical paths and critical cells in the IC, (2) a candidate PM position identifier coupled to the critical path/cell identifier and configured to identify a set of candidate positions for the PMs, (3) a cluster generator coupled to the critical path/cell identifier and configured to associate the critical cells to form clusters thereof and (4) a PM placement optimizer coupled to the candidate PM position identifier and the cluster generator and configured to place a PM within each of the clusters by selecting among the candidate positions.

Abstract: An apparatus and method are provided for connecting a host Enterprise System Connection Architecture (ESCON) Input/Output (I/O) interface to a cache of a data storage system. The apparatus includes (a) a set of at least 4 pipelines, each pipeline being coupled on a first end to the host ESCON I/O interface and being coupled on a second end to the cache, (b) a plurality of line processors, each line processor controlling one or more of the pipelines of the set of pipelines, and (c) in each pipeline, a protocol engine, the protocol engine configured to distinguish user data from frame header data and separate the user data from the frame header data for transport over the pipeline.

Abstract: When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is sent to a CPU, while the transaction is finished on the IO bus. To prevent a transaction between IO devices from gaining access to any resource in another logical partition, one access permission bit is provided for each combination of all the IO devices, and the access is permitted only when the bit has a predetermined value. A reset signal is provided by IO slot so that only an IO slot allocated to a specific logical partition can be reset without affecting any other logical partition. A transaction issued from an IO device in one logical partition is prevented from gaining access to a resource in another logical partition, while proper error handling can be performed.

Abstract: An information processing device is provided. The information processing device includes a frame acquiring unit for acquiring a frame using a signal transmitted via a network, a computing unit for computing a check sequence on the basis of data included in the frame, a checking unit for checking whether the frame is corrupted by checking whether the check sequence coincides with a check sequence added to the frame in advance, a storing unit for storing a table that is a list of check sequences computed in advance on the basis of a plurality of pieces of data representing addresses of frames to be received by the information processing device, and a determining unit for determining whether the frame should be received by determining whether a check sequence computed by the computing unit on the basis of data representing a destination address of the frame coincides with any one of the check sequences included in the table.

Abstract: Provided are a method, system and article of manufacture for verifying a record as part of an operation to modify the record. A search request is received to determine whether a record matches a value. A first component executes the search request to determine if the record matches the value. The first component sends a verify request to a second component that did not execute the search request to execute the search request to determine whether the record matches the value. A result of the first and second components executing the search request is logged.

Abstract: In some embodiments, the invention involves a system and method to continuously log correctable errors without rebooting by changing the granularity of the error detection and logging mechanism. A mask register is used to identify which errors are to be logged. Each bit of the mask register may represent a different memory component of the system. Logging of the memory component is determined by the value of the bit in the mask. The masking enables granularity of error logging to the channel and/or dual in-line memory module (DIMM) level. Other embodiments are described and claimed.

Abstract: A network error detecting method checks if a network connection device has an Internet protocol (IP) address, if domain name mapping of web pages is correct, and if data communication between a web browser and a web server is correct. Accordingly, the network connection device informs the web browser of an IP address error, a domain name mapping error, or a data communication error. The web browser displays the network errors to users when the network errors are detected.

Abstract: Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical.

Abstract: Verifying operation of a data processing system. A first sequence of addressing ranges is generated for multiple requesters. Each addressing range includes a start and an end address and a respective identifying number. A second sequence of verification ranges is generated corresponding the addressing ranges of the first sequence. Each verification range includes a start and an end address and specifies at least one allowed value including each respective identifying number of all of the addressing ranges that overlap the verification range. A respective accessing activity executing on each requestor accesses each addressing range in the first sequence. The accesses include writing the respective identifying number of the addressing range to at least one address of the addressing range. A verification activity executing on a requestor reads a value from each address of each verification range of the second sequence and outputs an error message in response to the value not matching the allowed value.

Abstract: A host fabric interface (HFI) enables debugging of global shared memory (GSM) operations received at a local node from a network fabric. The local node has a memory management unit (MMU), which provides an effective address to real address (EA-to-RA) translation table that is utilized by the HFI to evaluate when EAs of GSM operations/data from a received GSM packet is memory-mapped to RAs of the local memory. The HFI retrieves the EA associated with a GSM operation/data within a received GSM packet. The HFI forwards the EA to the MMU, which determines when the EA is mapped to RAs within the local memory for the local task. The HFI processing logic enables processing of the GSM packet only when the EA of the GSM operation/data within the GSM packet is an EA that has a local RA translation. Non-matching EAs result in an error condition that requires debugging.

Abstract: A write validation system that includes a first address signature collector module that generates a first address signature that is indicative of a write address of data when the data is received at a memory control module. A second address signature collector module generates a second address signature that is indicative of the write address of the data when the data is transferred from the memory control module. An address signature validation module receives the first address signature from the first address signature collector module, receives the second address signature from the second address signature collector module, and compares the first address signature to the second address signature.

Abstract: A radio LSI is provided that is not to cause a delay in sending acknowledgement data. A latch circuit provided in a sending/receiving section latches frame control information out of data being received. A decoder decodes the frame control information to decode a data length and structure of an address field. Furthermore, a latch circuit latches the address-field data of the reception data according to the decoded address-field information. A comparing circuit compares a content of a register entered with an address of the opposite-of-communication completely prepared data to be sent, with a source address of the data being received, to determine a setting/resetting of frame pending in acknowledgement data. A content of the determination is sent to a data-link section. This provides information required for acknowledgement data before completely receiving data, thus eliminating the possibility to cause a delay in sending acknowledgement data.

Abstract: In a data processing system, in order to provide its operating system with a better mechanism to identify and track addressing errors with a high potential to cause a storage overlay, it is first determined whether or not, a program interrupt has occurred. It is next determined whether or not this interrupt involves or occurs as a result of an address translation. It is then determined whether or not, the instruction involved calls for an update of storage. If it is determined that all three of these conditions are satisfied, then a flag is set in an area of storage accessible to the operating system so that it may provide a more specific event monitoring record.

Abstract: A system and method for automatically determining a physical location of one or more units in a rack, including: using one or more physical cables between rack units; cascading a first signal through the one or more units located in the rack, the first signal being encoded with a unit number and a physical parameter; and creating a rack ID by utilizing hardware parameters, the hardware parameters being determined by: detecting a second signal that exists from a bottom unit, the bottom unit located at the bottom of the rack; and using a third signal to send data between the one or more units in the rack by manipulating void spaces within the rack, the third signal being either cabled or an optical signal.

Abstract: Applications are protected from being exposed to exploits and instabilities due to memory operations involving zero byte allocations. Memory operations involving a zero byte allocation are handled by a zero byte memory manager. When an application requests a zero byte allocation, a pointer to a protected part of memory is returned such that when the application attempts to read and/or write to the location the program flow is interrupted.

Abstract: A cache includes a plurality of cache lines, where each cache line includes a detection type field, corresponding cache data field, a detection field, and a corresponding tag field. The detection type field indicates an error detection scheme from a plurality of error detection schemes currently in use for the corresponding cache data field. One example of an error detection scheme is a multiple bit error detection scheme (e.g. an error detection coding (EDC) or an error correction coding (ECC)). Another type is a single bit error detection scheme (e.g. parity error detection). The detection bits field stores parity bits if parity error detection is used. The detection bits field stores checking bits if EDC coding is used.

Abstract: When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is sent to a CPU, while the transaction is finished on the IO bus. To prevent a transaction between IO devices from gaining access to any resource in another logical partition, one access permission bit is provided for each combination of all the IO devices, and the access is permitted only when the bit has a predetermined value. A reset signal is provided by IO slot so that only an IO slot allocated to a specific logical partition can be reset without affecting any other logical partition. A transaction issued from an IO device in one logical partition is prevented from gaining access to a resource in another logical partition, while proper error handling can be performed.

Abstract: A method and system are provided to select address providers that provide mobile internet protocol devices with addresses for communication. An embodiment of the method includes obtaining an address request having a dynamic indicator and a failover counter. Upon obtaining an address request with the dynamic indicator and the failover counter, associating the failover counter with one or more address providers based on the failover counter. The address request is then communicated to one of the address providers associated with the failover provider.

Abstract: A method and apparatus for discovering errors in a translation look-aside buffer (TLB). The TLB comprises a content addressable memory (CAM) and a random access memory (RAM). The TLB contains additional logic to check for error when the TLB is not in normal use to translate from a first set of elements, stored as entries in the CAM, to a second set of elements, stored as entries in the RAM. If the TLB is not in normal use, a RAM entry is selected and checked for errors. If an error is detected in the RAM entry, the corresponding TLB entry is purged.

Abstract: Runtime checks on a program may be used to determine whether a pointer points to a legitimate target before the pointer is dereferenced. Legitimate addresses, such as address-taken local variables (ATLVs), global variables, heap locations, functions, etc., are tracked, so that the legitimate targets of pointers are known. The program may be transformed so that, prior to dereferencing a pointer, the pointer is checked to ensure that it points to a legitimate address. If the pointer points to a legitimate address, then the dereferencing may proceed. Otherwise, an error routine may be invoked. One example way to keep track of legitimate addresses is to group address-taken variables together within a specific range or ranges of memory addresses, and to check that a pointer has a value within that range prior to dereferencing the pointer. However, addresses may be tracked in other ways.

Abstract: A technology for reporting diagnostic information for code of an application program interface is disclosed. In one method approach, diagnostic information for a line of code in a file associated with an application program interface is received. The diagnostic information includes a designation of the line of code. The diagnostic information is stored in a fixed sized buffer. Efficient use of memory is provided without requiring elimination of other diagnostic information previously stored in the fixed sized buffer.

Abstract: Various embodiments include fault tolerant memory apparatus, methods, and systems, including an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit operable to detect a multi-bit error in data read from the memory device, and to retry the read operation in order to distinguish between an intermittent error and a persistent error.

Abstract: A data accessing method for accessing data in a plurality of physical page addresses of a plurality of physical blocks in a flash memory chip is provided. The data accessing method includes proving a plurality of logical page addresses for a host system, creating a logical page to physical page mapping table and a physical page to logical page mapping table to record the mapping between the logical page addresses and the physical page addresses. The data accessing method also includes writing data into the physical page addresses, and updating the logical page to physical page mapping table and the physical page to logical page mapping table. The data accessing method further includes determining whether the physical page addresses are valid or invalid based on the logical page to physical page mapping table and the physical page to logical page mapping table.

Abstract: Methods of operating two or more devices in lockstep by generating requests at each device, comparing the requests, and forwarding matching requests to a servicing node are described and claimed. A redundant execution system using the methods is also described and claimed.

Abstract: A method for dirty region logging of a file that includes receiving a request to open the file, determining each of a plurality of component files associated with the file, opening each of the plurality of component files, writing to a region of the at least one of the plurality component files, and updating a dirty region log (DRL) associated with the one of the plurality of component files to reflect the write to the region.

Abstract: A frame buffer for a microdisplay may be implemented with a repair algorithm that achieves desired uniformity in the frame buffer. Because the frame buffer and the display are tightly coupled, it is desirable to avoid providing unnecessary redundant elements which break up the uniformity of the overall integrated circuit. To this end, when a cell in the frame buffer is defective, a system to automatically address in its place an adjacent cell may be implemented. In one embodiment, control logic may address a column multiplexer to select an adjacent cell in an adjacent column in the same row to provide information in place of the defective cell in the frame buffer.

Abstract: Systems and methods for efficient processing of virtual hardware memory accesses to using runtime code patching. Virtual hardware memory accesses are processed by handling a program's OS-trapped memory exception and performing runtime patching on the program's code to bypass the OS-trapped memory exception mechanism. Program runtime patching comprises modifying function addresses in a program's function address table to redirect function calls to virtualization functions for processing virtual hardware memory accesses without triggering OS-trapped memory exceptions.

Abstract: A system for resolving address conflicts in a network. In an illustrative embodiment, the system includes an address-configuration module that is adapted to assign addresses to one or more devices. The one or more devices are connected to the network via device interfaces. An interface-monitoring module communicates with the address-configuration module. The interface-monitoring module is adapted to determine when an address conflict involving plural addresses occurs and to provide a signal in response thereto. A conflict-resolution module is adapted to selectively terminate one or more device interfaces associated with the plural addresses in response to the signal and based on the addresses and one or more predetermined precedence rules. In a more specific embodiment, the system further employs a user interface for facilitating selectively adjusting the precedence rules.

Abstract: Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical.

Abstract: A plurality of detectors can be evaluated to determine if more than one has been assigned the same address. Responsive thereto, such detectors could be identified for follow-up maintenance, or service.

Abstract: The present disclosure relates to a method for executing, by a processor, a program read in a program memory, comprising steps of: detecting a program memory read address jump; providing prior to a jump address instruction for jumping a program memory read address, an instruction for storing the presence of the jump address instruction; and activating an error signal if an address jump has been detected and if the presence of a jump address instruction has not been stored. The present disclosure also relates to securing integrated circuits.

Abstract: In an embodiment of the invention, if a microprocessor detects runaway of a CPU executing a program, it starts a recovery program. The runaway in the program execution is detected by monitoring accesses a non-implementation space in a program space. If the CPU accesses any address in the non-implementation space, the microprocessor sends an instruction to the CPU to execute a predetermined recovery program. Thereby, the microprocessor can detect and stop the runaway into the non-implementation space.

Abstract: Described are techniques for obtaining configuration information and conditionally executing a system call in accordance with a specified configuration state. A host issues a request for configuration information from a data storage system. The data storage system maintains a separate table of configuration information representing a configuration state of the data storage system. The host receives a response including a custom value indicating the current configuration state. The host may issue a request to the data storage system to conditionally execute a call if the data storage system is in a configuration state corresponding to the custom value.

Abstract: When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is sent to a CPU, while the transaction is finished on the IO bus. To prevent a transaction between IO devices from gaining access to any resource in another logical partition, one access permission bit is provided for each combination of all the IO devices, and the access is permitted only when the bit has a predetermined value. A reset signal is provided by IO slot so that only an IO slot allocated to a specific logical partition can be reset without affecting any other logical partition. A transaction issued from an IO device in one logical partition is prevented from gaining access to a resource in another logical partition, while proper error handling can be performed.

Abstract: Method and systems are described for testing an address line inter-coupling a processor and a memory. The contents of a first address in the memory are initially compared with the contents of a second address in the memory, wherein each of the first and second addresses are addressable in the memory by a different value applied on the address line. If the contents of the first and second addresses match, the contents of either one of the first and second addresses are changed, and a subsequent comparison of the contents of the first and second memory addresses is performed. If the second comparison determines that contents of the first and second memory address still match, then a fault condition associated with the address line is identified.

Abstract: Methods for synchronously transmitting control data from a first device to a second device in a streaming data network and for transferring non-addressed data through a streaming data network are disclosed. A first device may insert an identifier identifying a second device into data packets transmitted over a streaming data network. A first acknowledgement may be received from the second device at the first device. At least a portion of the control data may be inserted into the data packets at least until a second acknowledgement is received at the first device. The previous step may be repeated with additional portions of the of the control data until all control data has been transmitted to the second device. The identifier may then be removed from the data packets at least until a third acknowledgment is received at the first device.

Abstract: The network communication system is capable of communicating with many internal units at high speed, improving reliability of the system and decreasing a production cost and a development cost. The network communication system comprises a plurality of control units respectively connected to internal LANs, which connect internal units mutually. Each of the control units includes: a port opening/closing unit for selectively setting the control unit in an open state, in which the control unit acts as the unit having a common IP address of the control units with respect to the external network, or in a close state, in which an access to the control unit from the external network is prohibited; and a unit for solving the address duplication, which sets the control unit in the close state and changes the network address of the corresponding internal LAN so as to solve the address duplication. One of the control units is set in the open state, and the rest of the control units is set in the close state.

Abstract: A memory 2 is formed having an array of memory cells 4 arranged in rows 14. An address decoder 6 generates a word line signal WL in response to an input address to select one of the rows of memory cells for access. The word line signal also accesses address identifying data associated with the row of memory cells being accessed. This address identifying data is compared with the input address by fault detection circuitry 10. If a mismatch is detected, then this indicates a fault within the address decoder 6.

Abstract: A method, computer program product, and distributed data processing system that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to validate that a direct memory access address referenced by an incoming I/O transaction that was initiated through a memory mapped I/O operation are associated with a virtual adapter or virtual resource that is referenced by the incoming memory mapped I/O operation is provided. Specifically, the present invention is directed to a mechanism for sharing conventional PCI (Peripheral Component Interconnect) I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications. A single physical I/O adapter validates that one or more direct memory access addresses referenced by an incoming I/O transaction initiated through a memory mapped I/O operation are associated with a virtual adapter or virtual resource that is referenced by the incoming memory mapped I/O operation.

Abstract: In a data processing system, in order to provide its operating system with a better mechanism to identify and track addressing errors with a high potential to cause a storage overlay, it is first determined whether or not, a program interrupt has occurred. It is next determined whether or not this interrupt involves or occurs as a result of an address translation. It is then determined whether or not, the instruction involved calls for an update of storage. If it is determined that all three of these conditions are satisfied, then a flag is set in an area of storage accessible to the operating system so that it may provide a more specific event monitoring record.

Abstract: A cache memory device that includes a cache which stores data and tag information specifying an address of stored data, includes a detection unit that detects an error by reading out the tag information when a writing/readout request of desired data occurs to the cache, a search unit that searches the tag information for an address of the desired data when no error is detected in the tag information as a result of error detection by the detection unit, a memory unit that stores an address of data that is to be replaced by the desired data, the address being contained in the tag information, when the address of the desired data is not contained in the tag information as a result of search by the search unit, and a control unit that requests an external unit to replace data with a use of the address stored by the memory unit.

Abstract: A memory controller carries out error detection on a wide range of area of a memory cell array, which includes not only readout addresses but also non-readout addresses. Thus, by carrying out error detection at an address at which an error occurs without accessing the address for readout, it is possible to detect occurrence of an error at the address. Accordingly, it is possible to prevent a “read disturb phenomenon” in which repetition of access to a readout address for readout may probably cause an error at a non-readout address other than the readout address.