Storage Content Error Patents (Class 714/54)
  • Patent number: 10380029
    Abstract: A method of managing memory includes generating a page pool by aligning a plurality of pages of a memory; when a request to store first data is received, allocating a destination page corresponding to the first data using a page pool; and updating a page table using information about the allocated destination page.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: August 13, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Don Lee, Min-Kyu Jeong, Jong-Pil Son
  • Patent number: 10338999
    Abstract: Confirming memory marks indicating an error in computer memory including detecting, by memory logic responsive to a memory read operation, an error in at a memory location; marking, by the memory logic in an entry in a hardware mark table, the memory location as containing the error, the entry including one or more parameters for correcting the error; and retrying, by the memory logic, the memory read operation, including: responsive to again detecting the error in the memory location, determining whether the error is correctable at the memory location using the parameters included in the entry; and if the error is correctable at the memory location using the one or more parameters included in the entry, confirming the error in the entry of the hardware mark table.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: July 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: John S. Dodson, Marc A. Gollub, Warren E. Maule, Brad W. Michael
  • Patent number: 10310935
    Abstract: Embodiments of the present invention provide systems and methods for dynamically modifying data scrub rates based on RAID analysis. The method includes determining a grouping for an array based on a temperature for the array, a configurable threshold temperature range for the array, and an I/O distribution of the array. The method further includes modifying the data scrub rate for the array based on the grouping.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Xue Dong Gao, Yang Liu, Mei Mei, Hai Bo Qian
  • Patent number: 10296405
    Abstract: A memory system may be provided. The memory system may include a memory apparatus including a plurality of memory cells. The memory system may include and a controller configured to control a write operation and a read operation with respect to the memory apparatus, detect an error occurrence position by performing the write operation and the read operation on a corresponding region of the memory apparatus in which an error occurs based on error occurrence address information generated in the read operation while changing a level of data to be written, and determine a type of error based on the detected error occurrence position.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: May 21, 2019
    Assignee: SK hynix Inc.
    Inventors: Jung Hyun Kwon, Sung Eun Lee, Jae Sun Lee, Jingzhe Xu
  • Patent number: 10261828
    Abstract: A transactional memory environment includes a first processor and a processor set. The processor set includes one or more additional processors. In the transactional memory environment, a computer-implemented method includes sending a transaction query from the first processor to all processors in the processor set, and generating an indication by each additional processor in the processor set. The indication includes whether the additional processor is executing a current transaction. The computer-implemented method further includes sending the indication from each additional processor in the processor set to the first processor and proceeding, by the first processor, based on the indication. A corresponding computer program product and computer system are also disclosed.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Timothy J. Slegel
  • Patent number: 10204008
    Abstract: A memory module includes an error correction logic to provide data error protection for data stored in the memory module. The error correction logic is selectively controllable between an enabled state and a disabled state. Data stored in the memory module is without error protection provided by the memory module if the error correction logic is in the disabled state.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: February 12, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregory Trezise, Andrew Hana
  • Patent number: 10198196
    Abstract: Various embodiments of the present disclosure provide a method and apparatus for monitoring health condition of a hard disk by obtaining full-dimensional characteristics associated with the hard disk, wherein the full-dimension characteristics comprise at least two of: hard disk performance information, data integrity information, input/output I/O correctness information, and a hard disk Self-Monitoring Analysis and Reporting Technology S.M.A.R.T. report, and determining the health condition of the hard disk based on the full-dimension characteristics.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: February 5, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Man Lv, Chris Zirui Liu, Colin Yong Zou
  • Patent number: 10176107
    Abstract: Techniques described herein generally include methods and systems related to dynamic cache-sizing used to reduce the energy consumption of a DRAM cache in a chip multiprocessor. Dynamic cache sizing may be performed by adjusting the refresh interval of a DRAM cache or by combining way power-gating of the DRAM cache with adjusting the refresh interval.
    Type: Grant
    Filed: March 29, 2014
    Date of Patent: January 8, 2019
    Assignee: Empire Technology Development LLC
    Inventor: Yan Solihin
  • Patent number: 10169383
    Abstract: Various embodiments for scrubbing data within a data storage subsystem are disclosed. An event is detected in which utilization of the data storage subsystem has fallen below a dynamically adjusted threshold value. A storage element is selected from a plurality of storage elements within the data storage subsystem. Data modifications are temporarily suspended on the selected storage element while simultaneously maintaining read access to the selected storage element. A scrubbing operation is performed on the selected storage element after the temporary designation, wherein the scrubbing operation automatically initiates when a quantity of active data to be scrubbed reaches a predetermined quantity threshold, the predetermined quantity threshold of active data comprising a total threshold number of bytes or blocks corresponding to a greatest frequency of access thereof.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Gregory T. Kishi
  • Patent number: 10089167
    Abstract: Embodiments of the invention provide a method, system and computer program product for log file reduction according to problem space topology. A method for log file reduction according to problem space topology can include receiving a fault report for a fault in a solution executing in memory of one or more computers of a computer data processing system. The method further can include extracting references to at least two resources of the computer data processing system from the fault report. The method yet further can include filtering a set of all log files for the computer data processing system to only a subset of log files related to the at least two resources. Finally, the method can include displaying the subset of log files in a log file analyzer.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: October 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Matthew Duggan, Kristian Stewart, Zhenni Yan
  • Patent number: 10083070
    Abstract: Embodiments of the invention provide a method, system and computer program product for log file reduction according to problem space topology. A method for log file reduction according to problem space topology can include receiving a fault report for a fault in a solution executing in memory of one or more computers of a computer data processing system. The method further can include extracting references to at least two resources of the computer data processing system from the fault report. The method yet further can include filtering a set of all log files for the computer data processing system to only a subset of log files related to the at least two resources. Finally, the method can include displaying the subset of log files in a log file analyzer.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: September 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Matthew Duggan, Kristian Stewart, Zhenni Yan
  • Patent number: 10025808
    Abstract: Systems and methods for compacting change logs using file content location identifiers.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: July 17, 2018
    Assignee: Red Hat, Inc.
    Inventor: Anand Avati
  • Patent number: 10002091
    Abstract: A system comprising first and second redundant controller modules, each controller module comprising mode management circuitry configured to identify whether the corresponding controller module operates in a master mode or a slave mode. The mode management circuitry in each controller module is configured to couple to the mode management circuitry in the other controller module. The mode management circuitries in the controller modules are configured to collectively operate so that one of the controller modules is assigned the master mode and the other of the controller modules is assigned the slave mode. At least one of the mode management circuitries in the controller modules is configured to assign the master mode to the corresponding controller module based on a takeover signal when the mode management circuitry in the corresponding controller module is ready for use.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: June 19, 2018
    Assignee: Honeywell International Inc.
    Inventors: Zhi Yang, Jie Lv, Lei Zou
  • Patent number: 9977720
    Abstract: A method includes: causing at least three processors to perform a same process; extracting, when one of the at least three processors outputs different operational information generated by performing the same process, majority processors with which outputted operational information are the same and a minority processor with which different operational information is outputted; and controlling one of the two redundant processors to output a result of the same process.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: May 22, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Koki Fujimoto
  • Patent number: 9965345
    Abstract: An apparatus for controlling programming of a non-volatile memory including at least one block partitioned into a plurality of physical sections, each of the physical sections including a plurality of memory cells, the apparatus including a controller configured to access a table including information corresponding to individual ones of the plurality of physical sections. The controller is configured to identify a first programming method for a first physical section of the plurality of physical sections and identify a second programming method for a second physical section of the plurality of physical sections according to information in the table corresponding to the first and second physical sections. The controller is also configured to program the first and second physical sections according to the first and second programming methods for the first and section physical sections, respectively.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: May 8, 2018
    Assignee: Macronix International Co., Ltd.
    Inventor: Yi Chun Liu
  • Patent number: 9953042
    Abstract: Among other things, in one aspect, in general, a system for managing data in a data storage system includes a plurality of index nodes each storing a map of entries, each entry of the map including an identifier corresponding to a particular portion of data stored in the data storage system, and metadata indicating a location where the particular portion of data is stored in the data storage system, and one or more supernodes configured to return an identification of an index node that recently submitted a request for a particular identifier associated with at least one of the portions of data.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: April 24, 2018
    Assignee: Red Hat, Inc.
    Inventors: Jonathan Coburn, Michael Fortson
  • Patent number: 9905314
    Abstract: A storage module and method for datapath bypass are disclosed. In one embodiment, a storage module begins to perform a read operation that reads a set of code words from the memory and attempts to perform an error detection and correction operation on one of the read code words. In response to determining that the code word has an uncorrectable error, the storage module reads the other code words in the set but bypasses the error detection and correction operation on those other code words. The code word that had the uncorrectable error and the other code words are re-read, wherein at least the code word with the uncorrectable error is re-read with a different read condition. The storage module then attempts to perform the error detection and correction operation on the re-read code words. Other embodiments are provided.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: February 27, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Daniel E. Tuers, Yoav Weinberg, Yuri Ryabinin
  • Patent number: 9892136
    Abstract: Various embodiments for scrubbing data within a data storage subsystem are disclosed. According to one embodiment, a method is provided for scrubbing data of a storage element within a data storage subsystem, the method comprising: selecting a storage element from the plurality of storage events; determining that a quantity of active data has reached a predetermined quantity threshold; and temporarily suspending data modifications on a portion of the selected storage element while maintaining read access to the selected storage element in response to the determination.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: February 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Gregory T. Kishi
  • Patent number: 9875151
    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: January 23, 2018
    Assignee: Rambus Inc.
    Inventors: Yuanlong Wang, Frederick A. Ware
  • Patent number: 9740555
    Abstract: Techniques for incrementally increasing media size in data storage systems using grid encoded data storage techniques are described herein. A grid of shards is created where each shard of the grid of shards has a first index, a second index and each shard also has an associated storage device configured with a storage capacity that is large enough to store the largest set of data on a shard. Upon determining to replace the storage devices of the grid with storage devices that have a different storage capacity, the storage devices can be incrementally replaced within the grid by first padding each shard of the grid of shards with a set of data values, replacing a data shard storage device with a device of the different storage capacity, and replacing a set of derived shard storage devices with devices of the different storage capacity.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: August 22, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Bryan James Donlan, Colin Laird Lazier
  • Patent number: 9727413
    Abstract: A method, computer-readable storage media, and a system are provided for managing a scrub. The method may include detecting a trigger for the scrub. The trigger may be based upon a metric of a memory unit. The method may further include scrubbing the memory unit based upon the detection of the trigger.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: August 8, 2017
    Assignee: International Business Machines Corporation
    Inventors: Edgar R. Cordero, Gary A. Tressler, Diyanesh B. Vidyapoornachary
  • Patent number: 9690520
    Abstract: A method begins by a processing module of a dispersed storage network (DSN) receiving a DSN retrieval request regarding a data object and performing a scoring function using properties of the DSN retrieval request and properties of DSN memory of the DSN to produce a storage scoring resultant. The method continues with the processing module identifying a set of primary storage units based on the storage scoring resultant and sending a set of retrieval requests to the set of primary storage units. When a primary storage unit does not provide a favorable response, using the storage scoring resultant to identify an alternative storage unit. When the alternative storage unit is identified, sending a corresponding retrieval request to the alternative storage unit.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: June 27, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gary W. Grube, Jason K. Resch
  • Patent number: 9570191
    Abstract: A method of managing a memory in an electronic device is provided that includes calculating an indication of remaining life of a memory component that is used as a swap space by the electronic device; and adjusting the use of the memory component as a swap space based on the indication of remaining life, wherein the adjusting includes one of: (i) reducing a rate at which data is swapped in and out of the memory component, and (ii) discontinuing the use of the memory component as a swap space.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: February 14, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Tae Kim, Sun-Ae Seo, Dong-Jun Shin, Hee-Sub Shin
  • Patent number: 9552247
    Abstract: Some embodiments are directed to a method, corresponding system, and corresponding apparatus for detecting unexpectedly high latency, due to excessive retries of a given storage device of a set of storage devices. Some embodiments may comprise a processor and associated memory. Some embodiments may monitor one or more completion time characteristics of one or more accesses between the given storage device and one or more host machines. Some embodiments may then compare the one or more completion time characteristics with a given threshold. As a result of the comparison, some embodiments may report, by the one or more host machines, at least one error associated with the given storage device. The error may be unreported by the set of storage devices.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: January 24, 2017
    Assignee: Dell Products, LP
    Inventors: Robert B. Jacoby, Giang L. Nguyen
  • Patent number: 9535619
    Abstract: An information handling system and method provide for receiving a request to remove a selected physical disk from a disk group realizing a virtual disk in a redundant array data storage subsystem, determining whether removal of the selected physical disk is feasible, and, when feasible, removing the selected physical disk from the disk group without deleting the virtual disk realized by the disk group and reconstructing the virtual disk to be realized by the disk group using only the proposed number of physical disks, wherein the proposed number of physical disks is less than an initial number of physical disks of the disk group.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: January 3, 2017
    Assignee: DELL PRODUCTS, LP
    Inventors: Neeraj Joshi, Sandeep Agarwal, Deepu S. Sreedhar M
  • Patent number: 9520899
    Abstract: A method is provided for generating a maximized linear correcting code from a base linear correcting code, the base correcting code and the maximized linear correcting code being associated with one and the same parity matrix H, the matrix being used to generate syndromes, the syndromes being used for decoding code words. The method comprises a step of identifying the syndromes unused for decoding the base linear correcting code, a step of identifying the errors that can affect the code words and make it possible to obtain the unused syndromes when a code word is multiplied by the matrix H and a step of selecting a unique error for each unused syndrome from among the identified errors, the error being called additional error.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: December 13, 2016
    Assignee: COMMISARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Samuel Evain, Valentin Gherman
  • Patent number: 9472275
    Abstract: A memory device and a method of operating the memory device are provided for performing a read-retry operation. The method of operating the memory device includes starting a read-retry mode, reading data of multiple cell regions using different read conditions, and setting a final read condition for the cell regions according to results of data determination operations on data read from the cell regions.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: October 18, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Kook Park, Young-Hoon Oh, Dae-Seok Byeon, Yong-Kyu Lee, Hyo-Jin Kwon
  • Patent number: 9459977
    Abstract: A data processing system includes a processor configured to execute processor instructions and a memory. The memory has a data array and a checkbit array wherein each entry of the checkbit array includes a plurality of checkbits and corresponds to a storage location of the data array. The system includes error detection/correction logic configured to, during normal operation, detect an error in data access from a storage location of the data array using the plurality of checkbits in the entry corresponding to the storage location. The system further includes debug logic configured to, during debug mode, use a portion of the plurality of the checkbits in the entry corresponding to the storage location to generate a breakpoint/watchpoint request for the processor.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: October 4, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: William C. Moyer
  • Patent number: 9448886
    Abstract: Methods and systems for managing and locating available storage space in a system comprising data files stored in a plurality of storage devices and configured in accordance with various data storage schemes (mirroring, striping and parity-striping). A mapping table associated with each of the plurality of storage devices is used to determine the available locations and amount of available space in the storage devices. The data storage schemes for one or more of the stored data files are changed to a basic storage mode when the size of a new data file configured in accordance with an assigned data storage scheme exceeds the amount of available space. The configured new data file is stored in accordance with the assigned data storage scheme in one or more of the available locations and the locations of the new data file are recorded.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: September 20, 2016
    Inventor: Gary Stephen Shuster
  • Patent number: 9450614
    Abstract: A memory system includes a memory module that supports error detection and correction (EDC) in a manner that relieves a memory controller or processor of some or all of the computational burden associated with EDC. Individual EDC components perform EDC functions on subsets of the data, and share data between themselves using relatively short, fast interconnections.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: September 20, 2016
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Scott C. Best
  • Patent number: 9411739
    Abstract: Systems, apparatuses, and methods for improving transactional memory (TM) throughput using a TM region indicator (or color) are described. Through the use of TM region indicators younger TM regions can have their instructions retired while waiting for older TM regions to commit. A copy-on-write (COW) buffer may be used to maintain a mapping from checkpointed architectural registers to physical registers, wherein the COW buffer maintains a plurality of register checkpoints for a plurality of TM regions by marking separations between TM regions using pointers, a first pointer to identify a position in the COW buffer of the last committed instruction, a retirement pointer to identify a boundary between a youngest TM region and a currently retiring position.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: August 9, 2016
    Assignee: Intel Corporation
    Inventors: Omar M. Shaikh, Ravi Rajwar, Paul Caprioli, Muawya M. Al-Otoom
  • Patent number: 9378008
    Abstract: Embodiments of the present disclosure involve a method for creating, applying, and removing a software fix for an application without terminating the application. To create the fix, the system converts an unresolved internal reference in a source code section to an external imported reference, generates a header file which includes a re-definition of the external imported reference, and generates a binary representation for the fix by compiling the source code section using the generated header file and linking the complied object. To apply the fix, the system loads the binary representation into a virtual address space, places a long jump operator in a compiler-generated padding prior to the start of an affected function, and replaces a no-operation prologue at the start of the function with a short jump operator in an atomic write operation. To remove the fix, the system replaces the short jump operator with the no-operation prologue, removes the long jump operator, and unloads the software fix.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: June 28, 2016
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Ian Druch, Sujatha Srinivasa Gopalan
  • Patent number: 9298390
    Abstract: A first volume comprising a plurality of blocks stored in a first location is accessed. A plurality of hash values representing the plurality of blocks is stored. The plurality of blocks is copied to a second volume stored in a second location, generating a copied volume. The copied volume is verified based on the plurality of hash values. In one embodiment, the first volume is altered, after the plurality of hash values is stored. Altering the first volume may include changing data in a selected one of the plurality of blocks. The first volume may be altered during copying of the plurality of blocks to the second volume.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: March 29, 2016
    Assignee: Cirrus Data Solutions, Inc.
    Inventors: Wai T. Lam, Wayne Lam, Yik Shum Tam
  • Patent number: 9280458
    Abstract: A technique reclaims memory pages in a virtualization platform. The technique involves receiving, by a virtual machine of the virtualization platform, an inflate command which directs a balloon driver of the virtual machine to inflate. The technique further involves issuing, by the virtual machine and in response to the inflate command, a sweep request to a hypervisor. The sweep request directs the hypervisor to (i) perform a scan of memory pages allocated to the virtual machine for a predetermined pattern of characters, (ii) de-allocate memory pages having the predetermined pattern of characters from the virtual machine (e.g., zeroed pages), the de-allocated memory pages including super pages and regular pages, and (iii) update a list of memory page mappings to reflect the de-allocated memory pages. The technique further involves completing balloon driver inflation after the list of memory page mappings is updated.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: March 8, 2016
    Assignee: Citrix Systems, Inc.
    Inventor: Paul Durrant
  • Patent number: 9225780
    Abstract: A method of writing data to a distributed file system including a file system client, a server and a storage resource target, includes generating, on the client, a write request including a byte stream to be written to the storage resource target; formatting, on the client, the byte stream into sectors in accordance with the T10 protocol, the sectors including a data field and a protection information field, the protection information field including a guard field, an application field and a reference field; computing, on the client, checksum data for the guard field; sending, across a network, the data and the protection information to the server; verifying, in T10-capable hardware on the server, the checksum data for the guard field; verifying, on the storage resource target, the checksum data for the guard field; and storing the data on the storage resource target.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: December 29, 2015
    Assignee: Xyratex Technology Limited
    Inventors: Peter J. Braam, Nathaniel Rutman
  • Patent number: 9208182
    Abstract: A method and system for scrubbing data within a data storage subsystem is disclosed. According to one embodiment, a method is provided for scrubbing data of a storage element within a data storage subsystem. In the described method embodiment, a request to access the storage element is processed utilizing a first processing module and access permission metadata associated with the storage element. A data scrub process is concurrently performed utilizing a second processing module by modifying the access permission metadata and validating data of the storage element substantially simultaneously with the processing.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: December 8, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Gregory T. Kishi
  • Patent number: 9110789
    Abstract: A method of applying an address space to data storage in a non-volatile solid-state storage is provided. The method includes receiving a plurality of portions of user data for storage in the non-volatile solid-state storage and assigning to each successive one of the plurality of portions of user data one of a plurality of sequential, nonrepeating addresses of an address space. The address range of the address space exceeds a maximum number of addresses expected to be applied during a lifespan of the non-volatile solid-state storage. The method includes writing each of the plurality of portions of user data to the non-volatile solid-state storage such that each of the plurality of portions of user data is identified and locatable for reading via the one of the plurality of sequential, nonrepeating addresses of the address space.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: August 18, 2015
    Assignee: Pure Storage, Inc.
    Inventors: John Hayes, Shantanu Gupta, John Davis, Brian Gold, Zhangxi Tan
  • Patent number: 9104337
    Abstract: Systems capable of transformation of logical data objects for storage and methods of operating thereof are provided. One method includes identifying among a plurality of requests addressed to the storage device two or more “write” requests addressed to the same logical data object, deriving data chunks corresponding to identified “write” requests and transforming the derived data chunks, grouping the transformed data chunks in accordance with the order the requests have been received and in accordance with a predefined criteria, generating a grouped “write” request to the storage device, and providing mapping in a manner facilitating one-to-one relationship between the data in the obtained data chunks and the data to be read from the transformed logical object. The method further includes obtaining an acknowledging response from the storage device, multiplying the obtained acknowledging response, and sending respective acknowledgements to each source that initiated each respective “write” request.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: August 11, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ori Shalev, Jonathan Amit
  • Patent number: 9098207
    Abstract: There is provided a system capable of transformation of logical data objects for storage and method of operating thereof. The method comprises: a) identifying among a plurality of requests addressed to the storage device two or more “write” requests addressed to the same logical data object; b) deriving data chunks corresponding to identified “write” requests and transforming the derived data chunks; c) grouping the transformed data chunks in accordance with the order the requests have been received and in accordance with a predefined criteria; d) generating a grouped “write” request to the storage device; and e) providing mapping in a manner facilitating one-to-one relationship between the data in the obtained data chunks and the data to be read from the transformed logical object.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: August 4, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ori Shalev, Jonathan Amit
  • Patent number: 9081697
    Abstract: A storage control apparatus receives a write request for a storage apparatus. When the storage control apparatus receives the write request, the storage control apparatus duplicates into a specific storage area, data stored in a storage area of the storage apparatus and parity data whose generation source is the data. The storage control apparatus determines whether one of the storage apparatuses is started up for which a writing process is executed in response to the write request. When the storage apparatus is re-started, the storage control apparatus writes the data duplicated in the specific storage area into the storage area of the duplication source of the storage apparatus and writes the parity data duplicated in the specific storage area into the storage area of the duplication source of the storage apparatus.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: July 14, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Hiroshi Sakurai
  • Patent number: 9047171
    Abstract: Systems and methods may provide for determining whether a memory access request is error-tolerant, and routing the memory access request to a reliable memory region if the memory access request is error-tolerant. Moreover, the memory access request may be routed to an unreliable memory region if the memory access request is error-tolerant. In one example, use of the unreliable memory region enables a reduction in the minimum operating voltage level for a die containing the reliable and unreliable memory regions.
    Type: Grant
    Filed: September 29, 2012
    Date of Patent: June 2, 2015
    Assignee: Intel Corporation
    Inventors: Zhen Fang, Shih-Lien Lu, Ravishankar Iyer, Srihari Makineni
  • Patent number: 9043660
    Abstract: Embodiments relate to a computer implemented information processing system, method and program product for data access. The information processing system includes a data store having a top tier store and at least another tier store with the top tier store including a counter for each entry of a symbol and another tier store including a representative frequency value defined for the another tier store. A sorter is also provided configured to sort the symbol in the top tier store and the another tier stores according to a value generated in the counter for the assessed symbol. The said sorter is also configured to restore entry of the symbol in the top tier store, in response to a symbol having moved from said top tier store to another tier store, by using the representative frequency value defined for said another store to which said symbol was moved.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Takashi Imamichi, Teruo Koyanagi, Raymond H. P. Rudy, Yuya Unno
  • Publication number: 20150143164
    Abstract: Clustered storage systems and methods are presented herein. One clustered storage system includes a logical volume comprising first and second pluralities of storage devices. The first plurality of storage devices is different from the second plurality of storage devices and includes at least the same data as the second plurality of devices. The storage system also includes a first storage node operable to process first I/O requests to the first plurality of storage devices and a second storage node communicatively coupled to the first storage node and operable to process second I/O requests to the second plurality of storage devices. An I/O request of the first I/O requests initiates a redirection condition that the first storage node detects. Then, based on the redirection condition, the first storage node directs the second storage node to process data of the I/O request.
    Type: Application
    Filed: November 20, 2013
    Publication date: May 21, 2015
    Applicant: LSI CORPORATION
    Inventors: Sridhar Rao Veerla, Naveen Krishnamurthy
  • Patent number: 9037927
    Abstract: Events which have occurred in storage systems can be managed easily regardless of complexity of a storage configuration. An event notification system 1 includes: an event notifying client 133 for detecting the occurrence of an event(s) in volumes of a storage system 10; a management application server 20 for storing information about the occurred event as setting/failure information 21; and an event information aggregation server 30 for creating and managing event information 31 including an event key 311 for associating the occurred event with the setting/failure information 21. When the event information aggregation server 30 in such an event notification system 1 notifies an administrator terminal 50 of the event key 311 and an administrator selects the event key 311, the management application server 20 has the administrator terminal 50 display an event browse screen 52 indicating the relativity of a volume, in which the event occurred, to a volume in which a related event occurred.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: May 19, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Toshimichi Kishimoto, Shinichiro Kanno
  • Patent number: 9026866
    Abstract: The present disclosure relates to some aspects relate to a method for detecting stack memory corruption. In some embodiments, the method comprises determining an expected memory range of a data element that is to be written to a stack memory by tracking changes to a stack pointer. The determined memory range is stored in a stack object database. Upon receiving a stack memory access related instruction (e.g., LOAD/STORE instruction or arithmetic instruction operating on memory addresses) to write data to the stack memory, an address of the memory location to be accessed is determined. If the address falls within the expected memory range, no stack corruption is present. However, if the address falls outside of the expected memory range, stack corruption is present. Therefore, the present method provides for real time detection of corruption (e.g., overrun and underrun errors) in stack memory.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: May 5, 2015
    Assignee: Infineon Technologies AG
    Inventor: Prakash Kalanjeri Balasubramanian
  • Patent number: 9021316
    Abstract: A circuit and method of detecting a fault attack in a circuit includes a plurality of registers each identified by an address. The method includes storing in a memory the address present on an address bus during a write operation to one of said registers. In response to a first alert signal indicating that the data stored by a first of said registers has been modified, comparing the address identifying said first register with said stored address.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Frederic Bancel
  • Patent number: 9003242
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array including a plurality of memory cells, a first register configured to store data of the memory cells, and a sequence control circuit configured to control the memory cell array and the first register. In at least a data read operation of the memory cells, the sequence control circuit reads out, from the memory cell array, data including flag information representing whether the number of failed bits is in an allowable range.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: April 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Naoya Tokiwa
  • Publication number: 20150095722
    Abstract: A process for determining a problematic condition while running software includes: loading a first pattern data set having a symptom code module, a problematic condition determination module, and a set of responsive action module(s), generating a runtime symptom code in response to a first problematic condition being caused by the running of the software on the computer, determining that the runtime symptom code matches a symptom code corresponding to the first pattern data set, determining that the first problematic condition caused the generation of the runtime symptom code, and taking a responsive action from a set of responsive action(s) that corresponds to the first problematic condition.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Applicant: International Business Machines Corporation
    Inventors: Anoop G. M. Ramachandra, Murali K. Surampalli
  • Publication number: 20150095723
    Abstract: Disclosed is a detection system for detecting fail block using logic block address and data buffer address in a storage tester, which is capable of comparing data read from SSD test without expected data buffer. The system comprises a device driver for controlling HBA; a request processor for reading the request to Root Complex and transmitting the result to a data engine; and the data engine for generating data to be transmitted to SSD and comparing the read data.
    Type: Application
    Filed: August 7, 2014
    Publication date: April 2, 2015
    Applicant: UNITEST INC.
    Inventor: Young Myoun HAN
  • Publication number: 20150089306
    Abstract: Mechanisms are provided for providing an early warning of an error state of a remote direct memory access (RDMA) resource to a userspace application. The mechanisms detect, using kernelspace logic, an error event having occurred, and perform a write operation to write an error state value to a userspace shared memory state data structure indicating the RDMA resource to be in an error state. The mechanisms detect, using userspace logic, the RDMA resource being in an error state by reading the error state value from the userspace shared memory state data structure in response to a userspace application attempting to perform a RDMA operation using the RDMA resource. In addition, the mechanisms initiate, by the userspace application, an operation to tear down the RDMA resource in response to detecting the RDMA resource being in the error state.
    Type: Application
    Filed: September 26, 2013
    Publication date: March 26, 2015
    Applicant: International Business Machines Corporation
    Inventors: Omar Cardona, Matthew R. Ochs, Vikramjit Sethi