Abstract: Aspects of the disclosed technology include techniques and mechanisms for an efficient error correction coding scheme that can detect and correct data errors that may occur in a memory. In general, the scheme comprises segmenting the data that would be transferred as part of a data request into different parts and applying error correction codes to the separate parts.

Abstract: Errors in big datasets can be automatically detected and output in an interactive graphical user interface (GUI) according to some examples described herein. In one such example, a system includes processing nodes for receiving processing tasks associated with analyzing a dataset (e.g., a big dataset). In response to receiving the processing tasks, the processing nodes can each execute a data-processing module to analyze entries in the dataset based on a predefined set of rules to determine if the entries include one or more types of errors. The data-processing module can then generate processing results indicating whether the entries include at least one type of error. The system can further include a GUI module that is executable to generate a GUI based on the processing results, where the GUI can provide insights about the types of errors present in the dataset for use in resolving said errors.

Abstract: A method for operating a memory is provided, including, for example, obtaining a set of read voltages, each of which can include an initial voltage value and an offset voltage value with a certain offset relative to the initial voltage value. The initial voltage value in each of the set of read voltages can be a preset read voltage for distinguishing two adjacent memory states of memory cells of the memory. The operating method can further include performing read operations respectively based on the initial voltage values and the offset voltage values, obtaining the quantity of memory cells in which a read result corresponding to each voltage value meets set conditions, determining a difference between the two quantities corresponding to every two adjacent voltage values belonging to the same set of read voltages, and determining an optimal read voltage for distinguishing the two adjacent memory states based on the difference.

Abstract: A memory controller includes an interface and a processor. The interface is configured to communicate with a plurality of memory cells. The processor is configured to, using multiple Read Thresholds (RTs) positioned between adjacent Programming Voltages (PVs), produce (i) a base parametric model of Threshold Voltage Distributions (TVDs) associated with the PVs, and (ii) auxiliary information that depends on the RTs and on the base parametric model, to read a group of the memory cells using the RTs to produce multiple readouts, the threshold voltages of the memory cells in the group are distributed in accordance with actual TVDs, to derive from the base parametric model an actual parametric model, based on the multiple readouts and on the auxiliary information, and determine a readout parameter based on the actual parametric model, and to perform a read-related operation using the readout parameter.

Abstract: The technology disclosed herein may detect, avoid, or protect against “use after free” or “double free” programing logic errors. An example method may involve: receiving, by a processing device, a memory allocation request; identifying a physical memory address referencing a chunk of memory; identifying a security parameter specifying a number of virtual memory addresses comprised by a set of memory addresses that are mapped to the identified physical memory address; generating a plurality of pointers to the chunk of memory, wherein each pointer of the plurality of pointers references a corresponding virtual memory address of the set of virtual memory addresses; determining a sequential number assigned to the memory allocation request; selecting, among the plurality of pointers, a pointer corresponding to the sequential number; providing the pointer in response to the memory allocation request; and updating pointer validation data indicating validity of the pointer.

Abstract: A method comprises generating, for a cacheline, a first tag and a second tag, the first tag and the second tag generated as a function of user data stored and metadata in the cacheline stored in a first memory device, and a multiplication parameter derived from a secret key, storing the user data, the metadata, the first tag and the second tag in the first cacheline of the first memory device; generating, for the cacheline, a third tag and a fourth tag, the third tag and the fourth tag generated as a function of the user data stored and metadata in the cacheline stored in a second memory device, and the multiplication parameter; storing the user data, the metadata, the third tag and the fourth tag in the corresponding cache line of the second memory device; receiving, from a requesting device, a read operation directed to the cacheline; and using the first tag, the second tag, the third tag, and the fourth tag to determine whether a read error occurred during the read operation.

Abstract: A device includes a match element that includes a first data input configured to receive a first result, wherein the first result is of an analysis performed on at least a portion of a data stream by an element of a state machine. The match element also includes a second data input configured to receive a second result, wherein the second result is of an analysis performed on at least a portion of the data stream by another element of the state machine. The match element further includes an output configured to selectively provide the first result or the second result.

Abstract: The present technology relates to a storage device. According to the present technology, a memory controller controlling a memory device including a plurality of memory blocks may include an operation controller and a lifetime information controller. The operation controller may control the memory device to receive a write request from a host and perform a write operation on a selected memory block among the plurality of memory blocks. The lifetime information controller may generate lifetime information including a lifetime level of the selected memory block based on an erase and write count of the selected memory block.

Abstract: From among physical storage devices (PSDs) of a storage system, a set of two or more of the PSDs that are eligible for scrubbing may be determined; and from among the set, a relative eligibility of the PSDs may be determined. Conformance prediction analysis may be applied to determine the set and the relative eligibility of PSDs of the set. The conformance prediction analysis may determine a scrubbing eligibility classification (e.g., label), and a confidence value for the classification, which may serve as the relative eligibility of the PSD. The eligible PSDs may be ranked in an order according to determined confidence values, and may be further classified according to such order. The future workload of the storage system may be forecasted, and the scrubbing of PSDs may be scheduled based on the forecasted workload of the system and the relative eligibilities of the set of PSDs.

Abstract: A controller of a non-volatile memory detects errors in data read from a particular physical page of the non-volatile memory. Based on detecting the errors, the controller performs a read voltage threshold calibration for a page group including the particular physical page and a multiple other physical pages. Performing the read voltage threshold calibration includes calibrating read voltage thresholds based on only the particular physical page of the page group. After the controller performs the read voltage threshold calibration, the controller optionally validates the calibration. Validating the calibration includes determining whether bit error rates diverge within the page group and, if so, mitigating the divergence. Mitigating the divergence includes relocating data from the page group to another block of the non-volatile memory.

Abstract: Methods, systems, and devices for a read algorithm for a memory device are described. When performing a read operation, the memory device may access a memory cell to retrieve a value stored by the memory cell. The memory device may compare a set of reference voltages with a signal output by the memory cell based on accessing the memory cell. Thus, the memory device may determine a set of candidate values stored by the memory cell, where each candidate value is associated with one of the reference voltages. The memory device may determine and output the value stored by the memory cell based on determining the set of candidate values. In some cases, the memory device may determine the value stored by the memory cell based on performing an error control operation on each of the set of candidate values to detect a quantity of errors within each candidate value.

Abstract: This disclosure describes how data supporting real-time reporting services can be cached during a log intake process. In particular, instead of caching all the log data being generated by an operational system, only the log data relevant to existing queries associated with the real-time reporting services are cached. In some embodiments, only particular metrics contained within the log data are stored for rapid access by the real-time reporting services.

Abstract: Methods, systems, and devices for memory data correction using multiple error control operations are described. A single command may be received to correct an error detected in data stored by a memory array. A first error control operation and a second error control operation may be implemented based on the single command. The first error control operation may be performed on the data stored by the memory array using one or more different reference voltages to read the data. The error may be determined to remain in the data after performing the first error control operation. The second error control operation may then be performed on the data stored by the memory array. The second error control operation may use one or more voltage distributions associated with the memory cells of the memory array.

Abstract: The present invention relates to a modular architecture for a resilient extensible SmallSat (MARES) command and data handling (C&DH) device used in a spacecraft, the modular architecture which conforms to a 1U CubeSat board area form factor, including: a C&DH processor card disposed on a backplane of the form factor; a C&DH processor card disposed on a backplane of the form factor; a fault tolerant field programmable gate array (FPGA) disposed on the C&DH processor card, the FPGA including an embedded fault tolerant memory controller, and a soft-core processor which runs core flight software on a real-time executive for a multiprocessor operating system; and a C&DH auxiliary card disposed on the backplane and used in conjunction with the C&DH processor card, to provide processing capability for the spacecraft, the auxiliary card which contains peripheral interface drivers and read electronics for monitoring a health and safety of the spacecraft.

Abstract: A system includes first and second subsystems and a third processor. The first subsystem includes a first memory and a first processor. The first memory stores data, which includes metadata associated with transmitted metadata fields. The first processor transmits the data to the second subsystem. The second subsystem includes a second memory and a second processor. The second memory stores expected metadata fields. The second processor receives the data. The third processor determines that the first subsystem transmitted the data to the second subsystem and that a mismatch exists between the transmitted and expected metadata fields. In response, the third processor prevents the second subsystem from executing an application configured to process the data using the expected metadata fields. The third processor resolves the mismatch by modifying the expected metadata fields such that they correspond to the transmitted metadata fields and allows the second subsystem to execute the application.

Abstract: In a protective quorum service, during an initial period of normal operation in which a clustered pair of data storage nodes provide host I/O access to a data storage object and replicate write-type requests to each other, the nodes are first registered to the quorum service. Subsequently, based on the registration and in response to a first auto promote request from a first-requesting node, a success response is returned and the service enters an auto promoted condition, the success response indicating that the first-requesting node is to continue providing the host I/O access to the data storage object without write replication. In response to receiving a subsequent auto promote request from the other node when in the auto promoted condition, a failure response is returned indicating that the other node is to cease providing host I/O access to the data storage object.

Abstract: One embodiment provides a computer implemented method of for monitoring and upgrading a dual-flash device. The method includes performing an OS upgrade on a server; writing an upgraded OS to the dual-flash device; updating a grub.cfg file corresponding to the upgraded OS; and deleting old OS files from the dual-flash device.

Abstract: According to aspects of the present disclosure, systems and methods can be provided to recover from memory errors that occur during or following a virtual machine migration. Methods, computer program products and/or systems are provided for handling memory error that perform the following operations: (i) obtaining a memory address that triggered an uncorrected error on a first host associated with a virtual machine migration; (ii) computing a page associated with the memory address; (iii) determining if a copy of the page associated with the memory address is available on a second host associated with the virtual machine migration; (iv) obtaining data from the copy of the page on the second host; and (v) generating a new page on the first host with the data obtained from the second host.

Abstract: The present application discloses a method and apparatus for generating error reporting content of a deep learning framework, an electronic device and a readable storage medium, which relates to the field of deep learning technologies. An implementation solution adopted by the present application to generate error reporting content of a deep learning framework is: acquiring an error code and error information corresponding to the error code; generating an error file according to the error code and the error information corresponding thereto, and packaging the error file into the deep learning framework; running the deep learning framework, and in response to the deep learning framework receiving an error code returned by a third-party library when an error occurs in calling of a third-party library application programming interface (API), extracting, from the error file, error information corresponding to the received error code; and generating error reporting content according to the error information.

Abstract: A method for detecting a denial of service attach on a call center, the method including automated means for detecting at least one anomaly in calls made to the call center from at least one source, determining if a detected anomaly has a match in a historical file of previously detected anomalies, and filtering calls received from the at least one source if the detected anomaly does not have a match in the historical file of previously detected anomalies.

Abstract: A technique manages data within solid state device (SSD) storage. The technique involves, in response to writing data to a set of SSD storage components, consuming a set of recurring write quotas for the set of SSD storage components. Each recurring write quota identifies an amount of remaining usefulness for a respective SSD storage component, e.g., periodically allocated budgets for write operations based on measured (or counted) reliability and/or healthiness factors. The technique further involves, as the set of recurring write quotas are consumed, performing a set of quota evaluation operations to evaluate the set of recurring write quotas. The technique further involves, in response to a set of results from the set of quota evaluation operations, performing a set of remedial activities to control access to the data that was written to the set of SSD storage components.

Abstract: In an apparatus with transactional memory support circuitry, for a first type of transaction started using a first type of transaction start instruction, commitment of results of instructions executed speculatively following the first type of transaction start instruction are prevented until a transaction end instruction is reached. An abort is triggered when a conflict is detected between an address of a memory access from another thread and the addresses tracked for the transaction. For a second type of transaction started using a second type of transaction start instruction, an address of the read operation is marked as trackable whilst an address of a write operation is omitted from being marked as trackable. This allows an apparatus that supports transactional memory to also be used for multi-word address watching.

Abstract: A processing system includes a timer circuit and a processing circuit. The timer circuit is configured to generate a system time signal. The processing circuit is configured to receive the system time signal, detect whether the system time signal reaches or exceeds a given reference value, and start execution of a given processing operation in response to the detection. The timer circuit has associated an error code calculation circuit configured to compute a first set of error detection bits as a function of bits of the system time signal. The processing circuit has an associated error detection circuit configured to: compute a second set of error detection bits as a function of the bits of the system time signal received, compare the first set of error detection bits with the second set of error detection bits, and generate an error signal in response to the comparison.

Abstract: Embodiments are disclosed for managing heap metadata corruption. The techniques include detecting a metadata corruption error in a first heap disposed in a first region of memory. The techniques also include generating a second heap in a free memory region that is disposed beyond a break value address of a memory allocation system. The techniques further include updating a first entry for the first heap in a heap directory. Additionally, the techniques include generating a second entry for the second heap in the heap directory. The techniques also include processing a call to the memory allocation system for the first heap based on the first entry and the second entry.

Abstract: In order to reduce write tail latency, a storage system generates redundant write requests when performing a storage operation for an object. The storage operation is determined to be effectively complete when a minimum number of write requests have completed. For example, the storage system may generate twelve write requests and also generate four redundant write requests for a total of sixteen write requests. The storage system considers the object successfully stored once twelve of the sixteen writes complete successfully. To generate the redundant writes, the storage system may use replication or erasure coding. For replication, the storage system may issue a redundant write request for each of n chunks being written. For erasure coding, the storage system may use rateless codes which can generate unlimited number of parity chunks or use an n+k+k? erasure code which generates an additional k? encoded chunks, in place of an n+k erasure code.

Abstract: Non-standard sector size system support for SSD testing. An automated test equipment for simultaneous testing of multiple solid state drives (SSDs), wherein the SSD has a sector size that is not an integral power of two, includes a tester block configured to receive a command to read and verify an amount of data from the SSD starting at a starting address. The starting address is not constrained to correspond to a sector boundary and the amount of data is not constrained to be an integral multiple of the SSD data sector size. The test equipment also includes logic within said tester block configured to determine a starting sector of the SSD that the starting address points to, and logic within said tester block configured to determine a number of sectors required for the amount of data to be read. The tester block is configured to read a sector from the SSD.

Abstract: Systems and methods for batched storage hinting with fast guest storage allocation. An example method may involve: detecting, by a hypervisor, that storage has been released by a guest operating system and remains allocated to a virtual machine executing the guest operating system; accessing, by the hypervisor, one or more sets of storage blocks, wherein a set of the one or more sets comprises an identifier associated with the storage and is associated with the virtual machine; receiving, by a processing device executing the hypervisor, a request to allocate a storage block to the virtual machine; identifying, by the hypervisor, at least one storage block of the one or more sets that is associated with the virtual machine; and allocating the at least one storage block to the virtual machine.

Abstract: Systems and methods are validating data in a data set. A data set including data to validate and a validator to use in validating the data is selected based on user input generated based on interactions of a user with a graphical user interface. The validator is applied to the data to determine whether one or more statistics generated through application of the validator to the data is valid or invalid based on a validation routine associated with the validator. A data quality report indicating whether the data set is valid or invalid, based on a determination of whether the one or more statistics is valid or invalid, is generated and selectively presented to the user through the graphical user interface.

Abstract: Systems and methods for storing data are described. A system can comprise a controller, one or more physical non-volatile memory devices, a bus comprising a plurality of input/output (I/O) lines. The controller configured to receive data, encode the received data into a codeword, and transfer, in parallel, different portions of the codeword to different physical non-volatile memory devices among the plurality of physical non-volatile memory devices.

Abstract: A method for operating a storage controller reduces a probability of data loss in a storage system having redundant arrays of independent storage volumes (RAID) by identifying an old storage volume in a first location of a first RAID array of the storage system, and further by exchanging the old storage volume in the first location of the first RAID array with a second storage volume in a second location of a second RAID array of the storage system.

Abstract: A method and system for rebuilding a Redundant Array of Independent Disks (“RAID”), the system comprising a RAID engine comprising one or more processing devices that facilitate packet communications with a plurality of storage devices, the packet communications including Read/Write-Rebuild opcodes and settings that prioritize read and write requests associated with a RAID rebuild of the plurality of storage devices, the Read/Write-Rebuild opcodes including rebuild input/output (“IO”) read requests that read good portions of data and parity information from a set of the plurality of storage devices, and rebuild IO write requests that write data to a new one of the plurality storage devices wherein the written data includes data that is reconstructed by the RAID engine based on the data and the parity information.

Abstract: According to one embodiment, an execution unit is described, which includes a mask generation circuit configured to generate a mask by multiplying a mask generation vector by blocks of codewords of a plurality of cyclic codes, a masking circuit configured to mask data to be processed by means of the mask, and an arithmetic logic unit configured to process the masked data by means of additions and rotations.

Abstract: Dynamic deferral systems and methods providing a means to defer performance of a task for a distributed computing system entity both by the number of work cycles as well as in response to an occurrence of a triggering event. By deferring the scheduling in terms of the number of work-cycles, the memory footprint is reduced as the scheduling matrix uses only one byte to store the number. This approach also takes advantage of the most significant bit of a byte to indicate whether the scheduled job is to be evoked in response to a triggering event.

Abstract: A read operation can be performed to retrieve data of a write unit at a memory sub-system. An indication of a time of the performance of the read operation can be received. Another indication of another time of a performance of a write operation to store the data of the write unit at the memory sub-system can be received. A difference between the time of the performance of the read operation and the another time of the performance of the write operation can be determined. A refresh operation can be performed for the data of the write unit at the memory sub-system based on the difference between the time of the performance of the read operation and the another time of the performance of the write operation.

Abstract: A method for performing access management in a memory device, the associated memory device and the controller thereof, and the associated electronic device are provided. The method may include: receiving a host command and a logical address from a host device; performing a checking operation to obtain a checking result, for determining whether to load a logical-to-physical (L2P) table from the NV memory to a random access memory (RAM) of the memory device; reading the target data and associated metadata from the NV memory, wherein a latest version of the L2P table is available in the RAM when reading the target data from the NV memory is performed; and checking whether a recorded logical address within the metadata and the logical address received from the host device are equivalent to each other, to control whether to send the target data to the host device.

Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.

Abstract: Computer-implemented techniques for fair data scrubbing. The techniques can be used to balance a desire to verify recently stored data soon after it is stored on a target data storage media device, when the computing and networking cost of reconstructing the data in the event of a detected data storage media device error can be lower, against a desire to minimize the latency between rescrubbing data. By doing so, the techniques improve the operation of a data storage system that implements the techniques.

Abstract: A selective data restoration technique is disclosed. A request to recover data in a dataset is received along with an identifier of a particular portion of the data to be recovered. The request may specify a time that indicates a desired recovery state (e.g., recover the values as they were at the time). Change data is determined for the specified time. For example, data stream filters generate recovery data by applying filters (e.g., keys) to a time window batch of the stream data. The stream data may correspond to changes to a data set, and the recovery data may correspond to only a portion of the dataset (e.g., a portion of a table). The system performs a recovery action, based on the recovery data, using the recovery data to automatically restore data in a data store, or providing the recovery date to the requesting entity, for example.

Abstract: A device includes a match element that includes a first data input configured to receive a first result, wherein the first result is of an analysis performed on at least a portion of a data stream by an element of a state machine. The match element also includes a second data input configured to receive a second result, wherein the second result is of an analysis performed on at least a portion of the data stream by another element of the state machine. The match element further includes an output configured to selectively provide the first result or the second result.

Abstract: A technique includes determining that a given memory device of a plurality of memory devices has failed and in response to the determination that the given memory device has failed, re-encoding a data unit associated with the given memory device. The data unit is associated with a payload and a symbol-based error correction code. The re-encoding includes determining a bit-based error correction code for the payload and replacing the data unit in the memory with the payload and the bit-based error correction code.

Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k?n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i?k) threshold voltage.

Abstract: A controller of a non-volatile memory manages each of multiple disjoint sets of physical pages as a respective page group. The controller mitigates errors by repetitively performing background mitigation reads of each of the plurality of blocks including, in order, performing a background mitigation read of a first physical page in a first page group in a first block; prior to again performing a background mitigation read in the first block, performing a background mitigation read of a first physical page in a first page group in each other of the plurality of blocks; performing a background mitigation read of a first physical page in a second page group in the first block; and prior to again performing a background mitigation read in the first block, performing a background mitigation read of a first physical page in a second page group in each other of the plurality of blocks.

Abstract: Methods and apparatus such as a processor platform to manage a process under a memory constraint are disclosed herein. An example method includes detecting that a process is to transition from a foreground mode of operation to a background mode of operation. Without transitioning the process to the background mode of operation, a projected out of memory score is calculated. The projected out of memory score is compared to a score threshold, and the process is terminated when the projected out of memory score is greater than the score threshold. When the projected out of memory score is less than or equal to the score threshold, the process is allowed to transition to the background mode of operation. A priority adjustor may determine a projected adjustment value, for example by determining a default adjustment value, or by performing a lookup of an adjustment value currently associated with a second process operating in the background mode.

Abstract: A memory management method is provided. The method includes performing a read retry operation to a target block stripe, and identifying a read retry recording table of the target block stripe; selecting a target read retry index value from one or more first read retry index values according to the one or more first read retry index values in the read retry recording table; using a target read retry option corresponding to the read retry index value to perform a read operation to the target block stripe; in response to determining that the read operation is successful, determining that the read retry operation is completed, and updating the read retry recording table according to the target read retry index value; and determining whether to perform a wear leveling operation to the target block stripe according to the latest read retry recording table.

Abstract: A method includes transmitting a command signal including a time-out time from a host to a storage device; determining, by the storage device, a first time amount, which is an amount of time required for the storage device to perform an operation corresponding to the command signal; when the first time amount is not greater than the time-out time, providing a first response signal including a success flag from the storage device to the host after the storage device performs the operation within the time-out time; when the first time amount is longer than the time-out time, providing a second response signal including the first time amount and a time-out reset flag from the storage device to the host; and when the host receives the second response signal, retransmitting the command signal to the storage device after the host resets the time-out time to the first time amount.

Abstract: A failing computer readable storage medium comprising a portion of a transient object store is detected at a site cache. The site cache associated with the transient object store is set to an error read only state. The failing computer readable storage medium is replaced with an operational computer readable storage medium.

Abstract: A method includes integrating a file system recovery log layer in a file system. The file system buffers data in a cyclical manner, and transforms all incoming random requests into a series of synchronous sequential updates. The method determines whether to flush a received write transaction to a recovery log that is stored in the file system recovery log layer. If it is determined to flush the received write transaction to the recovery log and the received write transaction is a first write transaction for writing data associated with the received write transaction to a file system block. The data associated with the received write transaction is appended in the recovery log and byte-ranges remaining in the file system block are recorded.

Abstract: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software.

Abstract: A method of managing memory includes generating a page pool by aligning a plurality of pages of a memory; when a request to store first data is received, allocating a destination page corresponding to the first data using a page pool; and updating a page table using information about the allocated destination page.

Abstract: Confirming memory marks indicating an error in computer memory including detecting, by memory logic responsive to a memory read operation, an error in at a memory location; marking, by the memory logic in an entry in a hardware mark table, the memory location as containing the error, the entry including one or more parameters for correcting the error; and retrying, by the memory logic, the memory read operation, including: responsive to again detecting the error in the memory location, determining whether the error is correctable at the memory location using the parameters included in the entry; and if the error is correctable at the memory location using the one or more parameters included in the entry, confirming the error in the entry of the hardware mark table.