Abstract: A data processing system 2 is provided with multiple processor cores 4, 6, 8, 10 each incorporating a data cache memory 12, 14, 16, 18. A snoop control unit 20 manages coherency between the data values stored within the data caches 12, 14, 16, 18. The snoop control unit 20 incorporates a TAG memory 22. If an error is detected within an entry of the TAG memory 22, then a hit operation is forced to the corresponding storage location one or more of the data caches 12, 14, 16, 18.

Abstract: The invention provides a method for performing copy back operations. First, a copy back command is sent to a flash memory for reading a first error correction code (ECC) data from a first address. The first ECC data is then received from the flash memory. The first ECC data is then decoded without performing error correction to calculate a fail count of the first ECC data. The fail count is then compared with a first threshold value. When the fail count is less than the first threshold value, a first program command is sent to the flash memory for storing the first ECC data to a second address of the flash memory. When the fail count is less than the first threshold value, the first ECC data is not sent back to the flash memory.

Abstract: Disclosed is a nonvolatile cache memory including a nonvolatile memory part and a cache controller. The nonvolatile memory part is configured to store cache data. The cache controller is configured to control reading and writing of the cache data with respect to the nonvolatile memory part. Further, the cache controller is configured to perform, as a preparation for an interruption of power supply, standby preparation processing to generate standby state data and store the generated standby state data in the nonvolatile memory part. Further, the cache controller is configured to perform, at resumption of the power supply, restoration processing of the cache data stored in the nonvolatile memory part using the standby state data.

Abstract: In an embodiment, a computer system accesses various different data entries in dense data array, where at least one of those data entries in the dense data array is invalid. The computer system creates an associated sparse data array that includes multiple data entries with zero values as well as data entries with non-zero values. The non-zero data entries are configured to store location information and data values for each of the invalid data entries in the dense array. The zero-value data entries are inferred from the location information of the non-zero data entries. The computer system stores the location information and data values of the non-zero data entries in the sparse data array. Those data values stored in the sparse array are proportional to the number of invalid values in the dense array.

Abstract: A method begins when a dispersed storage (DS) processing unit of a DS unit has at least one of DS unit operational data and DS unit operating system algorithm to store. The method continues with the DS processing unit encoding at least a portion of the at least one of DS unit operational data and DS unit operating system algorithm in accordance with an error coding dispersal storage function to produce a plurality of data slices. The method continues with the DS processing unit storing at least some of the plurality of data slices in memory devices of the DS unit in accordance with the error coding dispersal storage function.

Abstract: A processor includes an accumulator, a storage that outputs data to the accumulator, an error detector that outputs a first error detection signal upon detecting an error in the data, an error identifier that outputs an error identification signal indicating that an error occurs in the storage, an error identification signal holder that outputs the error identification signal as a second error detection signal, an error detection signal holder that holds the first error detection signal and outputs a cancellation signal to stop the accumulation processing of the accumulator, a first calculator that starts making a first calculation based on the second error detection signal and the cancellation signal, and outputs a correction start signal after a lapse of a calculation period, and an error corrector that corrects the error of the data upon receiving the correction start signal.

Abstract: Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values.

Abstract: Subject matter described pertains to apparatuses and methods for operating a memory device.

Abstract: Methods of writing data to and reading data from memory devices and systems for writing and reading data are disclosed. In a particular embodiment, a method includes writing data bits a first time into a memory. Auxiliary parity bits are written in the memory, where the auxiliary parity bits are computed based on the data bits. Subsequent to writing the data bits a first time and writing the auxiliary parity bits, the data bits are written a second time into the memory. Writing the data bits the first time and writing the data bits the second time are directed to one or more storage elements at a common physical address in the memory. Subsequent to writing the data bits the second time, the auxiliary parity bits are discarded while maintaining the data bits in the memory.

Abstract: A method of dynamic data storage for error correction in a memory device is disclosed. Data for storage is received, and the received data is then encoded and associated error correction code (ECC) is generated. The encoded data is stored in a portion of a data partition of the memory device, wherein percentage of the stored data in the data partition is determined according to an amount of corrected errors associated with the data partition or is predetermined.

Abstract: An integrated circuit containing a memory array, a redundancy circuit and a redundancy error correction circuit coupled to said redundancy circuit. A method for constructing a redundancy word which corresponds to each memory segment and a method for error checking the redundancy word during a memory access request.

Abstract: Provided is a storage system, including: one or more disk drives storing data; a disk controller for controlling data access to the disk drive; a power supply controller for autonomously turning off a power source of the disk drive according to the data access status to the disk drive, and autonomously turning on the power source of the disk drive, which was turned off, after the lapse of a prescribed period from the time the power source was turned off irrespective of the data access status to the disk drive; and a media inspection unit for inspecting a failure in the disk drive in which the power source thereof was autonomously turned on irrespective of the data access status to the disk drive.

Abstract: A storage apparatus includes a storage drive which writes and reads out a block of data with respect to a storage medium loaded on the storage apparatus, a processor which executes access control on a plurality of volumes assigned to the storage medium and a memory which stores a piece of management information that includes a piece of information indicating a usage frequency of each of the volumes. The processor executes a procedure including: determining a reallocation target volume from among a plurality of volumes assigned to the storage medium based on the management information, and moving the data of the reallocation target volume to a reallocation destination storage medium which is different from the storage medium.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes: receiving a data input having at least a first local chunk and a second local chunk, the data input also being defined as having at least a first global chunk and a second global chunk; rearranging an order of the first local chunk and the second local chunk to yield a locally interleaved data set; storing the locally interleaved data set to a first memory, such that the first global chunk is stored to a first memory space, and the second global chunk is stored to a second memory space; accessing the locally interleaved data set from the first memory; and storing the locally interleaved data set to a second memory. The first global chunk is stored to a third memory space defined at least in part based on the first memory space, and the second global chunk is stored to a fourth memory space defined at least in part based on the second memory space.

Abstract: Systems and methods are disclosed for handling unclean shutdowns for a system having non-volatile memory (“NVM”). In some embodiments, the system can leverage from information obtained from index pages in order to efficiently reconstruct logical-to-physical mappings after an unclean shutdown event. In other embodiments, the system can reconstruct logical-to-physical mappings by leveraging from context information stored in a NVM. In further embodiments, context information can be used in conjunction with index pages to reconstruct logical-to-physical mappings after an unclean shutdown.

Abstract: A method includes, in a storage device that includes a non-volatile memory having a physical storage space, receiving data items associated with respective logical addresses assigned in a logical address space that is larger than the physical storage space. The logical addresses of the data items are translated into respective physical storage locations in the non-volatile memory. The data items are stored in the respective physical storage locations.

Abstract: An information storage device includes a semiconductor memory divided into storage regions and a management unit. The management unit manages the storage regions so that any storage region which caused read or write errors a predetermined threshold number of times, which may be two or more, is made unavailable for storing data.

Abstract: A method including creating a commit-in-progress context from a copy of a data object in a redirect-on-write file system; and begin storing the commit-in-progress context in a persistent storage device. The method further includes, while storing the commit-in-progress context in the persistent storage device: receiving a notification of a pending modification to the first data object, creating an update-in-progress context from a copy of the commit-in-progress context, and begin applying the modification to the update-in-progress context. The method further includes detecting that a connectivity error has occurred between the commit-in-progress context and the storage device, and in response, identifying whether the commit-in-progress context is successfully stored in the storage device.

Abstract: A method begins when a dispersed storage (DS) processing unit of a DS unit has at least one of DS unit operational data and DS unit operating system algorithm to store. The method continues with the DS processing unit encoding at least a portion of the at least one of DS unit operational data and DS unit operating system algorithm in accordance with an error coding dispersal storage function to produce a plurality of data slices. The method continues with the DS processing unit storing at least some of the plurality of data slices in memory devices of the DS unit in accordance with the error coding dispersal storage function.

Abstract: Methods, computer-readable media, and computer systems are provided for initiating storage of data on multiple storage devices and confirming storage of the data after the data has been stored on one but not necessarily all of the devices. A storage server receives, from a client, a request to store data. In response to the request, the storage server initiates, in parallel, storage of the data on multiple storage systems. The storage server detects that the data has been stored on any one of the storage systems, such as an auxiliary system, and, in response, indicates, to the client, that the data has been stored. The storage server may flush or discard data on the auxiliary storage system upon detecting that the data has been successfully stored on a target storage system, where the data persists.

Abstract: Systems and methods for maximizing a number of available states for a version number used for memory corruption detection. A physical memory may be a DRAM comprising a plurality of regions. Version numbers associated with data structures allocated in the physical memory may be generated so that version numbers of adjacent data structures in a virtual address space are different. A reserved set and an available set of version numbers are associated with each one of the plurality of regions. A version number in a reserved set of a given region may be in an available set of another region. The processor detects no memory corruption error in response to at least determining a version number stored in a memory location in a first region identified by a memory access operation is also in a reserved set associated with the first region.

Abstract: Storage volumes are provided across a plurality of storage devices, where the storage volumes include at least a first storage volume and a second storage volume. A storage controller detects fault in a portion of a particular one of the plurality of storage devices, where the portion corresponds to the first storage volume. The storage controller identifies the particular storage device as faulty for the first storage volume without identifying the particular storage device as faulty for the second storage volume.

Abstract: A method and system for verifying memory device integrity includes identifying at least one memory block corresponding to at least one memory location within a memory device. The memory block is associated with a portion of a file and a checksum representing data within the memory block at a first time. Based at least in part on determining that the memory block is mapped to the same portion of the same file at a second time, it is indicated that the checksum represents expected data within the memory block. A system for verifying memory device integrity is also disclosed.

Abstract: Disclosed are an apparatus and method for writing data based on a drive state. In one embodiment, a method may comprise receiving a command to store data to a first area of a data storage device, detecting whether the data storage device is in a first state indicating a lowered write reliability, and writing the data to a second area when the first state is detected, the second area having a higher write reliability than the first area. In another embodiment, an apparatus may comprise a processor configured to receive a command to write data to a first area of a data storage device, detect whether the data storage device is in a first mode indicating a reduced writing reliability relative to a second mode, and write the data to a second area of the data storage device when the first mode is detected.

Abstract: In a controller of a tape drive, when an error recovery section cannot recover an error detected by an error detecting section, an error-report generation section generates an error report, an error-information acquisition section acquires error information of the tape drive and a cartridge loaded in the tape drive, an error-information exchange section acquires pieces of error information of other tape drives and cartridges loaded in these other tape drives, an error-factor judging section judges whether the error is attributable to the tape drive or the cartridge based on these pieces of error information, an error-report update section updates the error report in accordance with the result of this judgment, and an error-report output section outputs the error report thus updated to a host.

Abstract: The information processing device which recovers a domain developing a fault caused by added application and device driver while maintaining security and reliability includes a plurality of processors, wherein the plurality of processors form a plurality of domains according to processing contents to be executed, and the processors in different domains communicate with each other through a communication unit, and which further includes a recovery unit for executing, for a domain developing a fault, failure recovery processing based on a failure recovery request notified by the domain and a recovery condition set in advance for each domain.

Abstract: A flash memory system comprising temporary memory, writing apparatus for writing first logical data from the temporary memory into flash memory cells having at least two levels, thereby to generate a physical representation of the first logical data including known errors, reading apparatus for reading the physical representation from the cells, thereby to generate, and store in the temporary memory, second logical data which if read immediately is identical to the first logical data other than the known errors; and controlling apparatus controlling the writing apparatus and the reading apparatus and including known error ID apparatus operative to identify the known errors by comparing the first logical data to second logical data read immediately after the physical representation is generated, to store information characterizing the known errors and to use the information, when the second logical data is next read, to correct the known errors.

Abstract: A method, computer program product, and system determining the cause of serialization failures is described. A method may comprise, if a first object that has been serialized with all references to member fields by the first object removed passes deserialization, restoring, via at least one of a client electronic device and a server computer, a first reference to a first member field by the first object. The method may further comprise serializing, via at least one of the client electronic device and the server computer, the first object with the restored first reference to the first member field. The method may also comprise, if the serialized first object with the restored first reference to the first member field fails deserialization, determining, via at least one of the client electronic device and the server computer, that the first reference to the first member field by the first object causes the failure.

Abstract: An electronic apparatus includes an error detection times acquiring module and a waiting module. The error detection times acquiring module acquires the number of reading error detection times of a program according to a power-ON instruction instructing a power-ON operation, the number of error detection times being stored in a storage module. The waiting module waits for a reception of data capable of recognizing a communication counterpart device when the number of error detection times is more than a predetermined value by comparing the acquired number of error detection times with the predetermined value.

Abstract: A host device 200A includes a data buffer 250. When data has been already written to a part of a physical block and data is additionally written to the physical block, it is determined whether or not the data written to the physical block is held in the data buffer. When the data is held, data is written to the block, and when an error exists, data in unit of physical blocks is rewritten. When the data is not held in the data buffer, a new physical block is required to be secured and then, data is written to the new block. Thereby, even when power is shut off or an error occurs during writing in the semiconductor memory device, destruction of data already written is prevented.

Abstract: A method for processing a write instruction for writing data to a database stored on a logical device includes obtaining first and second addresses that specify the location of the data in respective first and second address spaces. A third address corresponding to an expected location of the data record in the first address space is then calculated. On the basis of a comparison between the first address and the third address, a determination is made as to whether to execute the write instruction.

Abstract: A system to improve memory failure management may include memory, and an error control decoder to determine failures in the memory. The system may also include an agent that may monitor failures in the memory. The system may further include a table where the error control decoder may record the failures, and where the agent can read and write to.

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.

Abstract: Data storage services are provided for clients for backup of data objects from the clients. A data object is sent to a first location in a first storage device. A determination is made if the data object was successfully stored at the first location, and if so, meta data corresponding with the data object is stored, wherein the meta data includes first path information on a first data path of the data object to the first location. The data object is migrated from the first location to a second location in a second storage device. A determination is made if the data object was successfully stored at the second location, and if so, second path information on a second data path of the data object is added to the second location to the meta data corresponding with the data object, to update the meta data.

Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

Abstract: A system is provided. The system detects a dropped write from a hard disk drive (HDD). The system includes two or more HDDs, each being configured to define a data block spread across the two or more HDDs. The data block is configured to regenerate a checksum across the full data block during a read operation to detect the dropped write.

Abstract: Systems and method for configuring a page-based memory device without pre-existing dedicated metadata. The method includes reading metadata from a metadata portion of a page of the memory device, and determining a characteristic of the page based on the metadata. The memory device may be configured as a cache. The metadata may include address tags, such that determining the characteristic may include determining if desired information is present in the page, and reading the desired information if it is determined to be present in the page. The metadata may also include error-correcting code (ECC), such that determining the characteristic may include detecting errors present in data stored in the page. The metadata may further include directory information, memory coherency information, or dirty/valid/lock information.

Abstract: Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data.

Abstract: A system and method for error detection in a data storage array includes one or more storage medium interconnected with a controller through a network. A data integrity engine in the controller applies a first error detection process to a data object to create one or more data blocks and associated parity codes. First and second error detection processes are applied to detect and repair errors in the data object.

Abstract: An information processing device includes a memory unit that stores registration data of a search target and error information indicating an error of the registration data in association with each other. The information processing device includes a search unit that searches for registration data from the registration data stored by memory unit, the registration data searched by the search unit being registration data for which a value obtained by subtracting a value of the error information from a value of distance between query data related to a search request and the registration data is within the predetermined neighborhood range.

Abstract: Disclosed is a method of detecting a product data error in a storage system. First and second vital product data (VPD) EEPROMs are read. Indicators of whether wither or both reads failed are received. Based on these indicators, the contents of the VPD EEPROMs may be compared. Based on a result of the comparing indicating a match, an arbitrary one of the VPD EEPROMS is used. Based on an indicator indicating an error with the first VPD EEPROM, the second VPD EEPROM is used.

Abstract: A memory controller including a detection module and a protection module is provided. The memory controller is applicable to a memory having a command transmission port and a data transmission port. The detection module detects whether an error condition occurs in an electronic device associated with the memory. When the error condition is detected, the protection module sends an interrupt command to the memory via the command transmission port to stop an operation associated with the data transmission port.

Abstract: A reproducing apparatus is provided. The reproducing apparatus includes a recording/reading unit that records data on or reads data from a disc including a defect management area in which defect information regarding data recorded in a data area of the disc and defect management information for managing the defect information are repeatedly recorded, and a controller that controls the recording/reading unit to read the defect information and the defect management information from the defect management area, and read data from the disc using the defect information. First defect information, which is repeatedly recorded, includes second defect information which is recorded in a predetermined area and defect information regarding a defective block occurring after the second defect information is recorded. The defect management information includes location information of the defect information.

Abstract: A dispersed storage device for use within a dispersed storage network operates to select a set of dispersed storage units for storage of a data object by slicing an encoded data segment of a data object into error coded data slices, determining slice metadata for the error coded data slices, determining memory characteristics of dispersed storage units capable of storing the error coded data slices and selecting the set of dispersed storage units for storing the error coded data slices based on the slice metadata and the memory characteristics.

Abstract: Embodiments of an invention for verifying firmware using system memory error check logic are disclosed. In one embodiment, an apparatus includes an execution core, firmware, error check logic, non-volatile memory, comparison logic, and security logic. The error check logic is to generate, for each line of firmware, an error check value. The comparison logic is to compare stored error check values from the non-volatile memory with generated error check values from the error check logic. The security logic is to prevent the execution core from executing the firmware if the comparison logic detects a mismatch between the stored error code values and the generated error code values.

Abstract: A system implementing parallel memory error detection and correction divides data having a word length of K bits into multiple N-bit portions. The system has a separate error processing subsystem for each of the N-bit portions, and utilizes each error processing subsystem to process the associated N-bit portion of the K-bit input data. During memory write operations, each error processing subsystem generates parity information for the N-bit data, and writes the N-bit data and parity information into a separate memory array that corresponds to the error processing subsystem. During memory read operations, each error processing subsystem reads N-bits of data and the associated parity information. If, based on the parity information, an error is detected from the N-bit data, the error processing subsystem attempts to correct the error. The corrected N-bit data from each of the error processing subsystems are combined to reproduce the K-bit word.

Abstract: A data file on a storage media is processed during playback or execution to identify unreadable data. Replacement data corresponding to the unreadable data is obtained over a communications network, and the replacement data is used to playback or execute the data file as if the data file does not contain any unreadable data.

Abstract: The present invention is a method, computer-readable medium and an apparatus for protection and recovery of non-redundant computer-readable information stored in a memory having multiple segments that features replacing computer-readable information stored in one of the multiple segments based upon a determination that computer-readable information stored in one of the remaining segments of the multiples segments is in a desired state. To that end, the memory device operates synergistically with a shelf manager, which maintains a state of computer-readable information in the differing address ranges of the memory device, so that any computer-readable information replaced in memory device may be achieved by executing uncorrupted computer-readable information stored in the memory device.

Abstract: A method for updating data includes, in a processor, receiving a data field update associated with an existing data object of a data class, modifying a data field of an updater data object of the data class based upon the data field update, traversing the updater data object to identify the modified data field, and modifying a data field of the existing data object based upon the identified data field of the updater data object.

Abstract: Embodiments of the present invention include computer-implemented methods for selectively applying remedial actions, according to a predefined order, for reducing the error rate in a computer memory system. In one embodiment, an ordered set of remedial actions are sequentially invoked in response to a single-bit error (SBE) in a DIMM reaching successive error thresholds. For example, in an air-cooled system, the remedial actions may include dynamically increasing a DIMM refresh rate, dynamically increasing a rate of airflow used to cool the DIMMs, and dynamically throttling the DIMMs. The remedial actions may be layered as they are successively invoked, to provide a cumulative remedial effect. At least two of the remedial actions may be simultaneously invoked in response to a multi-bit error rate reaching an associated threshold.