Storage Content Error Patents (Class 714/54)
-
Publication number: 20150019918Abstract: A method and an apparatus for reducing a read latency are provided. The method includes: when one or more flash chips corresponding to a read command are in a busy state, setting data read from the one or more flash chips in a busy state to wrong data; obtaining, according to the wrong data and data read from other flash chips, reconstructed correct data, and reporting the correct data. By using the present invention, data read from a flash chip is set to wrong data, and reconstructed correct data is obtained according to the wrong data and data read from other flash chips. In this way, when the flash chip is in a busy state, it can be avoided that a read operation is blocked by an erase operation or a write operation, thereby effectively reducing latency and improving a performance of a storage system.Type: ApplicationFiled: September 2, 2014Publication date: January 15, 2015Inventor: Yansong Li
-
Publication number: 20150006975Abstract: A data storage device includes a non-volatile memory and a controller. The non-volatile memory includes a word line coupled to a plurality of storage elements. A method includes detecting a condition associated with a defect in the word line. A first subset of the plurality of storage elements and a second subset of the plurality of storage elements are determined based on an estimated location of the defect. The method further includes determining a first read threshold for the first subset and a second read threshold for the second subset.Type: ApplicationFiled: June 27, 2013Publication date: January 1, 2015Inventors: SEUNGJUNE JEON, IDAN ALROD, ERAN SHARON, DANA LEE
-
Publication number: 20150006977Abstract: Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.Type: ApplicationFiled: January 31, 2012Publication date: January 1, 2015Inventors: Gary Gostin, Erin A. Handgen
-
Publication number: 20150006976Abstract: A data storage device includes a non-volatile memory that includes a three-dimensional (3D) memory and circuitry associated with operation of memory cells of the 3D memory. The non-volatile memory includes a word line coupled to a plurality of storage elements. A method includes detecting a condition associated with a defect in the word line. A first subset of the plurality of storage elements and a second subset of the plurality of storage elements are determined based on an estimated location of the defect. The method further includes determining a first read threshold for the first subset and a second read threshold for the second subset.Type: ApplicationFiled: May 22, 2014Publication date: January 1, 2015Applicant: SANDISK TECHNOLOGIES INC.Inventors: SEUNGJUNE JEON, IDAN ALROD, ERAN SHARON, DANA LEE
-
Patent number: 8924793Abstract: A data storage device comprises storage media and a controller. The storage media may comprise a plurality of media defects, at least some of the media defects being listed in a grown defect list and a primary defect list comprising a plurality of entries sorted in an order according to physical address locations. The controller may be configured to generate a push down list from the primary defect list and the grown defect list by populating the push down list with entries from the primary defect list such that the push down list entries maintain the order; translating each entry in the grown defect list to a physical address location; and inserting each translated physical address location with updated push down count into the push down list.Type: GrantFiled: July 12, 2012Date of Patent: December 30, 2014Assignee: Western Digital Technologies, Inc.Inventor: Joe C. Lee
-
Patent number: 8924775Abstract: A data storage device may comprise storage media comprising a plurality of sectors, and a controller configured to selectively read and write data thereto. The controller may be further configured to tag a sector as a bad sector to be relocated after a first failed read and to untag the tagged sector after a successful write attempt after the first failed read. After a second failed read from the sector subsequent to the successful write, the controller may tag the untagged sector as a bad sector to be relocated and adjust a recurring bad sector counter for that sector. On a subsequent write request, based at least in part on the bad sector counter and a threshold, the controller may determine whether to relocate data stored at a physical location on the data storage device corresponding to the sector to a spare location on the data storage device.Type: GrantFiled: September 25, 2012Date of Patent: December 30, 2014Assignee: Western Digital Technologies, Inc.Inventors: Kum Gatt Siew, Petrus Hu, Siew Lily Yang
-
Publication number: 20140372793Abstract: Systems and methods are provided that may be used to identify and report multiple information units (e.g., logical blocks) having medium errors within a given composite information structure (e.g., physical block) of a storage device (e.g., such as a hard drive) whenever any single information unit having an error within the same composite information structure is accessed.Type: ApplicationFiled: June 13, 2013Publication date: December 18, 2014Applicant: DELL PRODUCTS L.P.Inventors: Chandrashekar Nelogal, David M. Pereira
-
Patent number: 8914680Abstract: File system errors are handled and computing systems are recovered by, responsive to receiving a page buffer request, initializing a sleep timer according to a detection interval value plus a hang resolution range value; responsive to the timer expiring, detecting that a process, thread, application program, daemon, or task is waiting on availability of the requested page buffer; and responsive to the detection, quarantining metadata associated with the requested page buffer, failing the page buffer request and releasing one or more locks on the requested page buffer. This process is then optionally repeated for additional processes, threads, application programs, daemons, tasks or combinations thereof which are waiting for availability of the requested page buffer, optionally randomizing the detection interval value in order to avoid an instantaneous recovery from the error.Type: GrantFiled: July 2, 2012Date of Patent: December 16, 2014Assignee: International Business Machines CorporationInventors: Adekunle Bello, Aruna Yedavilli
-
Patent number: 8909996Abstract: Methods, computer-readable media, and computer systems are provided for initiating storage of data on multiple storage devices and confirming storage of the data after the data has been stored on one but not necessarily all of the devices. A storage server receives, from a client, a request to store data. In response to the request, the storage server initiates, in parallel, storage of the data on multiple storage systems. The storage server detects that the data has been stored on any one of the storage systems, such as an auxiliary system, and, in response, indicates, to the client, that the data has been stored. The storage server may flush or discard data on the auxiliary storage system upon detecting that the data has been successfully stored on a target storage system, where the data persists.Type: GrantFiled: January 9, 2012Date of Patent: December 9, 2014Assignee: Oracle International CorporationInventors: Kesavan P. Srinivasan, Boris Erlikhman, Juan R. Loaiza, Jia Shi, Alexander Tsukerman, Kothanda Umamageswaran
-
Patent number: 8909999Abstract: A dynamic voltage scaling system based on on-chip monitoring and voltage prediction is disclosed, comprising a main circuit that has integrated on-chip monitoring circuits, a supply voltage scaling module, and voltage converters, wherein, the supply voltage scaling module comprises a sampling and statistics module designed to calculate the error rate of the main circuit in the current time slice, a state recording module designed to record the error rate and the corresponding supply voltage, an error prediction module, and a state transition probability generation module; the error prediction module predicts the error trend of the main circuit in a future time slice according to the state recording module and the state transition probability generation module, and generates regulation signals and sends to the corresponding voltage converters, so as to generate the voltage required for operation of the entire main circuit.Type: GrantFiled: October 17, 2011Date of Patent: December 9, 2014Assignee: Southeast UniversityInventors: Longxing Shi, Weiwei Shan, Jun Yang, Haolin Gu, Xinning Liu, Yang Zhang
-
Patent number: 8897109Abstract: Embodiments described herein are directed to a virtual repair of digital media using a virtual repair service. Digital media stored on a digital media device is read using a media player. A request is received by a virtual repair unit from the media player to perform a virtual repair of a segment of unreadable digital content of the digital media. The virtual repair unit retrieves a readable copy of the digital content corresponding to the segment of unreadable digital content identified in the request from a media repository using the virtual repair unit. The virtual repair unit transmits the readable copy of the digital content to the media player for insertion into a buffer of the media player.Type: GrantFiled: July 11, 2013Date of Patent: November 25, 2014Assignee: Xerox CorporationInventor: Gavan Leonard Tredoux
-
Patent number: 8892964Abstract: A system and method for arbitrating exchange identifier assignments for I/O operations are disclosed. In an exemplary embodiment, the method comprises receiving, by a storage system, a data command from a host system. The data command is directed to a virtual device of the storage system, the virtual device comprising a plurality of physical devices of the storage system. A range of exchange identifier values are allocated to the data command. The range may include a predefined number of exchange identifiers, the predefined number determined prior to the receiving of the data command. A plurality of I/O operations corresponding to the data command are issued, where each of the plurality of I/O operations is directed to a physical device of the plurality of physical devices of the storage system. An exchange identifier within the range of exchange identifier values is associated with each of the plurality of I/O operations.Type: GrantFiled: June 28, 2013Date of Patent: November 18, 2014Assignee: NetApp, Inc.Inventors: Howard Young, Srinivasa Nagaraja Rao
-
Patent number: 8892940Abstract: A method includes, in at least one aspect, receiving a command for a group of data units to be transmitted to a host in a first sequence; for each data unit of the group of data units, receiving an identifier of the data unit and a signal indicating that the data unit has been retrieved and processed for errors, wherein the identifiers and the signals are received in accordance with the group of data units being retrieved from one or more memory devices in a second sequence that is different from the first sequence; tracking the group of data units retrieved in the second sequence; determining, by processing circuitry, that the group of data units has been retrieved and processed for errors; and initiating transmission of the group of data units to the host in accordance with the first sequence.Type: GrantFiled: January 29, 2014Date of Patent: November 18, 2014Assignee: Marvell World Trade Ltd.Inventors: Cheng Kuo Huang, Siu-Hung Frederick Au, Lau Nguyen, Perry Neos
-
Publication number: 20140337675Abstract: If a failure occurs in physical resources constituting a virtual volume, a management server device is notified of information required by a user.Type: ApplicationFiled: July 25, 2014Publication date: November 13, 2014Applicant: Hitachi, Ltd.Inventors: Nobumitsu TAKAOKA, Masaaki IWASAKI, Shoji KODAMA
-
Patent number: 8887091Abstract: An information processing apparatus includes a determination unit configured to determine whether incorrect updating processing in which information stored in a memory of the information processing apparatus is incorrectly updated has been executed in a first application program for receiving an instruction issued by a user and for controlling execution of processing corresponding to the instruction; a forcible termination unit configured to, when the determination unit determines that the incorrect updating processing has been executed, forcibly terminate the first application program; and a restart control unit configured to, when the determination unit determines that the incorrect updating processing has been executed, after the forcible termination unit terminates the first application program, notify the user of the occurrence of the incorrect updating.Type: GrantFiled: December 17, 2007Date of Patent: November 11, 2014Assignee: Sony CorporationInventors: Hidenori Yamaji, Akira Hirai, Takuya Nishibayashi
-
Patent number: 8880963Abstract: There are provided a message processing device and a method improved to store a plenty of messages used for processing. When a message is transmitted to another node for providing a service, a message processing unit (26) monitors the message transferred and stores it in a storage region whose allocation is released when the remaining memory amount has become little. When an error has occurred in the processing of a service providing unit (200), the message processing unit (26) stores the error type and a session identifier associated with it. When a message transmission is requested from outside and the error type, the session identifier, and a message associated with them are stored, the message processing unit (26) transmits them. If the storage region which was containing a message is released and no message exists, the message processing unit (26) transmits the other two items.Type: GrantFiled: September 6, 2005Date of Patent: November 4, 2014Assignee: Hewlett-Packard Development Company, L. P.Inventor: Hideaki Nobata
-
Publication number: 20140298116Abstract: A method and apparatus for of storing data comprising monitoring a plurality f storage units within a mass storage area and detecting when a storage unit within the mass storage area is overloaded, The method further comprising randomly distributing the data on the overloaded storage unit to the other storage units within the mass storage area.Type: ApplicationFiled: June 18, 2014Publication date: October 2, 2014Inventors: BRIAN BODMER, ERIC BODNAR, JONAH KAJ FLEMING, DEVUTT SHETH, MARK TARANTINO
-
Patent number: 8850173Abstract: A machine and method to manage BIOS images.Type: GrantFiled: April 29, 2009Date of Patent: September 30, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: John Landry, James Luke Mondshine
-
Patent number: 8850282Abstract: A verifying device includes a receiving unit operable to receive data recorded on a recording medium and a verifying unit operable to verify the received data. The verifying unit sets a predetermined first range and a second range that includes a plurality of the first ranges on the received data, performs first verification about an error on data included in the first range out of the received data, performs second verification about an error on data included in the second range out of the received data on the basis of a result of the first verification, and determines whether the recorded data is successfully recorded on the recording medium on the basis of the results of the first and second verification.Type: GrantFiled: November 9, 2012Date of Patent: September 30, 2014Assignee: Panasonic CorporationInventors: Kengo Yasumura, Naoki Fujimoto, Hiroyuki Awano, Yasuhiro Sasano
-
Patent number: 8843779Abstract: A disk drive including a disk surface including a first backup location, and a second backup location, a head actuated radially over the disk surface to write data to the disk surface, a memory configured to store a signature, and control circuitry coupled to the head. The control circuitry can be configured to receive a command to write data to the disk surface, insert the signature into the data, write the data to the disk surface, and alternately writing a spare copy of the data to the first backup location and to the second backup location based on a value of the signature.Type: GrantFiled: September 12, 2012Date of Patent: September 23, 2014Assignee: Western Digital Technologies, Inc.Inventors: Chin Phan Kuan, Noppol Vangnayunut, Nikki Poh Ling Khew, Peng Lee Liang
-
Publication number: 20140281750Abstract: A method includes determining a read threshold voltage corresponding to a group of storage elements in a non-volatile memory of a data storage device. The method also includes determining an error metric corresponding to data read from the group of storage elements using the read threshold voltage. The method includes comparing the read threshold voltage and the error metric to one or more criteria corresponding to a corrupting event.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Applicant: SANDISK TECHNOLOGIES INC.Inventors: SEUNGJUNE JEON, IDAN ALROD, QING LI, XIAOYU YANG
-
Publication number: 20140281751Abstract: Embodiments relate to early data delivery prior to error detection completion in a memory system. One aspect is a system that includes a cache subsystem interface with a correction pipeline in a system domain. The system includes a memory control unit interface in a memory controller nest domain and a buffer control block providing an asynchronous boundary layer between the system domain and the memory controller nest domain. A controller is configured to receive a frame of a multi-frame data block and write the frame to the buffer control block. The frame is read by the cache subsystem interface prior to completion of error detection of the multi-frame data block. Error detection is performed on the frame in the memory controller nest domain. Based on detecting an error in the frame, an intercept signal is sent from the memory controller nest domain to the correction pipeline in the system domain.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Glenn D. Gilda, Mark R. Hodges, Vesselina K. Papazova, Patrick J. Meaney
-
Patent number: 8839051Abstract: A system for clocking a decoder is disclosed. The system includes: a channel front end configured to receive input data, a first clock configured to provide a first clock signal as input to the channel front end, a decoder configured to receive intermediate data associated with the output of the channel front end, and a second clock configured to provide a second clock signal as input to the decoder. In some embodiments, the second clock signal is not derived from the first clock signal.Type: GrantFiled: February 24, 2012Date of Patent: September 16, 2014Assignee: SK hynix memory solutions inc.Inventors: Kwok W. Yeung, Kin Man Ng, Kin Ming Chan
-
Publication number: 20140245084Abstract: Systems and methods are disclosed for monitoring the time it takes to perform a write operation, and based on the time it takes, a determination is made whether to retire a block that is a recipient of the write operation. The time duration of the write operation for a page or a combination of pages may indicate whether any block or blocks containing the page or combination of pages is experiencing a physical failure. That is, if the time duration of the write operation for a particular page exceeds time threshold, this may indicate that this page requires a larger number of program cycles than other pages. The longer programming cycle can be an indication of cell leakage or a failing block.Type: ApplicationFiled: May 1, 2014Publication date: August 28, 2014Applicant: Apple Inc.Inventors: Matthew J. Byom, Nir J. Wakrat
-
Patent number: 8819500Abstract: A system including a reconstruction module and a correlation module. The reconstruction module is configured to reconstruct data bits detected from first signals, and to generate second signals based on the reconstruction of the data bits detected from the first signals. The correlation module is configured to generate first correlation values by correlating (i) the first signals and (ii) the second signals, and to generate second correlation values by self-correlating the second signals. In response to one or more of (i) the first signals and (ii) the second signals including a floating number having (i) a plurality of bits and (ii) a sign bit, the correlation module is configured to generate one or more of (i) the first correlation values and (ii) the second correlation values based on (i) a plurality of most significant bits of the floating number and (ii) the sign bit of the floating number.Type: GrantFiled: October 7, 2013Date of Patent: August 26, 2014Assignee: Marvell International Ltd.Inventors: Shaohua Yang, Zining Wu
-
Patent number: 8812933Abstract: A memory system includes a nonvolatile memory device and a memory controller configured to control the nonvolatile memory device and configured to provide the nonvolatile memory device with error flag information including error location information of an error of data read from the nonvolatile memory device.Type: GrantFiled: April 18, 2012Date of Patent: August 19, 2014Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Sang-Hyun Joo, Kitae Park, Sangyong Yoon, Jinman Han
-
Publication number: 20140223243Abstract: Redundant storage devices in particular suitable for so-called SSD electronic disks. A data storage system is proposed based on a plurality of redundant physical storage disks in which the read/write commands intended to be sent to the redundant disks are subjected to a transfer function before being sent to at least one of the disks so that the actual commands sent to at least two disks are different. The values returned by the disks that received the commands that had undergone the transfer function are subjected to the inverse transfer function. Thus, a design error in the control module of the disks will be detected, since the control modules of the disks will not be called identically.Type: ApplicationFiled: February 5, 2014Publication date: August 7, 2014Inventors: Jean-Luc Robin, Benjamin Klein
-
Publication number: 20140223242Abstract: A technique for motivating lazy RCU callbacks under out-of-memory conditions. In response to detecting an actual or potential OOM condition, non-lazy callback processing is performed for all processors whose RCU callback lists are non-empty due to at least one callback permitting lazy callback processing being present.Type: ApplicationFiled: February 4, 2013Publication date: August 7, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Paul E. McKenney
-
Patent number: 8793533Abstract: A method and device offering a software diversity of the cited type for floating-point arithmetic, which is applicable in a realtime environment, wherein the method and a device for high-performance validation of the calculation use floating-point numbers of any accuracy within the context of functional safety in accordance with International Electrotechnical Commission (IEC) standard 61508. The method utilizes a specific form of software diversity and has effects on both the runtime environment and the engineering environment.Type: GrantFiled: August 3, 2010Date of Patent: July 29, 2014Assignee: Siemens AktiengesellschaftInventor: Jan Richter
-
Patent number: 8793440Abstract: Aspects of the subject matter described herein relate to error detection for files. In aspects, before allowing updates to a clean file, a flag marking the file as dirty is written to non-volatile storage. Thereafter, the file may be updated as long as desired. Periodically or at some other time, the file may be marked as clean after all outstanding updates to the file and error codes associated with the file are written to storage. While waiting for outstanding updates and error codes to be written to storage, if additional requests to update the file are received, the file may be marked as dirty again prior to allowing the additional requests to update the file. The request to write a clean flag regarding the file may be done lazily.Type: GrantFiled: June 17, 2010Date of Patent: July 29, 2014Assignee: Microsoft CorporationInventors: Thomas J. Miller, Jonathan M. Cargille, William R. Tipton, Surendra Verma
-
Patent number: 8788891Abstract: Embodiments relate to a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line and recording a second address of the second error. Embodiments also include comparing the first and second bitline address, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching the first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to a third bitline address and deleting a location corresponding to the third cache line from available cache locations based on the activated bitline delete mode and the third bitline address matching the second bitline address.Type: GrantFiled: June 14, 2012Date of Patent: July 22, 2014Assignee: International Business Machines CorporationInventors: Ekaterina M. Ambroladze, Michael A. Blake, Michael Fee, Hieu T. Huynh, Patrick J. Meaney, Arthur J. O'Neill
-
Patent number: 8762800Abstract: A system that includes a multiplicity of flash memory cells; a reading apparatus; a writing apparatus for writing logical data from temporary memory into individual flash memory cells from among said multiplicity of flash memory cells, thereby to generate a physical representation of the logical data including a plurality of physical levels at least some of which represent, to said reading apparatus, at least one bit-worth of said logical data; and a special cell marking apparatus operative to store an earmark in at least an individual one of said multiplicity of flash memory cells for subsequent special treatment.Type: GrantFiled: January 28, 2013Date of Patent: June 24, 2014Assignee: Densbits Technologies Ltd.Inventors: Hanan Weingarten, Shmuel Levy
-
Patent number: 8751877Abstract: In an embodiment, a computer system accesses various different data entries in dense data array, where at least one of those data entries in the dense data array is invalid. The computer system creates an associated sparse data array that includes multiple data entries with zero values as well as data entries with non-zero values. The non-zero data entries are configured to store location information and data values for each of the invalid data entries in the dense array. The zero-value data entries are inferred from the location information of the non-zero data entries. The computer system stores the location information and data values of the non-zero data entries in the sparse data array. Those data values stored in the sparse array are proportional to the number of invalid values in the dense array.Type: GrantFiled: November 18, 2011Date of Patent: June 10, 2014Assignee: Microsoft CorporationInventors: Sudarshan Raghunathan, C. David Callahan, II, Adam P. Jenkins
-
Patent number: 8745449Abstract: Various embodiments of the present invention provide systems and methods for managing solid state drives. As an example, a storage system is described that include at least a first flash memory block and a second flash memory block, and a control circuit. The first flash memory block and the second flash memory block are addressable in the storage system. The control circuit is operable to identify the first flash memory block as partially failed, receive a write request directed to the first flash memory block; and direct the write request to the second flash memory block.Type: GrantFiled: January 11, 2012Date of Patent: June 3, 2014Assignee: LSI CorporationInventors: David L. Dreifus, Robert W. Warren, Brian McKean
-
Patent number: 8732521Abstract: A method, system, and computer program product for restoring blocks of data stored at a corrupted data site using two or more mirror sites. The method commences by receiving a trigger event from a component within an application server environment where the trigger event indicates detection of a corrupted data site. The trigger is classified into at least one of a plurality of trigger event types, which trigger event type signals further processing for retrieving from at least two mirror sites, a first stored data block and a second stored data block corresponding to the same logical block identifier from the first mirror site. The retrieved blocks are compared to determine a match value, and when the match value is greater than a confidence threshold, then writing good data to the corrupted data site before performing consistency checks on blocks in physical or logical proximity to the corrupted data site.Type: GrantFiled: August 31, 2011Date of Patent: May 20, 2014Assignee: Oracle International CorporationInventors: Sameer Joshi, Prasad Bagal, Rajiv Wickremesinghe, Richard Long, Harish Nandyala, Shie-rei Huang
-
Patent number: 8732531Abstract: An information processing apparatus includes a processing device and a management device managing the processing device, wherein the processing device includes a first storage device for storing a first program, a first processor that executes the first program, detects an error occurring in the processing device, and extracts partial information which is part of information stored in the first storage device when the error is detected in the processing device through the execution of the first program, and a first control device that transmits the extracted partial information to the management device, and wherein the management device includes a second control device connected to the first control device and that receives the transmitted partial information from the processing device; and a second storage device that stores the received partial information.Type: GrantFiled: September 29, 2010Date of Patent: May 20, 2014Assignee: Fujitsu LimitedInventor: Jinsuke Nakai
-
Patent number: 8726071Abstract: A method begins by a processing module receiving data to store and determining error coding dispersal storage function parameters. The method continues with the processing module encoding at least a portion of the data in accordance with the error coding dispersal storage function parameters to produce a set of data slices. The method continues with the processing module defining addressable storage sectors within the single hard drive based on a number of data slices within the set of data slices to produce a set of addressable storage sectors. The method continues with the processing module storing data slices of the set of data slices in corresponding addressable storage sectors of the set of addressable storage sectors.Type: GrantFiled: February 27, 2013Date of Patent: May 13, 2014Assignee: Cleversafe, Inc.Inventors: S. Christopher Gladwin, Gary W. Grube, Timothy W. Markison
-
Patent number: 8707135Abstract: A method of dynamic data storage for error correction in a memory device is disclosed. Data for storage is received, the received data is encoded and error correction code (ECC) is generated. The encoded data is stored in the memory device that includes a plurality of pages each having a plurality of data partitions. More corrected errors a marked page has, a smaller portion with a space of at least one datum of each of the corresponding data partitions associated with the marked page is allocated to store the encoded data, while a size of the ECC is fixed, thereby increasing capability of correcting errors in the marked page.Type: GrantFiled: March 1, 2013Date of Patent: April 22, 2014Assignee: Skymedi CorporationInventors: Chih-Cheng Tu, Yan-Wun Huang, Han-Lung Huang, Ming-Hung Chou, Chien-Fu Huang, Chih-Hwa Chang
-
Patent number: 8707110Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.Type: GrantFiled: September 6, 2013Date of Patent: April 22, 2014Assignee: Rambus Inc.Inventors: Ian Shaeffer, Craig E. Hampel
-
Publication number: 20140108875Abstract: Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for media defect detection.Type: ApplicationFiled: October 15, 2012Publication date: April 17, 2014Applicant: LSI CorporationInventors: Ming Jin, Fan Zhang, Haitao Xia
-
Publication number: 20140101497Abstract: Events which have occurred in storage systems can be managed easily regardless of complexity of a storage configuration. An event notification system 1 includes: an event notifying client 133 for detecting the occurrence of an event(s) in volumes of a storage system 10; a management application server 20 for storing information about the occurred event as setting/failure information 21; and an event information aggregation server 30 for creating and managing event information 31 including an event key 311 for associating the occurred event with the setting/failure information 21. When the event information aggregation server 30 in such an event notification system 1 notifies an administrator terminal 50 of the event key 311 and an administrator selects the event key 311, the management application server 20 has the administrator terminal 50 display an event browse screen 52 indicating the relativity of a volume, in which the event occurred, to a volume in which a related event occurred.Type: ApplicationFiled: October 4, 2012Publication date: April 10, 2014Applicant: HITACHI, LTD.Inventors: Toshimichi Kishimoto, Shinichiro Kanno
-
Patent number: 8694825Abstract: A mechanism is provided for protecting storage fabrics from an errant device causing a single point of failure. The mechanism identities a source of the out-of-context traffic, isolates the TAG to prevent further catastrophe, and ensures that device isolation control operations are processed timely allowing device isolation and removing the source of the issue. Should device isolation not solve the issue, the mechanism allows the host to use a binary search method to isolate the device that may be hiding its true identity and sourcing possibly malicious traffic.Type: GrantFiled: July 20, 2011Date of Patent: April 8, 2014Assignee: International Business Machines CorporationInventor: Paul N. Cashman
-
Publication number: 20140089745Abstract: A method of reading data in an electronic system comprises detecting whether a trigger signal in the electronic system is enabled, the trigger signal being selectively enabled according to at least one operating condition of the electronic system, as a consequence of detecting that the trigger signal is enabled, changing a size of read-ahead data based on the enabled trigger signal, and performing a read operation based on a read command and the changed size of the read-ahead data.Type: ApplicationFiled: September 25, 2013Publication date: March 27, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: SEUNG-SOO YANG
-
Patent number: 8683272Abstract: Various embodiments are directed to a gaming device including a background memory validation system. The background memory validation system includes a background kernel thread that validates read-only pages on the gaming device. Additionally, the background kernel thread also minimizes potential timing problems because this process only validates page content in memory that is fully-loaded and functional.Type: GrantFiled: February 27, 2013Date of Patent: March 25, 2014Assignee: Bally Gaming, Inc.Inventors: Ronald A. Cadima, Anand Singh, James Schaefer
-
Patent number: 8667326Abstract: A system is provided. The system detects a dropped write from a hard disk drive (HDD). The system includes two or more HDDs, each being configured to define a data block spread across the two or more HDDs. The data block is configured to regenerate a checksum across the full data block during a read operation to detect the dropped write.Type: GrantFiled: May 23, 2011Date of Patent: March 4, 2014Assignee: International Business Machines CorporationInventor: James A. O'Connor
-
Patent number: 8667323Abstract: Processing for file system volume error detection and processing for resultant error correction are separated to support system availability and user satisfaction. File system volumes for storing data structures are proactively scanned while the volumes remain online to search for errors or corruptions thereon. Found errors are scheduled to be corrected, i.e., spot corrected, dependent on the severity of the identified errors, error correction scheduling and/or at the determination of a file system administrator and/or user, to assist in maintaining minimal user and file system impact. When spot correction is initialized, one file system volume at a time is taken offline for correction. Spot correction verifies prior logged corruptions for the offline volume, and if independently verified, attempts to correct the prior noted corruptions. Volumes are retained offline only for the time necessary to verify and attempt to correct prior noted volume corruptions.Type: GrantFiled: December 17, 2010Date of Patent: March 4, 2014Assignee: Microsoft CorporationInventors: Sarosh C. Havewala, Neal R. Christiansen, John D. Slingwine, Daniel Chan, Craig A. Barkhouse
-
Publication number: 20140059396Abstract: According to one embodiment, a memory system includes a NAND-type flash memory and a memory controller. A comparison module of the memory controller compares a first threshold voltage distribution of a first memory area with a second threshold voltage distribution of the first memory area acquired earlier than the first threshold voltage distribution, if an error is detected in data read from the first memory area. An error factor determination module of the memory controller determines a cause of the error based on the comparison result, and inhibits a data move operation of moving data of the first memory area to the second memory area based on the determination result.Type: ApplicationFiled: February 28, 2013Publication date: February 27, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Motohiro MATSUYAMA, Yoko Masuo, Gen Ohshima
-
Patent number: 8656228Abstract: A system and computer implemented method for isolating errors in a computer system is provided. The method includes receiving a direct memory access (DMA) command to access a computer memory, a read response, or an interrupt; associating the DMA command to access the computer memory, the read response, or the interrupt with a stream identified by a stream identification (ID); detecting a memory error caused by the DMA command in the stream, the memory error resulting in stale data in the computer memory; and isolating the memory error in the stream associated with the stream ID from other streams associated with other stream IDs upon detecting the memory error.Type: GrantFiled: June 23, 2010Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Mark A. Check, David F. Craddock, Thomas A. Gregg, Pak-kin Mak, Gary E. Strait
-
Publication number: 20140047265Abstract: A novel ECC scheme is disclosed that offers an error protection level that is at least the same as (if not better than) that of the conventional ECC scheme without negatively impacting latency and design complexity. Embodiments of the present disclosure utilize an ECC scheme which leaves up to extra 2B for metadata storage by changing the error detection and correction process flow. The scheme adopts an early error detection mechanism, and tailors the need for subsequent error correction based on the results of the early detection.Type: ApplicationFiled: March 29, 2012Publication date: February 13, 2014Inventors: Debaleena Das, Rajat Agarwal, C. Scott Huddleston
-
Patent number: 8650438Abstract: The present disclosure includes systems and techniques relating to solid state drive controllers. In some implementations, a device includes a buffer that holds a block of data corresponding to a command from a host. The command identifies the block of data and a logical sequence in which the identified block of data is to be transmitted. In response to the command, a data retriever included in the device retrieves the portions of the block of data from non-volatile memory units in a retrieval sequence that is different from the logical sequence. When the device receives multiple commands identifying multiple blocks of data, the device services the commands in parallel by retrieving portions of blocks of data identified by both commands.Type: GrantFiled: July 23, 2010Date of Patent: February 11, 2014Assignee: Marvell World Trade Ltd.Inventors: Cheng Kuo Huang, Siu-Hung Fred Au, Lau Nguyen, Perry Neos