Ecc, Parity, Or Fault Code (i.e., Level 2+ Raid) Patents (Class 714/6.24)
  • Patent number: 11221958
    Abstract: A system and method for an LBA RAID storage device. The LBA RAID storage device includes a plurality of data channels and a plurality of storage components. Each of the storage components is connected to one of the plurality of data channels. A storage controller is configured to receive a data and write the data to a RAID group made up of at least two storage components of the plurality of storage components that are each connected to a separate data channel.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: January 11, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changho Choi, Nima Elyasi
  • Patent number: 11196565
    Abstract: In one example, a system for managing encrypted memory comprises a processor to store a first MAC based on data stored in system memory in response to a write operation to the system memory. The processor can also detect a read operation corresponding to the data stored in the system memory, calculate a second MAC based on the data retrieved from the system memory, determine that the second MAC does not match the first MAC, and recalculate the second MAC with a correction operation, wherein the correction operation comprises an XOR operation based on the data retrieved from the system memory and a replacement value for a device of the system memory. Furthermore, the processor can decrypt the data stored in the system memory in response to detecting the recalculated second MAC matches the first MAC and transmit the decrypted data to cache thereby correcting memory errors.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: December 7, 2021
    Assignee: INTEL CORPORATION
    Inventors: David M. Durham, Rajat Agarwal, Siddhartha Chhabra, Sergej Deutsch, Karanvir S. Grewal, Ioannis T. Schoinas
  • Patent number: 11182358
    Abstract: A controller-implemented method includes reading, by a controller, a scrub unit containing a read unit and, in response to determining that the scrub unit is not marked as being scrubbed in a current scrub cycle, storing, by the controller, the scrub unit to a memory. The method also includes marking, by the controller, another scrub unit associated with the stored scrub unit as a scrub-pending scrub unit and reading, by the controller, the scrub-pending scrub unit in response to determining that a subsequent read matches predefined criteria. The method includes performing, by the controller, a scrub using the stored scrub unit and the scrub-pending scrub unit. A system includes a processor and logic integrated with the processor, executable by the processor, or integrated with and executable by the processor. The logic is configured to perform the foregoing method.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Gregory Kishi, Itzhack Goldberg, Daniel I. Tan
  • Patent number: 11061788
    Abstract: Storage management techniques involve, in response to a request to write data to a redundant array of independent disks (RAID), determining whether there is an offline disk in a plurality of storage disks constituting the RAID, the RAID comprising a plurality of stripes, each of the plurality of stripes comprising a plurality of storage blocks divided from the plurality of storage disks; in response to determining that there is an offline disk in the plurality of storage disks, selecting a target stripe from the plurality of stripes, the target stripe having a storage block allocated from the offline disk for storing parity information; and writing the data to the target stripe. In this way, the performance of data write can be improved in presence of an offline disk. In addition, the performance of subsequent data read can also be improved potentially.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: July 13, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Jibing Dong, Geng Han, Hongpo Gao, Jianbin Kang, Jian Gao
  • Patent number: 11016850
    Abstract: The disclosed computer-implemented method for detecting bit rot in distributed storage devices having failure domains may include (1) receiving, at a computing device, a combination of data chunks created by adding, for each failure domain storing data chunks, data chunks from different stripes, (2) receiving a combination of parity chunks created by adding, for each failure domain storing parity chunks, parity chunks from the different stripes, (3) creating at least one new parity chunk from the combination of data chunks, and (4) identifying a presence of bit rot in the failure domains when the at least one new parity chunk does not match the combination of parity chunks. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: May 25, 2021
    Assignee: Veritas Technologies LLC
    Inventors: Sushrut Gajbhiye, Deodatta Barhate, Roshan Kolhe, Shailesh Marathe, Anindya Banerjee
  • Patent number: 10998919
    Abstract: Described herein is a system and method for coded streaming data to facilitate recovery from failed or slow processor(s). A batch of processing stream data can be partitioned into a plurality of data chunks. Parity chunk(s) for the plurality of data chunks. The plurality of data chunks and the parity chunk(s) can be provided to processors for processing. Processed data of at least some (e.g., one or more) of the plurality of data chunks, and, processed data of parity chunk(s) are received. When it is determined that processed data for a pre-defined quantity of data chunks has not been received by a pre-defined period of time, the processed data for particular data chunk(s) of particular processor(s) from which processed data has not been received are determined based, at least in part, upon the received processed parity chunk(s) and the received processed data chunk(s).
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 4, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Todd Robert Porter, Xin Tian, Alexander Alperovich
  • Patent number: 10929226
    Abstract: Providing for increased flexibility for large scale parity, the including: writing data to a storage system, including utilizing a first data protection scheme; identifying, for storage media in the storage system, characteristics of the storage media; identifying, in dependence up the characteristics for the storage media, a second data protection scheme to use for the data; and writing the data to the to the storage system utilizing the second data protection scheme.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: February 23, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Ethan Miller, Robert Lee, Par Botes, Ronald Karr
  • Patent number: 10929243
    Abstract: Techniques are provided for service-level rebuild of one or more storage drives. Storage drives can store data of varying priority levels. In an example, when a storage drive is rebuilt, higher-priority data is written to the rebuilt storage drive before lower-priority data. In some examples where multiple storage drives are being rebuilt, a system can prioritize a use of rebuild bandwidth in rebuilding storage drives.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: February 23, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: John Creed, Owen Martin
  • Patent number: 10930315
    Abstract: A method for performing error recovery for data stored on a track of a storage device, in which the method includes: receiving a request to read the data from the storage device, identifying a plurality of sectors of the track to be read in response to the request, reading the data from the plurality of sectors of the track and parity data, based on the data read from the plurality of sectors, determining whether any of the plurality of sectors corresponds to a failed sector, and recovering a portion of the data from the failed sector using the parity data and portions of the data stored in remaining ones of the plurality of sectors.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: February 23, 2021
    Assignee: Marvell Asia Pte., Ltd.
    Inventors: Gregory Burd, Nedeljko Varnica, Heng Tang
  • Patent number: 10911537
    Abstract: A method, computer program product, computing system, and system for increasing speed during synchronization or restore are described. The method may include acquiring list of items to be synchronized or restored. The method may further include defining a set of storage sources available to a client computer. The method may also include mounting the available storage sources to the client computer. The method may additionally include determining a storage intersection of items in the list based on the items being available in more than one mounted storage device. Moreover, the method may include, in response to determining a set of items that has a storage intersection, synchronizing or restoring the items based on at least one of a speed of download and a network latency.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: February 2, 2021
    Inventors: Dmitry Chepel, Stanislav Protasov, Serguei M. Beloussov
  • Patent number: 10872010
    Abstract: The present disclosure includes apparatuses, methods, and systems for error identification on executed code. An embodiment includes memory and circuitry configured to read data stored in a secure array of the memory, identify a different memory having an error correcting code (ECC) corresponding to the read data of the memory, execute an integrity check to compare the ECC to the read data of the memory; and take an action in response to the comparison of the read data of the memory and the ECC, wherein the comparison indicates that the ECC identified an error in the read data of the memory.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Antonino Mondello, Alberto Troia
  • Patent number: 10783036
    Abstract: A method includes accessing at least three storage devices each including a first and a second logical unit stored therein. The method also includes grouping the respective first and second logical units of each of the at least three storage devices into a first striped scheme. The method also includes grouping the respective first logical unit of each of the at least three storage devices into a second striped scheme with parity.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: September 22, 2020
    Assignee: Seagate Technology LLC
    Inventor: Vijay Nanjunda Swamy
  • Patent number: 10769018
    Abstract: One embodiment described herein provides a method and system for handling errors in a storage system. During operation a data-placement module of the storage system detects an error occurring at a first physical location within the storage system. In response to determining that the error occurs during a write access, the system writes to-be-written data into a second physical location within the storage system, and updates a mapping between a logical address and a physical address associated with the to-be-written data.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: September 8, 2020
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 10769135
    Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for storing blockchain data. One of the methods includes determining block data and current state data associated with a current block of a blockchain; sending the current state data to one or more shared storage nodes of a blockchain network; performing error correction coding of the block data to generate encoded block data; dividing, based on one or more predetermined rules, the encoded block data into a plurality of data sets; storing, based on the one or more predetermined rules, one or more data sets of the plurality of data sets; hashing each data set of remaining data sets of the plurality of data sets to generate one or more hash values corresponding to the remaining data sets; and storing the one or more hash values and the current state data.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: September 8, 2020
    Assignee: Alibaba Group Holding Limited
    Inventor: Haizhen Zhuo
  • Patent number: 10742602
    Abstract: A given packet of the packetized data flow of packets is received. The given packet (145) is selectively discarded depending on at least one of the flow history of the packetized data flow and up pseudorandom test. In some embodiments, the selectively discarding is selectively executed of the given packet is at least partially overlapping with at least one further packet of the packetized data flow. Such techniques may find particular application in network-based intrusion prevention systems.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: August 11, 2020
    Assignee: Lantiq Beteiligungs-GmbH & Co. KG
    Inventors: Shiva Shankar Subramanian, Pinxing Lin
  • Patent number: 10727869
    Abstract: A decoder circuit includes an input to receive a first codeword encoded based on a quasi-cyclic low-density parity-check (QC LDPC) code and a plurality of memory banks to store the received codeword. Each column of the received codeword is assigned to one of the plurality of memory banks based at least in part on an order of the plurality of columns in the received codeword. A first reordering stage is to change the memory bank assignment for one or more of the plurality of columns by reordering the columns in the received codeword. An LDPC decoder is to decode the reordered codeword stored in the plurality of memory banks based at least in part on the QC LDPC code. A second reordering stage is to output the decoded codeword from the plurality of memory banks based at least in part on an order of the columns in the first codeword.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: July 28, 2020
    Assignee: Xilinx, Inc.
    Inventors: Richard L. Walke, Andrew Dow
  • Patent number: 10719260
    Abstract: The embodiments set forth a technique that enables the storage of data at a first data storage device. The technique includes, at the first data storage device, dividing the data to produce a first and second portion of the data, in which the first and second portions are associated with a computed exclusive or (“XOR”) value. Also, the technique includes deleting the second portion stored at the first data storage device, based at least in part on whether the computed XOR value is established. Also, the technique includes receiving a first replicated metadata, in which the first replicated metadata indicates a location of the second portion stored at the second data storage device. Furthermore, the technique includes communicating either the first portion or the second portion, to a remote computing device, based at least in part on the first replicated metadata.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: July 21, 2020
    Assignee: Apple Inc.
    Inventors: Vinay Ari, Guy D. Hemmo, Nicholas K. Puz, Lionel Li, Bernard L. Gallet
  • Patent number: 10684956
    Abstract: A system and method for an LBA RAID storage device. The LBA RAID storage device includes a plurality of data channels and a plurality of storage components. Each of the storage components is connected to one of the plurality of data channels. A storage controller is configured to receive a data and write the data to a RAID group made up of at least two storage components of the plurality of storage components that are each connected to a separate data channel.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changho Choi, Nima Elyasi
  • Patent number: 10684915
    Abstract: An apparatus comprises at least one processing device comprising a processor coupled to a memory. The processing device is configured to select a stripe column size for stripes of a data storage system, to determine a first compress block size for a first one of the stripes based on compressibility of data to be stored, to select a first prime number for computing parity blocks for the first stripe and a first number of sub-stripes for splitting stripe columns of the first stripe, to generate metadata specifying the first compress block size, the first prime number and the first number of sub-stripes for the first stripe, and to store data compressed using the first compress block size in the first stripe. The first prime number and first number of sub-stripes for the first stripe is different than a second prime number and second number of sub-stripes for a second stripe.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: June 16, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Zvi Schneider, Marcelo Taube, Lior Kamran, Alex Soukhman, David Krakov
  • Patent number: 10664363
    Abstract: Embodiments of the present disclosure provide a method for a storage system, a storage system and a computer program product. The method comprises determining a first drive in a drive array is temporarily unavailable. The method further comprises setting the first drive in a frozen state. The method further comprises: in response to receiving a write request for the first drive during the frozen state, pending the write request or recording the write request in a second drive in the drive array. The method further comprises: in response to receiving a read request for the first drive during the frozen state, reconstructing data to which the read request is directed through data stored in a third drive in the drive array.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: May 26, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Bing Liu, Man Lv
  • Patent number: 10658046
    Abstract: The embodiment of the present invention discloses a memory device and a method for operating the same. The memory device includes a memory array and a logic circuit. The logic circuit is coupled to the memory array, and is configured to perform a corresponding operation in response to an operation command from a controller. When an interruption event occurs during the corresponding operation, the logic circuit records a memory status, and the logic circuit further is configured to output the memory status to the controller in response to a status read command from the controller.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: May 19, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuen-Long Chang, Ken-Hui Chen, Su-Chueh Lo, Chun-Yu Liao
  • Patent number: 10595333
    Abstract: A method and wireless transmit/receive unit (WTRU) for uplink transmission are disclosed. A WTRU receives configuration information. The configuration information includes logical channel priority information and a maximum number of hybrid automatic repeat request (HARQ) transmissions. For a transmission time interval (TTI), the WTRU identifies a HARQ process to use for uplink transmission for the TTI on a condition that an uplink grant is for the TTI. The WTRU selects data for uplink transmission for the TTI. For a new uplink transmission, data is allocated in decreasing order of priority based on the logical channel priority information. The WTRU initializes a transmission counter. The transmission counter indicates a number of transmissions associated with the selected data. The WTRU transmits the selected data over an uplink channel based on the uplink grant using the identified HARQ process.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: March 17, 2020
    Assignee: InterDigital Technology Corporation
    Inventors: Stephen E. Terry, Guodong Zhang
  • Patent number: 10594491
    Abstract: In one example, a system for managing encrypted memory comprises a processor to store a first MAC based on data stored in system memory in response to a write operation to the system memory. The processor can also detect a read operation corresponding to the data stored in the system memory, calculate a second MAC based on the data retrieved from the system memory, determine that the second MAC does not match the first MAC, and recalculate the second MAC with a correction operation, wherein the correction operation comprises an XOR operation based on the data retrieved from the system memory and a replacement value for a device of the system memory. Furthermore, the processor can decrypt the data stored in the system memory in response to detecting the recalculated second MAC matches the first MAC and transmit the decrypted data to cache thereby correcting memory errors.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: David M. Durham, Rajat Agarwal, Siddhartha Chhabra, Sergej Deutsch, Karanvir S. Grewal, Ioannis T. Schoinas
  • Patent number: 10592134
    Abstract: Systems and methods are disclosed for open block stability scanning. When a solid state memory block remains in an open state, where the block is only partially filled with written data, for a prolonged period of time, a circuit may perform a scan on the block to determine the stability of the stored data. When the scan indicates that the data is below a stability threshold, the data may be refreshed by reading the data and writing it to a new location. When the scan indicates that the data is above a stability threshold, the circuit may extend the time period in which the block may remain in the open state.
    Type: Grant
    Filed: January 1, 2018
    Date of Patent: March 17, 2020
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, Antoine Khoueir, Ara Patapoutian
  • Patent number: 10567102
    Abstract: Methods and systems for enabling recovery of lost packets transmitted over a communication network. In one embodiment, a device includes a processor and a transmitter. The processor is configured to calculate a row parity packet (RPP) and a diagonal parity packet (DPP) for n packets. Each of the RPP, the DPP, and the n packets comprises n segments. The processor utilizes each packet, from among the n packets, to update parity values in the RPP and the DPP in such a way that each segment in the packet is used to update one segment in the RPP and at most one segment in DPP. The transmitter transmits the n packets, the RPP, and the DPP over the communication network. Receiving a subset of n members of a set comprising: the RPP, the DPP, and the n packets, enables recovery of two lost packets.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: February 18, 2020
    Assignee: Valens Semiconductor Ltd.
    Inventors: Shai Stein, Eran Rippel
  • Patent number: 10541770
    Abstract: Methods and systems that enable recovery lost packets that were transmitted over a communication network. In one embodiment, a device includes a receiver and a processor. The receiver receives n packets that belong to a set comprising n+2 packets transmitted over the communication network, where the set includes: n data packets, a row parity packet (RPP), and a diagonal parity packet (DPP). Each received packet comprises n segments. Each segment of the RPP comprises a result of a parity function applied to a set comprising n segments, each belonging to a different packet from among the n data packets. Each segment of the DPP comprises a result of a parity function applied to a set comprising n segments, each belonging to a different packet selected from a group comprising the n data packets and the RPP. The processor may utilize the received packets to recover two lost packets.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: January 21, 2020
    Assignee: Valens Semiconductor Ltd.
    Inventors: Shai Stein, Eran Rippel
  • Patent number: 10514984
    Abstract: A rebuild node of a storage system can assess risk of the storage system not being able to provide a data object. The rebuild node(s) uses information about data object fragments to determine health of a data object, which relates to the risk assessment. The rebuild node obtains object fragment information from nodes throughout the storage system. With the object fragment information, the rebuild node(s) can assess object risk based, at least in part, on the object fragments indicated as existing by the nodes. To assess object risk, the rebuild node(s) treats absent object fragments (i.e., those for which an indication was not received) as lost. When too many object fragments are lost, an object cannot be rebuilt. The erasure coding technique dictates the threshold number of fragments for rebuilding an object. The risk assessment per object influences rebuild of the objects.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: December 24, 2019
    Assignee: NetApp, Inc.
    Inventors: David Anthony Slik, Shehbaz Jaffer, Sethuraman Subbiah, Keith Arnold Smith, Giridhar Appaji Nag Yasa, Atish Kathpal
  • Patent number: 10496484
    Abstract: A device includes a memory device and a controller. The controller is configured to receive data to be stored in the non-volatile memory and to store a first copy of the data and a second copy of the data to a volatile memory. The controller is configured, in response to detecting a bit error corresponding to the first copy of the data prior to storage of the first copy of the data to the non-volatile memory, to perform an error detection operation that includes comparing first redundancy data corresponding to the first copy of the data to second redundancy data corresponding to the second copy of the data.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: December 3, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Guy Freikorn, Judah Gamliel Hahn
  • Patent number: 10372357
    Abstract: A method for execution by a dispersed storage and task (DST) execution unit that includes a processor includes receiving a slice pre-image request from a computing device via a network that indicates a data slice, a requesting entity and a plurality of storage units. A data pre-image is generated by performing a pre-image function on the data slice based on the plurality of storage units. An encrypted data pre-image is generated for transmission to the computing device by performing an encryption function on the data pre-image based on a key associated with the requesting entity.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: August 6, 2019
    Assignee: Pure Storage, Inc.
    Inventor: Jason K. Resch
  • Patent number: 10360106
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable based on the operational instructions, is configured to perform various operations. The computing device determines data access rates corresponding respectively to storage units (SUs). In certain situations, the computing device selects at least a data access threshold number of SUs excluding a first slowest SU having the first slowest data access rate to service data access request(s) for set(s) of encoded data slices (EDSs) corresponding to a data object. The computing device facilitates servicing of the data access request(s) for the set(s) of EDSs by the at least a data access threshold number of SUs that excludes the first slowest SU having the first slowest data access rate.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Greg R. Dhuse, Wesley B. Leggette, Jason K. Resch
  • Patent number: 10303542
    Abstract: A semiconductor device includes a bitwise operation unit and a storage control unit. The bitwise operation unit performs a bitwise operation on first n-bit (n is an integer) data that is storage object data and second data of an n-bit bit pattern and generates third data of a bit pattern that the number of “1s” and the number of “0s” are almost the same as each other. The storage control unit stores the third data into a first storage destination of a storage unit and stores fourth data that is the third data or data that is converted into the third data by performing a bitwise operation that has been predetermined in advance on the data into a second storage destination of the storage unit.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: May 28, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shinichi Suzuki
  • Patent number: 10290331
    Abstract: In general, embodiments of the technology relate to improving read performance of solid-state storage by using decoding schemes deemed particularly suitable for the read operation that is currently being performed. More specifically, embodiments of the technology relate to using program/erase (P/E) cycle values, retention times, and page numbers in order to determine the appropriate decoding parameters to use when reading data that has been previously stored in the solid-state storage.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: May 14, 2019
    Assignee: EMC IP Holding Company LLC
    Inventor: Seungjune Jeon
  • Patent number: 10277253
    Abstract: One embodiment provides a system that facilitates numerical operation-based erasure coding. During operation, the system determines the bit-width of processing capability of the computing system. The system then determines, based on the bit-width, a number of bits for representing a respective data element from a data stream and a number of data elements based on a number of a dimension of a generator matrix of erasure encoding. The system then obtains the number of data elements from the data stream and converts a respective obtained data element to a corresponding numerical representation. Here, a respective obtained data element is represented by the determined number of bits. The system then generates a code word, which comprises a plurality of coded fragments, of erasure encoding from the numerical representations based on the generator matrix of the erasure encoding.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: April 30, 2019
    Assignee: PhazrIO Inc.
    Inventors: Donald C. D. Chang, Chi-Kwan J. Cheung, Lara Dolecek, Gary N. Jin, Rocky Chi-Ray Lin
  • Patent number: 10241860
    Abstract: A smart storage device is provided. The smart storage device contains a data analysis engine and an error detection engine. An external controller sends a command indicating that data contained on a storage medium in the smart storage device which meets certain criterion should be scrubbed, and the smart storage device locates that data without the external controller passing the actual location of the data on the storage medium.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: March 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sheng Qiu, Yang Seok Ki
  • Patent number: 10169144
    Abstract: Some embodiments include apparatuses and methods using a first memory area and a second memory area included a memory device, and using control circuitry included in the memory device to communicate with a memory controller. The memory controller includes an error correction engine. The control circuitry of the memory device is configured to retrieve the first information from the first memory area and store in the first information after the error correction engine performs an error detection operation on the first information. The control circuitry is configured to retrieve second information from the first memory area and store the second information in the second memory area without an additional error detection operation performed on the second information if a result from the error detection operation performed by the error correction engine on the first information meets a threshold condition.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: January 1, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Carla L. Christensen
  • Patent number: 10126961
    Abstract: A method for execution by a dispersed storage and task (DST) execution unit that includes a processor includes receiving a slice pre-image request from a computing device via a network that indicates a data slice, a requesting entity and a plurality of storage units. A data pre-image is generated by performing a pre-image function on the data slice based on the plurality of storage units. An encrypted data pre-image is generated for transmission to the computing device by performing an encryption function on the data pre-image based on a key associated with the requesting entity.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: November 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jason K. Resch
  • Patent number: 9983959
    Abstract: The techniques and/or systems described herein implement erasure coding to generate various chunks for a data collection (e.g., data chunks and at least one encoding chunk). The chunks are then distributed and stored within an individual group (e.g., a pod) of storage units, where a pod of storage units is determined based on characteristics that affect an amount of time it takes to recover a data collection or to restore lost data.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: May 29, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Robert John Jenkins, Jr., Parikshit S Gopalan, Cheng Huang, Edmund Bernard Nightingale, Alexander Shamis, Sergey Yekhanin
  • Patent number: 9917599
    Abstract: A coding scheme for coding “code constructs” (for example, alphanumeric characters) into “bit sequences,” where at least one of the code constructs is assigned at least two different bit sequences (that is, a first bit sequence and a second bit sequence). This is sometimes referred to herein as “alternative codings for a single code construct.” In some embodiments, at least one of the alternative codings includes bits that can be used for error detection and/or correction. In some embodiments, the code scheme will be similar to a pre-existing code scheme that does not have alternative codings for a single code construct so that the alternative-codings coding scheme is back compatible with data encoded under the pre-existing coding scheme.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: March 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Itzhack Goldberg, Erik Rueger, Lance W. Russell, Neil Sondhi
  • Patent number: 9898373
    Abstract: A method begins by a dispersed storage (DS) processing module of a dispersed storage network (DSN), when in a rebuilding mode, determining a level of rebuilding urgency, where the level of rebuilding urgency is based on an inversely proportional function of a level of error encoded redundancy for error encoded data giving rise to the rebuilding mode. When the level of rebuilding urgency is at or above a critical level, the method continues with the DS processing module placing a set of storage units of the DSN in a critical rebuilding mode, where, when in the critical rebuilding mode, the set of storage units prioritize rebuilding of the error encoded data giving rise to the rebuilding mode over other error encoded data operations.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: February 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jason K. Resch
  • Patent number: 9886344
    Abstract: A storage apparatus includes a processor. The processor is configured to sequence a plurality of data pieces. The plurality of data pieces are respectively stored in a plurality of memory devices. The processor is configured to set compensation ranges to be respectively compensated by a first predetermined number of parities. The compensation ranges are respective portions of consecutive data pieces among the sequenced data pieces. The compensation ranges include a variably set number of data pieces for the respective parities. Each of the plurality of data pieces is included in a second predetermined number of compensation ranges.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: February 6, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Takanori Nakao
  • Patent number: 9843674
    Abstract: A card computing device may include and manage multiple virtualized universal integrated circuit cards (UICCs) for use with mobile communications. The card computing device may be capable of storing information, and executing applications, for multiple mobile networks (e.g., using multiple virtual UICCs) and of managing switches among those mobile networks. A mobile network operator (MNO) may be represented by a MNO profile, which, when enabled, may look and behave like a dedicated UICC. One or more applications may be deployed on the card computing device and each may be associated with a MNO profile. When a MNO profile is enabled, one or more applications may be activated and when a MNO profile is disabled, one or more active applications may be deactivated, according to some embodiments. Thus, a card computing device may be configured to activate and deactivate applications as part of managing MNO profiles.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: December 12, 2017
    Assignee: Oracle International Corporation
    Inventor: Sebastian J. Hans
  • Patent number: 9798491
    Abstract: A semiconductor system may include a plurality of memory devices corresponding to a plurality of channels, an address mapping unit suitable for converting addresses corresponding to provided external requests according to a selected address map among a plurality of address maps; a monitoring unit suitable for monitoring the external requests provided to each of the plurality of channels, and a control unit suitable for providing a control signal for controlling the address mapping unit to select an address map according to a result of the monitoring.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: October 24, 2017
    Assignee: SK Hynix Inc.
    Inventors: Kyung-Min Lee, Young-Suk Moon
  • Patent number: 9793922
    Abstract: Techniques for generating parities and repairing data erasures using repair-optimal parities are disclosed. The system includes an encoding module, which receives a request to recreate data for a subset of a plurality of content stores. The encoding module generates a new first parity and a new second parity using a subset of remaining content from the plurality of content stores. The encoding module generates a first portion of the requested data using the new first parity and a first subset of an original first parity for the plurality of content stores and a second portion of the requested data using the new second parity and a second subset of an original second parity for the plurality of content stores. The encoding module may recreate the data for the content store using the first portion of the requested data and the second portion of requested data.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: October 17, 2017
    Assignee: HGST Netherlands B.V.
    Inventors: Robert Mateescu, Lluis Pamies-Juarez, Cyril Guyot
  • Patent number: 9697147
    Abstract: A processing system comprises one or more processor devices and other system components coupled to a stacked memory device having a set of stacked memory layers and a set of one or more logic layers. The set of logic layers implements a metadata manager that offloads metadata management from the other system components. The set of logic layers also includes a memory interface coupled to memory cell circuitry implemented in the set of stacked memory layers and coupleable to the devices external to the stacked memory device. The memory interface operates to perform memory accesses for the external devices and for the metadata manager. By virtue of the metadata manager's tight integration with the stacked memory layers, the metadata manager may perform certain memory-intensive metadata management operations more efficiently than could be performed by the external devices.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: July 4, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gabriel H. Loh, James M. O'Connor, Bradford M. Beckmann, Michael Ignatowski
  • Patent number: 9654143
    Abstract: Embodiments of an invention for consecutive bit error detection and correction are disclosed. In one embodiment, an apparatus includes a storage structure, a second storage structure, a parity checker, an error correction code (ECC) checker, and an error corrector. The first storage structure is to store a plurality of data values, a plurality of parity values, and a plurality of ECC values, each parity value corresponding to one of the plurality of data values, a first bit of each parity value corresponding to a first of a plurality of portions of a corresponding data value, wherein the first of the plurality of portions of the corresponding data value is interleaved with a second of the plurality of portions of the corresponding data value, wherein a second bit of each parity value corresponds to a second of the plurality of portions of the corresponding data value, each ECC value corresponding to one of the plurality of data values.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Guillem Sole, Roger Espasa, Sorin Iacobovici, Brian Hickmann, Wei Wu, Thomas Fletcher
  • Patent number: 9612272
    Abstract: An ATE system performs RA over NAND flash memory DUTs. A first UBM captures fresh failure related data from a DUT. A second UBM transmits existing failure related data. A fail engine accesses the stored existing failure related data and generates a failure list based thereon. The storing and the accessing the existing failure related data, and/or the generating the failure list, are performed in parallel contemporaneously in relation to the capturing the fresh data. The generated failure list is queued. A failure processor, which may be operable for controlling the capturing, computes a redundancy analysis based on the queued failure list. The first and second UBMs then ping-pong operably.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: April 4, 2017
    Assignee: ADVANTEST CORPORATION
    Inventors: Xinguo Zhang, Michael Jones, Ken Hanh Duc Lai, Edmundo De La Puente, Alan S. Krech, Jr.
  • Patent number: 9575806
    Abstract: A method of an aspect includes running a plurality of threads on a plurality of thread processors. Memory accesses, of a thread of the plurality that is running on a first thread processor of the plurality, are monitored to both a first memory through a first memory controller and a second memory through a second memory controller. A second thread processor of the plurality is selected for a thread based on the monitoring of the memory accesses of the thread to both the first memory and the second memory. Installation of the thread, for which the second thread processor was selected, is initiated on the second thread processor. Other methods, apparatus, and systems are also disclosed.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: February 21, 2017
    Assignee: Intel Corporation
    Inventors: Ren Wang, Ling Ma, Ahmad Samih, Zhaojuan Bian
  • Patent number: 9575851
    Abstract: A computer implemented method, system, and computer program product for non-disruptively moving a replicated volume from a first storage medium to a second storage medium, the method comprising notifying a first data protection appliance that the replicated volume is moving from a first storage medium to a second storage medium; setting a replication connection between second volume and target of the first volume while maintaining replication connection from first volume to target of the first volume.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: February 21, 2017
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Assaf Natanzon, Saar Cohen
  • Patent number: 9563507
    Abstract: A method begins by a processing module storing a set of encoded data slices in storage units. A data segment of data is encoded, in accordance with dispersed storage error encoding parameters, to produce the set of encoded data slices. The dispersed storage error encoding parameters include a decode threshold number and a pillar width number, which is at least twice the decode threshold number. The method continues with the processing module processing a first request for retrieval of the data segment by retrieving a first sub-set of encoded data slices, which includes the decode threshold number, and decoding them to produce a first recovered data segment. The method continues with the processing module processing a second request for retrieval of the data segment by retrieving a second sub-set of encoded data slices, which includes the decode threshold number, and decoding them to produce a second recovered data segment.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: February 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Greg Dhuse, Ilya Volvovski, Zachary J. Mark, Sebastien Vas, Andrew Baptist
  • Patent number: 9563501
    Abstract: A method includes detecting that a first device in a memory array has degraded, the first device storing a portion of a data record, wherein the data record is encoded using a first error control technique. The method continues with recovering the data record using portions of the data record stored in devices other than the first device in the memory array and encoding the data record using a second error control technique. The method also includes storing the data record in the devices of the memory array other than the first device.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: February 7, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Christopher Bueb, Sean Eilert